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Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance
Superlattices and Microstructures 111 (2017) 123e133
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Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance Dharmendra Singh Yadav*, Abhishek Verma, Dheeraj Sharma, Sukeshni Tirkey, Bhagwan Ram Raad Nanoelectronics and VLSI Lab, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 26 January 2017 Received in revised form 3 June 2017 Accepted 6 June 2017 Available online 9 June 2017
Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION ). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION ) and decrement of ambipolar conduction (Iambi ) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit. © 2017 Elsevier Ltd. All rights reserved.
Keywords: Charge plasma Band to band tunneling Ambipolar conduction Work function engineering Sub-threshold swing Gate to drain capacitance
1. Introduction The incessant downsizing of device according to Moore's law has arisen as the most important factor in electronic systems due to the need of compactness and larger density of transistors in the integrated circuits. In this regard, scaling of MOSFET has been carried out continuously for past few decades which has significantly brought down the cost and provided compactness in devices [1]. Along with this, it also led to enhancement in current driving capability with high operational speed and better high frequency performance. This continuous scaling also leads to some adverse effects on the device such as increment in the leakage current, short channel effects (SCEs), drain induced barrier lowering (DIBL) and excessive power consumption [2]. Power consumption in electronic systems needs to be reduced in a significant manner to prevent from
* Corresponding author. E-mail addresses: [email protected] (D.S. Yadav), [email protected] (A. Verma), [email protected] (D. Sharma), [email protected] (S. Tirkey), [email protected] (B.R. Raad). http://dx.doi.org/10.1016/j.spmi.2017.06.016 0749-6036/© 2017 Elsevier Ltd. All rights reserved.
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future power crisis. The dissipation of power in the devices are dynamic and static in nature and are given by the following expressions (1) and (2)
Pstatic ¼ Ileakage Vdd
(1)
2 Pdynamic ¼ Ctotal Vdd f
(2)
where Pstatic is static power, Pdynamic is dynamic power, Ileakage is leakage current, Vdd is drain voltage, Ctotal is total parasitic capacitance and f is frequency of operation [3]. To reduce the power consumption, the scaling down of supply voltage (Vdd ) can be a solution (according to expression (1)), but with this scaling of (Vdd ), current driving capability of the device gets reduced which can be realized by the expression (3) as given below
IdðsatÞ ¼ KCox ðVdd Vth Þa
(3)
where IdðsatÞ is drain current in saturation state, K is the proportionality constant, a is fitting parameter (ranges between 1 and 2 which depends on channel length), Cox is oxide capacitance, and Vth is threshold voltage. To maintain higher Ids, Vth also needs to be scaled down proportionally along with Vdd . However, the scaling of Vth with Vdd is a challenging task beyond a certain extent in case of conventional MOSFET due to the limitation of subthreshold swing (SS 60 mV/decade) [2], as it increases the OFF-state current (IOFF ) of the device as per the relation given by expression (4)
IOFF ¼ Ids 10Vth =SS
(4)
here, IOFF is OFF-state current and Ids is drain to source current [4]. In order to overcome the limitations of MOSFET as mentioned above, a novel device TFET based on the quantum tunneling phenomena has appeared as an alternative of conventional MOSFET [5,6]. This quantum tunneling mechanism of TFET offers the ability to be operated at ultra low supply voltage with lower Vth and provides immunity against short channel effects (SCEs) and drain induced barrier lowering (DIBL). Along with this, it offers low leakage current in the order of femto ampere (fA) which helps in reduction of dynamic as well as static power consumption of the device [7]. Apart from these, it also provides SS lower than conventional MOSFET and has a further possibility to reduce the same beyond 60 mV/decade [5]. However, TFET shows various disadvantages such as ambipolar conduction (Iambi ), low ON-state current (ION ) and poor radio frequency (RF) performances [5e7]. In addition to these, fabrication of nano scale devices (ultra thin highly doped source and drain region) and Random dopant fluctuation (RDF) are major problems in physically doped TFETs [8,9]. In this concern, doping less TFET (DL TFET) is reported in the recent literature where the formation of n þ drain and the p þ source region is done by using metal electrodes with appropriate work function which simplifies the fabrication process, reduces RDF and lowers down the cost of device [10]. Although, the low ON-state current is still a severe problem in the case of Doping-less TFET (DL TFET) due to the presence of a barrier between the gate and source electrode over the silicon body [10]. However, the issue of ambipolar conduction remains for both the devices (physically doped TFET and Doping-less TFET (DL TFET)) [5e7], [10]. Therefore, to overcome these challenges of ambipolarity, low ON-state current and poor RF performance, various methods have been reported such as (i) Gaussian drain doping [11] (ii) band gap engineering [12] (iii) drain overlapping [13] (iv) gate under lapping [14] (v) gate work function engineering [15] (vi) drain engineering [16] and (vii) gate dielectric engineering [17,18]. Although, the physical realization of gaussian doping in drain region (needed to suppress ambipolar nature and improve RF performance) is very complex and it is not feasible in case of doping less devices [10,11]. In this regard, band gap engineering is used where the presence of wide band gap material at the drain and channel region reduces the ambipolar conduction and low band gap material in source region enhance the ON-state current [12] leading to improvement in high frequency performances. Even though it enhances the device performance, it also suffers from lattice mismatch and complex surface passivation of two different materials. Apart from these, a large capital investment is required to replace the existing silicon based technology. The use of gate electrode over the drain region suppresses the ambipolar behavior at the cost of poor RF performance due to increment in the gate to drain capacitance [13]. In this concern, the underlapping of gate electrode improves high frequency performance along with significant reduction in ambipolarity [14]. In addition to these, the presence of dual work functionality at the gate electrode [15], drain electrode [16] and hetero gate dielectric [17,18] are useful for providing improvement in terms of suppression of ambipolar behavior and high frequency figure of merits but up to a limited extent. Hence, in this paper, the integrated effort of dual work functionality at gate and drain electrode with hetero gate dielectric engineering is incorporated in doping less device with existing silicon based technology for achieving the overall improvement in terms of DC characteristics (ION , IOFF , SS, and Vth ) and RF figure of merits (Cgd , fT , gm , GBP). The arrangement of content in rest of the paper is as follows: Section 2 describes computational details along with device schematics and parameters followed by simulation models. Section 3 demonstrates the TCAD Results and Discussion where a detailed DC analysis has been analyzed along with Analog/Radio Frequency (RF) performances. Effect of gate and drain electrode length variation shown in Section 4. Finally, the impactful findings of the paper are enlightened as conclusion in Section 5.
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2. Device structure and simulation setup Cross sectional views of all the devices considered in this paper are shown in Fig. 1(aee). It has conventional doping less TFET (Fig. 1(a)), Drain engineered doping-less (DE DL) TFET (Fig. 1(b)), Dual metal gate doping-less (DMG DL) TFET (Fig. 1(c)), Drain engineered dual metal gate doping-less (DE DMG DL) TFET (Fig. 1(d)) and Hetero gate dielectric drain engineered dual metal gate doping-less (HGD DE DMG DL) TFET (Fig. 1(e)). The formation of n þ drain and p þ source regions are created by inducing plasma of charge using metal electrodes of different work functions [10] [16]. The design parameters of charge plasma DL TFET are as follows: Drain metal electrode length (LD ) of 50 nm with work function (fR1 ) of 3.9 eV is used in DL TFET (Fig. 1(a)) and DMG DL TFET (Fig. 1 (c)), whereas drain metal electrode length (LD ) of 40 nm with work function (fR1 ) of 3.9 eV is used in DE DL TFET (Fig. 1(b)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Extended drain metal electrode length (LB ) of 10 nm with work function (fR4 ) of 4.3 eV is used in DE DL TFET (Fig. 1(b)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Gate metal electrode length (LG ) of 50 nm with work function(fR2 ) of 4.6 eV is used in DL TFET (Fig. 1(a)) and DE DL TFET (Fig. 1(b)), whereas gate metal electrode length (LG ) of 40 nm with work function (fR2 ) of 4.6 eV is used in DMG DL TFET (Fig. 1(c)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Extended gate metal electrode length (LC ) of 10 nm with work function (fR5 ) of 4.0 eV is used in DMG DL TFET (Fig. 1(c)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Source metal electrode length (LS ) of 50 nm with work function (fR3 ) of 5.93 eV, silicon thickness (tsi ) of 10 nm, oxide thickness (tox ) of 1 nm is considered for both SiO2 and HfO2, drain/channel gap (LDC ) and source/channel gap (LSC ) of 5 nm and 2 nm are considered respectively for all devices of Fig. 1. 2-D ATLAS device simulator (ATLAS 2.18.19R) [19] is used to execute the simulation of all the devices. TCAD model is used for the operation and performance analysis of the device. For the evaluation of tunneling generation and recombination rate, nonlocal BTBT model with Trap-assisted tunneling model is employed [5e7]. Few more models like Fermi-Dirac, Band gap narrowing model, Shockley-Read-Hall (SRH) recombination, concentration dependent mobility, Auger recombination and field dependent mobility models are also incorporated for more precise and accurate simulation. Wentzel-Kramers-Brillouin (WKB) method is used for calculating tunneling probability and numerical solutions [19]. 3. Results and discussion 3.1. DC analysis This manuscript shows the effect of drain and gate work function engineering with hetero gate dielectric in the doping less TFET. The whole DC analysis is inspected in terms of band gap difference at the junction. The energy band diagrams
Fig. 1. Device Structures: (a) Doping-less (DL) TFET (conventional), (b) drain engineered doping-less (DE DL) TFET, (c) dual metal gate doping-less (DMG DL) TFET, (d) drain engineered dual metal gate doping-less (DE DMG DL) TFET and (e) hetero gate dielectric drain engineered dual metal gate doping-less (HGD DE DMG DL) TFET (proposed device).
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corresponding to OFF-state and ON-state are shown in Fig. 2 and Fig. 3 respectively for all the structures, where it is observed that structures comprising of the dual metal gate (DMG) show larger band bending at the source/channel interface. Whereas, the band bending in case of an ambipolar state is almost similar in both the devices (DE DMG DL TEFT and HDG DE DMG DL TFET) as shown in Fig. 4. HGD DE DMG DL TFET (proposed device) has the most shrinkage in bands at the source/ channel junction among all due to the presence of work function engineering as well as hetero gate dielectric engineering for both OFF and ON states (Figs. 2 and 3), which allows huge amount of electrons to tunnel easily from source to channel region. This can be also realized by the charge carrier concentration under thermal equilibrium condition as shown in Fig. 5 where it is noticed that abruptness is created at the source/channel interface which in turn provides shrinkage of energy bands at the source/channel junction as discussed earlier in Fig. 3. The effect in the electric field due to variation in band gap for all the structures considered is shown in Fig. 6. For this, we have shown the electric field under thermal equilibrium of all the devices. The spike of an electric field at source/channel interface is quite high relative to drain/channel interface, which accelerates the electrons at the source/channel interface to cross the band gap (valence band to conduction band) following the tunneling mechanism and reach towards the drain end. The maximum electric field at source/channel interface is observed in the case of HGD DE DMG DL TFET due to integrated effect of dual metal work function at gate electrode and presence of hetero gate dielectric. Whereas, the use of dual work functionality at drain electrode increases the hole concentration and decreases the electron concentration under the drain metal electrode length (LB ) (Fig. 5) which results in lowest electric field at the drain/channel interface in case of DE DL TFET, DE DMG DL TFET and HGD DE DMG DL TFET. The comparative analysis of transfer characteristic for all the structures (Fig. 1) under the ON-state, OFF-state, and ambipolar state is shown in Fig. 7, here the ON-state current is proportional to the transmission probability of electron/hole using band to band tunneling mechanism (BTBT) [20,21], which is given by equation (5)
TðEÞzexp
pffiffiffiffiffiffiffiffiffi 3=2 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ! 4 2m Eg εsi tox tSi εox 3 e Z Eg þ Df
(5)
here m stands for the carrier effective mass, Eg stands for the bandgap, e for the electron charge, Df stands for the energy range where tunneling is taking place. tox , tSi , εSi and εox are the oxide, silicon thickness and dielectric constants respectively [22]. The BTBT tunneling transmission helps to overcome the limit of a subthreshold slope of 60 mV/decade providing steeper transfer characteristic. The Ids -Vgs curve for all the device structures is depicted in Fig. 7. The ambipolarity of the device has been reduced significantly in HGD DE DMG DL TFET (proposed device) in comparison to other structures. Along with all the device characteristics, a comparative analysis of threshold voltage (Vth ) is performed for all the devices and found that Vth for proposed device HGD DE DMG DL TEFT is 1.7 times less than conventional charge plasma DL TFET and 1.22 times lesser than DE DMG DL TFET (Fig. 8). These figures are calculated by constant current method (Ids ¼ 107 A=mmÞ) [22]. 3.2. Analog/radio frequency (RF) analysis The study of high frequency responses are essential while dealing with charge plasma TFET. The analysis of the same are shown in terms of the gate to drain capacitance (Cgd ), transconductance (gm ), cut-off frequency (fT ) and gain bandwidth product (GBP). Parasitic capacitances are responsible for the degradation in RF performance of the device.
Fig. 2. Energy band diagram in OFF-state condition for different configuration of charge plasma TFETs.
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Fig. 3. Energy band diagram in ON-state condition for different configuration of charge plasma TFETs.
Total gate capacitance (Cgg ) is majorly contributed by Cgd due to the lower potential drop between channel and drain in TFETs as compared to large negative bias between channel and drain in the case of MOSFETs [23]. Higher Cgd and lower Cgs in the case of TFETs can be also realized by the lower channel to drain barrier resistance and larger source to channel barrier resistance respectively which makes Cgd more dominating [23]. Therefore, Cgd need to be reduced to achieve higher RF performance. The variation in Cgd is shown in Fig. 9 where Cgd increases with gate bias due to the presence of larger barrier at the drain/channel interface. Cgd is lower for the structures comprising of drain engineering whereas for the proposed device HGD DE DMG DL TEFT it increases to a little extent due to the effect of hetero gate dielectric, but it remains much lower than that of DL TFET and DMG DL TFET. Transconductance (gm ) is another important parameter to analyze the RF performance, which shows the rate of change of drain current with respect to the gate voltage. Fig. 10 shows the gm of all the devices where it is observed that HGD DE DMG DL TFET device has attained highest peak at the lower voltage (Vgs ) and drops at higher voltages due to mobility degradation. Here, the presence of HfO2 as a gate dielectric material near the source side with low gate work function (fR5 ) of 4.0 eV is used towards source end which provides better coupling of gate at source/channel interface, it also reduces the barrier at source/ channel interface which is responsible for enhancement of electric field and tunneling of carriers at source/channel interface. It results in better performance in terms of ON state current and gm with respect to other device. Apart from theses it is also responsible to achieve maximum electric field at lower gate to source voltage which results into degradation of mobility at low gate to source voltage in comparison to other devices. Other crucial parameters for RF analysis are fT and GBP, here fT is the transient frequency where the current gain of the device become unity and GBP is the measure of the device performance in high frequency ranges calculated at DC gain of 10. Both the parameters fT and GBP are calculated by using equations (6) and (7).
fT ¼
g m 2p Cgd þ Cgs
(6)
g m 2p Cgd
(7)
GBP ¼
Fig. 11 and Fig. 12 shows fT and GBP responses, where it is noticed that fT for HGD DE DMG DL TFET is significantly improved as compared to other devices (Fig. 11) at the lower voltage because of the combined effect of higher gm and lower Cgd . Now, looking at Fig. 12, it can be inferred that GBP for the proposed device is higher among all other devices. Thus, it is ensured that proposed modification done in DL TFET is beneficial for ultra low power and high frequency circuit applications. 4. Effect of gate and drain electrode length variation for HGD DE DMG DL TFET Selecting the optimized lengths (LB and LC ) and proper work function (fR4 and fR5 ) plays a very crucial role which is observed in the case of ON-state current, OFF-state current and threshold voltage/subthreshold swing. Therefore, the effect of length variation of electrodes with different values of work function (fR4 and fR5 ) is shown as follows: 4.1. Length (LC ) variation of gate metal electrode with variation in work function (fR5 ) values.
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Fig. 4. Energy band diagram in ambipolar condition for different configuration of charge plasma TFETs.
Fig. 5. Carrier concentration in Thermal equilibrium state for different configuration of charge plasma TFETs.
Fig. 6. Electric field in thermal equilibrium condition for different configuration of charge plasma TFETs.
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Fig. 7. Ids -Vgs characteristic of charge plasma TFETs.
Fig. 8. Threshold Voltage for different configuration of charge plasma TFETs.
Fig. 9. Gate to drain capacitance of charge plasma TFET's.
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Fig. 10. Transconductance for different configuration of charge plasma TFETs.
Fig. 11. ft vs Vgs curve for different configuration of charge plasma TFETs.
Fig. 12. Gain bandwidth product for different configuration of charge plasma TFETs.
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Fig. 13. Variation of device parameter with the fR5 for proposed device (HGD DE DMG DL TFET) (a) ON-state current, (b) OFF-state current and (c) Sub threshold swing.
4.2. Length (LB ) variation of drain metal electrode with variation in work function (fR4 ) values. In both the subsections, LB and LC are varied from 5 to 15 nm at a step size of 5 nm. 4.1. Length (LC ) variation of gate metal electrode with variation in work function (fR5 ) values Gate metal electrode length and work function engineering mostly effects the ON-state current, OFF-state current and SS, which is shown in Fig. 13(a), (b) and(c) respectively. The increment in length (LC ) of gate electrode significantly increases the ON-state current in the proposed device. Fig. 13(a) shows, ON-state current with respect to the work function (fR5 ) at distinct LC where it is notified that LC ¼ 15 nm provides better ON-state current. OFF-state current against (fR5 ) at different (LC ) is shown in Fig. 13(b) where it can be seen that (IOFF ) for (LC ) ¼ 5 and 10 nm is almost same and (LC ) increases beyond 10 nm it shows increment in (IOFF ). Thus, from Fig. 13(a) and (b) it is inferred that (LC ) ¼ 10 nm is optimized for maintaining trade off between (ION ) and (IOFF ). Effect of length (LC ) and work function (fR5 ) variation on the SS is shown in Fig. 13(c), which illustrates that lower value of SS i.e. 7.5 mV is achieved for LC 10 nm at fR5 ¼ 4.1 eV. 4.2. Length (LB ) variation of drain metal electrode with variation in work function (fR4 ) values The response in ON-state current ambipolar conduction and SS with variation in drain metal electrode length (LB ) and work function (fR4 ) over drain metal electrode is shown in Fig. 14(a), (b) and (c) respectively. Variation in ON-state current with respect to fR4 at different LB (Fig. 14(a)) depicts that ION increases with a decrease in length LB . Now from Fig. 14(b) it is observed that the ambipolar current increases with the decrease in drain metal electrode length (LB ) and for LB ¼ 5 nm, ambipolar current is obtained in order of 1013 A=mm. LB ¼ 15 nm is most appropriate drain electrode length for obtaining the reduced ambipolar current, but LB ¼ 15 nm is not chosen because of its limitation in obtaining a good response in ON-state
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Fig. 14. Variation of device parameter with the fR4 for proposed device (HGD DE DMG DL TFET) (a) ON-state current, (b) Ambipolar current and (c) Sub threshold swing.
current. SS decreases with a decrease in LB and the lowest value of SS is achieved at fR4 ¼ 4.0 eV as illustrated in Fig. 14(c). Hence, by analyzing Fig. 14(a), (b) and (c) it is found that LB ¼ 10 nm is the optimized value for achieving the better response in ON-state current and OFF-state current and steep sub-threshold swing. 5. Conclusion In this paper, the improvement in terms of ON/OFF-state current, ambipolar behavior and RF performance have been shown by the use of dual work functionality at drain and gate electrode with hetero gate dielectric for the proposed device (HGD DE DMG DL TFET). For this, extensive analysis of various charge plasma TFETs are performed with the help of 2D ATLAS simulation. HGD DE DMG DL TFET shows better performance with respect to other charge plasma TFETs. The cutoff frequency of proposed device is 1.65 times larger than the DE DMG DL TFET. The hetero gate dielectric and drain metal engineering plays a significant role in the improvement of ION =IOFF ratio (1011 ) and threshold voltage (1.7 times lesser than the DL TFET and 1.22 times less than DE DMG DL TFET in the case of proposed device). The parameters fT and GBP have attained its peak at low Vgs. Thus, the proposed device provides high operational speed and can be efficiently used for ultra low power applications. References [1] International Technology Roadmaps for Semiconductor, 2012 [Online]. Available: http://itrs.net. [2] J.P. Colinge, FinFETs and Other Multi-gate Transistors, Springer, New York, NY, USA, 2008. [3] H.J.M. Veendrick, Short-Circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE J. Solid-State Circuits, sc 17 (4) (Aug. 1984) 468e473. [4] R. Asra, M. Shrivastava, K.V.R.M. Murali, R.K. Pandey, H. Gossner, V.R. Rao, A tunnel FET for VDD scaling below 0.6 V with a CMOS-Comparable performance, IEEE Trans. Electron Devices 58 (7) (Jul. 2011) 1855e1863.
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[5] W.Y. Choi, B.G. Park, J.D. Lee, T.J.K. Liu, Tunneling field-effect transistor (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Trans. Electron Devices 28 (8) (Aug. 2007) 743e745. [6] K. Boucart, A.M. Ionescu, Double gate tunnel FET with high-k gate dielectric, IEEE Trans. Electron Devices 54 (7) (Jul. 2007) 1725e1733. [7] A.M. Ionescu, H. Riel, Tunnel field-effect transistors as energy-efficient electronic switches, Nature 479 (2011) 329e337, http://dx.doi.org/10.1038/ nature10679. [8] N. Damrongplasit, C. Shin, S.H. Kim, R.A. Vega, T.J.K. Liu, Study of random dopant fluctuation effects in germanium-source tunnel FETs, IEEE Trans. Electron Devices 58 (10) (Oct. 2011) 3541e3548. [9] N. Damrongplasit, S.H. Kim, T.J.K. Liu, Study of random dopant fluctuation induced variability in the raised-Ge-source TFET, IEEE Electron Device Lett. 34 (2) (Feb. 2013) 184e186. [10] M.J. Kumar, S. Janardhanan, Doping-less tunnel field effect transistor: design and investigation, IEEE Trans. Electron device 60 (10) (Oct. 2013) 3285e3290. [11] V. Vijayvargiya, S.K. Vishvakarma, Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance, IEEE Trans. Nano Technol. 13 (5) (Sep. 2014) 974e981. [12] S. Mookerjea, S. Datta, Band-gap engineered hot carrier tunnel transistors, in: Proc. Device Res. Conf University Park, PA, USA, 2009, pp. 121e122a. [13] D.B. Abdi, M.J. Kumar, Controlling ambipolar current in tunneling FETs using overlapping gate-to-drain, IEEE J. Electron Device Soc. 2 (6) (Nov. 2014) 187e190. [14] D.S. Yadav, D. Sharma, B.R. Raad, V. Bajaj, Impactful study of dual work function, underlap and hetero gate dielectric on TFET with different drain doping profile for high frequency performance estimation and optimization, Superlattices Microstruct. 96 (Aug. 2016) 36e46. [15] S. Saurabh, M.J. Kumar, Novel attributes of dual material gate nanoscale tunel field effect transistor, IEEE Trans. Electron device 58 (2) (Feb. 2011) 404e410. [16] B.R. Raad, D. Sharma, P. Kondekar, K. Nigam, D.S. Yadav, Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: a proposal, design, and investigation, IEEE Trans. Electron device 63 (10) (Oct. 2016) 3950e3957. [17] M.J. Lee, W.Y. Choi, Effects of device geometry on hetero-gate-dielectric tunneling field-effect transistors, IEEE Electron Device Lett. 33 (10) (Oct. 2012) 1459e1461. [18] W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field effect transistors, IEEE Trans. Electron Devices 57 (9) (Sep. 2010) 2317e2319. [19] Santa Clara, ATLAS Device Simulation Software, Silvaco Int., CA, USA, 2014. [20] J. Appenzeller, Y.-M. Lin, J. Knoch, P. Avouris, Band-to-band tunneling in carbon nanotube field-effect transistors, Phys. Rev. Lett. 93 (19) (Nov. 2004) 196e805. [21] M. Luisier, G. Klimeck, Atomistic full-band design study of InAs band-to-band tunneling field-effect transistors, IEEE Electron Device Lett. 30 (6) (Jun. 2009) 602e604. [22] J. Knoch, J. Appenzeller, A novel concept for field effect transistors the tunneling carbon nanotube FET, Proc. 63rd DRC 1 (Jun. 2005) 153e158. [23] S. Mookerjea, R. Krishnan, S. Datta, V. Narayanan, On enhanced Miller capacitance effect in interband tunnel transistors, IEEE Electron Device Lett. 30 (10) (Oct. 2009) 1102e1104.
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Superlattices and Microstructures journal homepage: www.elsevier.com/locate/superlattices
Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance Dharmendra Singh Yadav*, Abhishek Verma, Dheeraj Sharma, Sukeshni Tirkey, Bhagwan Ram Raad Nanoelectronics and VLSI Lab, Electronics and Communication Engineering Discipline, PDPM-Indian Institute of Information Technology, Jabalpur, 482005, India
a r t i c l e i n f o
a b s t r a c t
Article history: Received 26 January 2017 Received in revised form 3 June 2017 Accepted 6 June 2017 Available online 9 June 2017
Tunnel-field-effect-transistor (TFET) has emerged as one of the most prominent devices to replace conventional MOSFET due to its ability to provide sub-threshold slope below 60 mV/decade (SS 60 mV/decade) and low leakage current. Despite this, TFETs suffer from ambipolar behavior, lower ON-state current, and poor RF performance. To address these issues, we have introduced drain and gate work function engineering with hetero gate dielectric for the first time in charge plasma based doping-less TFET (DL TFET). In this, the usage of dual work functionality over the drain region significantly reduces the ambipolar behavior of the device by varying the energy barrier at drain/channel interface. Whereas, the presence of dual work function at the gate terminal increases the ON-state current (ION ). The combined effect of dual work function at the gate and drain electrode results in the increment of ON-state current (ION ) and decrement of ambipolar conduction (Iambi ) respectively. Furthermore, the incorporation of hetero gate dielectric along with dual work functionality at the drain and gate electrode provides an overall improvement in the performance of the device in terms of reduction in ambipolarity, threshold voltage and sub-threshold slope along with improved ON-state current and high frequency figures of merit. © 2017 Elsevier Ltd. All rights reserved.
Keywords: Charge plasma Band to band tunneling Ambipolar conduction Work function engineering Sub-threshold swing Gate to drain capacitance
1. Introduction The incessant downsizing of device according to Moore's law has arisen as the most important factor in electronic systems due to the need of compactness and larger density of transistors in the integrated circuits. In this regard, scaling of MOSFET has been carried out continuously for past few decades which has significantly brought down the cost and provided compactness in devices [1]. Along with this, it also led to enhancement in current driving capability with high operational speed and better high frequency performance. This continuous scaling also leads to some adverse effects on the device such as increment in the leakage current, short channel effects (SCEs), drain induced barrier lowering (DIBL) and excessive power consumption [2]. Power consumption in electronic systems needs to be reduced in a significant manner to prevent from
* Corresponding author. E-mail addresses: [email protected] (D.S. Yadav), [email protected] (A. Verma), [email protected] (D. Sharma), [email protected] (S. Tirkey), [email protected] (B.R. Raad). http://dx.doi.org/10.1016/j.spmi.2017.06.016 0749-6036/© 2017 Elsevier Ltd. All rights reserved.
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future power crisis. The dissipation of power in the devices are dynamic and static in nature and are given by the following expressions (1) and (2)
Pstatic ¼ Ileakage Vdd
(1)
2 Pdynamic ¼ Ctotal Vdd f
(2)
where Pstatic is static power, Pdynamic is dynamic power, Ileakage is leakage current, Vdd is drain voltage, Ctotal is total parasitic capacitance and f is frequency of operation [3]. To reduce the power consumption, the scaling down of supply voltage (Vdd ) can be a solution (according to expression (1)), but with this scaling of (Vdd ), current driving capability of the device gets reduced which can be realized by the expression (3) as given below
IdðsatÞ ¼ KCox ðVdd Vth Þa
(3)
where IdðsatÞ is drain current in saturation state, K is the proportionality constant, a is fitting parameter (ranges between 1 and 2 which depends on channel length), Cox is oxide capacitance, and Vth is threshold voltage. To maintain higher Ids, Vth also needs to be scaled down proportionally along with Vdd . However, the scaling of Vth with Vdd is a challenging task beyond a certain extent in case of conventional MOSFET due to the limitation of subthreshold swing (SS 60 mV/decade) [2], as it increases the OFF-state current (IOFF ) of the device as per the relation given by expression (4)
IOFF ¼ Ids 10Vth =SS
(4)
here, IOFF is OFF-state current and Ids is drain to source current [4]. In order to overcome the limitations of MOSFET as mentioned above, a novel device TFET based on the quantum tunneling phenomena has appeared as an alternative of conventional MOSFET [5,6]. This quantum tunneling mechanism of TFET offers the ability to be operated at ultra low supply voltage with lower Vth and provides immunity against short channel effects (SCEs) and drain induced barrier lowering (DIBL). Along with this, it offers low leakage current in the order of femto ampere (fA) which helps in reduction of dynamic as well as static power consumption of the device [7]. Apart from these, it also provides SS lower than conventional MOSFET and has a further possibility to reduce the same beyond 60 mV/decade [5]. However, TFET shows various disadvantages such as ambipolar conduction (Iambi ), low ON-state current (ION ) and poor radio frequency (RF) performances [5e7]. In addition to these, fabrication of nano scale devices (ultra thin highly doped source and drain region) and Random dopant fluctuation (RDF) are major problems in physically doped TFETs [8,9]. In this concern, doping less TFET (DL TFET) is reported in the recent literature where the formation of n þ drain and the p þ source region is done by using metal electrodes with appropriate work function which simplifies the fabrication process, reduces RDF and lowers down the cost of device [10]. Although, the low ON-state current is still a severe problem in the case of Doping-less TFET (DL TFET) due to the presence of a barrier between the gate and source electrode over the silicon body [10]. However, the issue of ambipolar conduction remains for both the devices (physically doped TFET and Doping-less TFET (DL TFET)) [5e7], [10]. Therefore, to overcome these challenges of ambipolarity, low ON-state current and poor RF performance, various methods have been reported such as (i) Gaussian drain doping [11] (ii) band gap engineering [12] (iii) drain overlapping [13] (iv) gate under lapping [14] (v) gate work function engineering [15] (vi) drain engineering [16] and (vii) gate dielectric engineering [17,18]. Although, the physical realization of gaussian doping in drain region (needed to suppress ambipolar nature and improve RF performance) is very complex and it is not feasible in case of doping less devices [10,11]. In this regard, band gap engineering is used where the presence of wide band gap material at the drain and channel region reduces the ambipolar conduction and low band gap material in source region enhance the ON-state current [12] leading to improvement in high frequency performances. Even though it enhances the device performance, it also suffers from lattice mismatch and complex surface passivation of two different materials. Apart from these, a large capital investment is required to replace the existing silicon based technology. The use of gate electrode over the drain region suppresses the ambipolar behavior at the cost of poor RF performance due to increment in the gate to drain capacitance [13]. In this concern, the underlapping of gate electrode improves high frequency performance along with significant reduction in ambipolarity [14]. In addition to these, the presence of dual work functionality at the gate electrode [15], drain electrode [16] and hetero gate dielectric [17,18] are useful for providing improvement in terms of suppression of ambipolar behavior and high frequency figure of merits but up to a limited extent. Hence, in this paper, the integrated effort of dual work functionality at gate and drain electrode with hetero gate dielectric engineering is incorporated in doping less device with existing silicon based technology for achieving the overall improvement in terms of DC characteristics (ION , IOFF , SS, and Vth ) and RF figure of merits (Cgd , fT , gm , GBP). The arrangement of content in rest of the paper is as follows: Section 2 describes computational details along with device schematics and parameters followed by simulation models. Section 3 demonstrates the TCAD Results and Discussion where a detailed DC analysis has been analyzed along with Analog/Radio Frequency (RF) performances. Effect of gate and drain electrode length variation shown in Section 4. Finally, the impactful findings of the paper are enlightened as conclusion in Section 5.
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2. Device structure and simulation setup Cross sectional views of all the devices considered in this paper are shown in Fig. 1(aee). It has conventional doping less TFET (Fig. 1(a)), Drain engineered doping-less (DE DL) TFET (Fig. 1(b)), Dual metal gate doping-less (DMG DL) TFET (Fig. 1(c)), Drain engineered dual metal gate doping-less (DE DMG DL) TFET (Fig. 1(d)) and Hetero gate dielectric drain engineered dual metal gate doping-less (HGD DE DMG DL) TFET (Fig. 1(e)). The formation of n þ drain and p þ source regions are created by inducing plasma of charge using metal electrodes of different work functions [10] [16]. The design parameters of charge plasma DL TFET are as follows: Drain metal electrode length (LD ) of 50 nm with work function (fR1 ) of 3.9 eV is used in DL TFET (Fig. 1(a)) and DMG DL TFET (Fig. 1 (c)), whereas drain metal electrode length (LD ) of 40 nm with work function (fR1 ) of 3.9 eV is used in DE DL TFET (Fig. 1(b)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Extended drain metal electrode length (LB ) of 10 nm with work function (fR4 ) of 4.3 eV is used in DE DL TFET (Fig. 1(b)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Gate metal electrode length (LG ) of 50 nm with work function(fR2 ) of 4.6 eV is used in DL TFET (Fig. 1(a)) and DE DL TFET (Fig. 1(b)), whereas gate metal electrode length (LG ) of 40 nm with work function (fR2 ) of 4.6 eV is used in DMG DL TFET (Fig. 1(c)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Extended gate metal electrode length (LC ) of 10 nm with work function (fR5 ) of 4.0 eV is used in DMG DL TFET (Fig. 1(c)), DE DMG DL TFET (Fig. 1(d)) and HGD DE DMG DL TFET (Fig. 1(e)). Source metal electrode length (LS ) of 50 nm with work function (fR3 ) of 5.93 eV, silicon thickness (tsi ) of 10 nm, oxide thickness (tox ) of 1 nm is considered for both SiO2 and HfO2, drain/channel gap (LDC ) and source/channel gap (LSC ) of 5 nm and 2 nm are considered respectively for all devices of Fig. 1. 2-D ATLAS device simulator (ATLAS 2.18.19R) [19] is used to execute the simulation of all the devices. TCAD model is used for the operation and performance analysis of the device. For the evaluation of tunneling generation and recombination rate, nonlocal BTBT model with Trap-assisted tunneling model is employed [5e7]. Few more models like Fermi-Dirac, Band gap narrowing model, Shockley-Read-Hall (SRH) recombination, concentration dependent mobility, Auger recombination and field dependent mobility models are also incorporated for more precise and accurate simulation. Wentzel-Kramers-Brillouin (WKB) method is used for calculating tunneling probability and numerical solutions [19]. 3. Results and discussion 3.1. DC analysis This manuscript shows the effect of drain and gate work function engineering with hetero gate dielectric in the doping less TFET. The whole DC analysis is inspected in terms of band gap difference at the junction. The energy band diagrams
Fig. 1. Device Structures: (a) Doping-less (DL) TFET (conventional), (b) drain engineered doping-less (DE DL) TFET, (c) dual metal gate doping-less (DMG DL) TFET, (d) drain engineered dual metal gate doping-less (DE DMG DL) TFET and (e) hetero gate dielectric drain engineered dual metal gate doping-less (HGD DE DMG DL) TFET (proposed device).
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corresponding to OFF-state and ON-state are shown in Fig. 2 and Fig. 3 respectively for all the structures, where it is observed that structures comprising of the dual metal gate (DMG) show larger band bending at the source/channel interface. Whereas, the band bending in case of an ambipolar state is almost similar in both the devices (DE DMG DL TEFT and HDG DE DMG DL TFET) as shown in Fig. 4. HGD DE DMG DL TFET (proposed device) has the most shrinkage in bands at the source/ channel junction among all due to the presence of work function engineering as well as hetero gate dielectric engineering for both OFF and ON states (Figs. 2 and 3), which allows huge amount of electrons to tunnel easily from source to channel region. This can be also realized by the charge carrier concentration under thermal equilibrium condition as shown in Fig. 5 where it is noticed that abruptness is created at the source/channel interface which in turn provides shrinkage of energy bands at the source/channel junction as discussed earlier in Fig. 3. The effect in the electric field due to variation in band gap for all the structures considered is shown in Fig. 6. For this, we have shown the electric field under thermal equilibrium of all the devices. The spike of an electric field at source/channel interface is quite high relative to drain/channel interface, which accelerates the electrons at the source/channel interface to cross the band gap (valence band to conduction band) following the tunneling mechanism and reach towards the drain end. The maximum electric field at source/channel interface is observed in the case of HGD DE DMG DL TFET due to integrated effect of dual metal work function at gate electrode and presence of hetero gate dielectric. Whereas, the use of dual work functionality at drain electrode increases the hole concentration and decreases the electron concentration under the drain metal electrode length (LB ) (Fig. 5) which results in lowest electric field at the drain/channel interface in case of DE DL TFET, DE DMG DL TFET and HGD DE DMG DL TFET. The comparative analysis of transfer characteristic for all the structures (Fig. 1) under the ON-state, OFF-state, and ambipolar state is shown in Fig. 7, here the ON-state current is proportional to the transmission probability of electron/hole using band to band tunneling mechanism (BTBT) [20,21], which is given by equation (5)
TðEÞzexp
pffiffiffiffiffiffiffiffiffi 3=2 rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ! 4 2m Eg εsi tox tSi εox 3 e Z Eg þ Df
(5)
here m stands for the carrier effective mass, Eg stands for the bandgap, e for the electron charge, Df stands for the energy range where tunneling is taking place. tox , tSi , εSi and εox are the oxide, silicon thickness and dielectric constants respectively [22]. The BTBT tunneling transmission helps to overcome the limit of a subthreshold slope of 60 mV/decade providing steeper transfer characteristic. The Ids -Vgs curve for all the device structures is depicted in Fig. 7. The ambipolarity of the device has been reduced significantly in HGD DE DMG DL TFET (proposed device) in comparison to other structures. Along with all the device characteristics, a comparative analysis of threshold voltage (Vth ) is performed for all the devices and found that Vth for proposed device HGD DE DMG DL TEFT is 1.7 times less than conventional charge plasma DL TFET and 1.22 times lesser than DE DMG DL TFET (Fig. 8). These figures are calculated by constant current method (Ids ¼ 107 A=mmÞ) [22]. 3.2. Analog/radio frequency (RF) analysis The study of high frequency responses are essential while dealing with charge plasma TFET. The analysis of the same are shown in terms of the gate to drain capacitance (Cgd ), transconductance (gm ), cut-off frequency (fT ) and gain bandwidth product (GBP). Parasitic capacitances are responsible for the degradation in RF performance of the device.
Fig. 2. Energy band diagram in OFF-state condition for different configuration of charge plasma TFETs.
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Fig. 3. Energy band diagram in ON-state condition for different configuration of charge plasma TFETs.
Total gate capacitance (Cgg ) is majorly contributed by Cgd due to the lower potential drop between channel and drain in TFETs as compared to large negative bias between channel and drain in the case of MOSFETs [23]. Higher Cgd and lower Cgs in the case of TFETs can be also realized by the lower channel to drain barrier resistance and larger source to channel barrier resistance respectively which makes Cgd more dominating [23]. Therefore, Cgd need to be reduced to achieve higher RF performance. The variation in Cgd is shown in Fig. 9 where Cgd increases with gate bias due to the presence of larger barrier at the drain/channel interface. Cgd is lower for the structures comprising of drain engineering whereas for the proposed device HGD DE DMG DL TEFT it increases to a little extent due to the effect of hetero gate dielectric, but it remains much lower than that of DL TFET and DMG DL TFET. Transconductance (gm ) is another important parameter to analyze the RF performance, which shows the rate of change of drain current with respect to the gate voltage. Fig. 10 shows the gm of all the devices where it is observed that HGD DE DMG DL TFET device has attained highest peak at the lower voltage (Vgs ) and drops at higher voltages due to mobility degradation. Here, the presence of HfO2 as a gate dielectric material near the source side with low gate work function (fR5 ) of 4.0 eV is used towards source end which provides better coupling of gate at source/channel interface, it also reduces the barrier at source/ channel interface which is responsible for enhancement of electric field and tunneling of carriers at source/channel interface. It results in better performance in terms of ON state current and gm with respect to other device. Apart from theses it is also responsible to achieve maximum electric field at lower gate to source voltage which results into degradation of mobility at low gate to source voltage in comparison to other devices. Other crucial parameters for RF analysis are fT and GBP, here fT is the transient frequency where the current gain of the device become unity and GBP is the measure of the device performance in high frequency ranges calculated at DC gain of 10. Both the parameters fT and GBP are calculated by using equations (6) and (7).
fT ¼
g m 2p Cgd þ Cgs
(6)
g m 2p Cgd
(7)
GBP ¼
Fig. 11 and Fig. 12 shows fT and GBP responses, where it is noticed that fT for HGD DE DMG DL TFET is significantly improved as compared to other devices (Fig. 11) at the lower voltage because of the combined effect of higher gm and lower Cgd . Now, looking at Fig. 12, it can be inferred that GBP for the proposed device is higher among all other devices. Thus, it is ensured that proposed modification done in DL TFET is beneficial for ultra low power and high frequency circuit applications. 4. Effect of gate and drain electrode length variation for HGD DE DMG DL TFET Selecting the optimized lengths (LB and LC ) and proper work function (fR4 and fR5 ) plays a very crucial role which is observed in the case of ON-state current, OFF-state current and threshold voltage/subthreshold swing. Therefore, the effect of length variation of electrodes with different values of work function (fR4 and fR5 ) is shown as follows: 4.1. Length (LC ) variation of gate metal electrode with variation in work function (fR5 ) values.
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Fig. 4. Energy band diagram in ambipolar condition for different configuration of charge plasma TFETs.
Fig. 5. Carrier concentration in Thermal equilibrium state for different configuration of charge plasma TFETs.
Fig. 6. Electric field in thermal equilibrium condition for different configuration of charge plasma TFETs.
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Fig. 7. Ids -Vgs characteristic of charge plasma TFETs.
Fig. 8. Threshold Voltage for different configuration of charge plasma TFETs.
Fig. 9. Gate to drain capacitance of charge plasma TFET's.
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Fig. 10. Transconductance for different configuration of charge plasma TFETs.
Fig. 11. ft vs Vgs curve for different configuration of charge plasma TFETs.
Fig. 12. Gain bandwidth product for different configuration of charge plasma TFETs.
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Fig. 13. Variation of device parameter with the fR5 for proposed device (HGD DE DMG DL TFET) (a) ON-state current, (b) OFF-state current and (c) Sub threshold swing.
4.2. Length (LB ) variation of drain metal electrode with variation in work function (fR4 ) values. In both the subsections, LB and LC are varied from 5 to 15 nm at a step size of 5 nm. 4.1. Length (LC ) variation of gate metal electrode with variation in work function (fR5 ) values Gate metal electrode length and work function engineering mostly effects the ON-state current, OFF-state current and SS, which is shown in Fig. 13(a), (b) and(c) respectively. The increment in length (LC ) of gate electrode significantly increases the ON-state current in the proposed device. Fig. 13(a) shows, ON-state current with respect to the work function (fR5 ) at distinct LC where it is notified that LC ¼ 15 nm provides better ON-state current. OFF-state current against (fR5 ) at different (LC ) is shown in Fig. 13(b) where it can be seen that (IOFF ) for (LC ) ¼ 5 and 10 nm is almost same and (LC ) increases beyond 10 nm it shows increment in (IOFF ). Thus, from Fig. 13(a) and (b) it is inferred that (LC ) ¼ 10 nm is optimized for maintaining trade off between (ION ) and (IOFF ). Effect of length (LC ) and work function (fR5 ) variation on the SS is shown in Fig. 13(c), which illustrates that lower value of SS i.e. 7.5 mV is achieved for LC 10 nm at fR5 ¼ 4.1 eV. 4.2. Length (LB ) variation of drain metal electrode with variation in work function (fR4 ) values The response in ON-state current ambipolar conduction and SS with variation in drain metal electrode length (LB ) and work function (fR4 ) over drain metal electrode is shown in Fig. 14(a), (b) and (c) respectively. Variation in ON-state current with respect to fR4 at different LB (Fig. 14(a)) depicts that ION increases with a decrease in length LB . Now from Fig. 14(b) it is observed that the ambipolar current increases with the decrease in drain metal electrode length (LB ) and for LB ¼ 5 nm, ambipolar current is obtained in order of 1013 A=mm. LB ¼ 15 nm is most appropriate drain electrode length for obtaining the reduced ambipolar current, but LB ¼ 15 nm is not chosen because of its limitation in obtaining a good response in ON-state
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Fig. 14. Variation of device parameter with the fR4 for proposed device (HGD DE DMG DL TFET) (a) ON-state current, (b) Ambipolar current and (c) Sub threshold swing.
current. SS decreases with a decrease in LB and the lowest value of SS is achieved at fR4 ¼ 4.0 eV as illustrated in Fig. 14(c). Hence, by analyzing Fig. 14(a), (b) and (c) it is found that LB ¼ 10 nm is the optimized value for achieving the better response in ON-state current and OFF-state current and steep sub-threshold swing. 5. Conclusion In this paper, the improvement in terms of ON/OFF-state current, ambipolar behavior and RF performance have been shown by the use of dual work functionality at drain and gate electrode with hetero gate dielectric for the proposed device (HGD DE DMG DL TFET). For this, extensive analysis of various charge plasma TFETs are performed with the help of 2D ATLAS simulation. HGD DE DMG DL TFET shows better performance with respect to other charge plasma TFETs. The cutoff frequency of proposed device is 1.65 times larger than the DE DMG DL TFET. The hetero gate dielectric and drain metal engineering plays a significant role in the improvement of ION =IOFF ratio (1011 ) and threshold voltage (1.7 times lesser than the DL TFET and 1.22 times less than DE DMG DL TFET in the case of proposed device). The parameters fT and GBP have attained its peak at low Vgs. Thus, the proposed device provides high operational speed and can be efficiently used for ultra low power applications. References [1] International Technology Roadmaps for Semiconductor, 2012 [Online]. Available: http://itrs.net. [2] J.P. Colinge, FinFETs and Other Multi-gate Transistors, Springer, New York, NY, USA, 2008. [3] H.J.M. Veendrick, Short-Circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE J. Solid-State Circuits, sc 17 (4) (Aug. 1984) 468e473. [4] R. Asra, M. Shrivastava, K.V.R.M. Murali, R.K. Pandey, H. Gossner, V.R. Rao, A tunnel FET for VDD scaling below 0.6 V with a CMOS-Comparable performance, IEEE Trans. Electron Devices 58 (7) (Jul. 2011) 1855e1863.
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