RF and ambipolar behaviour

Accepted Manuscript A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour Shivendra Yadav, Dheeraj Sharma, Bandi Venkata Chandan, Mohd Aslam, Deepak Soni, Neeraj Sharma PII:

S0749-6036(17)33027-6

DOI:

10.1016/j.spmi.2018.02.005

Reference:

YSPMI 5497

To appear in:

Superlattices and Microstructures

Received Date: 26 December 2017 Revised Date:

3 February 2018

Accepted Date: 4 February 2018

Please cite this article as: S. Yadav, D. Sharma, B.V. Chandan, M. Aslam, D. Soni, N. Sharma, A novel hetero-material gate-underlap electrically doped TFET for improving DC/RF and ambipolar behaviour, Superlattices and Microstructures (2018), doi: 10.1016/j.spmi.2018.02.005. This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to our customers we are providing this early version of the manuscript. The manuscript will undergo copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please note that during the production process errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain.

ACCEPTED MANUSCRIPT

RI PT

A Novel Hetero-material Gate-Underlap Electrically Doped TFET for Improving DC/RF and Ambipolar Behaviour Shivendra Yadav, Dheeraj Sharma, Bandi Venkata Chandan, Mohd. Aslam, Deepak Soni

M AN U

Neeraj Sharma

SC

Nanoelectronics and VLSI Lab. Electronics and Communication Engineering Discipline Indian Institute of Information Technology, Jabalpur, 482005, India.

Department of Computer Science Engineering, Ramrao Adik Institute of Technology Nerul, Navi Mumbai India.

Abstract

AC C

EP

TE D

In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET). Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig ) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected. Further, the use of low band gap material (Si0.5 Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5 Ge as a suitable candidate among different low band gap materials. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve Analog/RF performances without degrading the DC parameters of device. Additionally, hetero-junction alignment analysis Email addresses: [email protected] (Shivendra Yadav), [email protected] (Dheeraj Sharma), [email protected] (Bandi Venkata Chandan), [email protected] (Mohd. Aslam), [email protected] (Deepak Soni), [email protected] (Neeraj Sharma) Preprint submitted to Elsevier

February 7, 2018

ACCEPTED MANUSCRIPT

has been done for fabrication feasibility.

RI PT

Keywords: Ambipolarity, gate-underlap, drain-underlap, hetero material, gate leakage, inversion capacitance 1. Introduction

AC C

EP

TE D

M AN U

SC

Dimensions of metal oxide field effect transistors (MOSFETs) have been scaled down by three orders of magnitude in the last few decades. Miniaturization in feature size provides good scope for high density integrated circuits (ICs) as well as low-power and radio frequency (RF) devices. But, further down scaling in the dimensions of MOSFET to nano regime results short channel effects (SCEs), high leakage (OFF-state current), high static power dissipation and threshold roll-off [1-2]. MOSFET suffers low transition from OFF-state to ON-state which defines SS>60 mV/decade due to thermionic emission. Recently, tunnel field effect transistor (TFET) working mechanism of band to band tunnelling (BTBT) is reported as a potential replacement of MOSFET [3]. In conventional doped TFETs, it ’s hard to maintain abrupt junction at source/channel junctions due to diffusion of dopant atoms, which causes an adverse effect of random-dopant-fluctuations (RDFs) on the performance of TFET [4]. To resolve these issues, junctionless TFET (JL-TFET) is reported in [5]. Where by deciding the type (n-type or p-type) of TFET the substrate is doped either n+ or p+ and then p-i-n type structure is formed by work-function engineering. JL-TFET has improved ON-current, subthreshold swing (SS) and threshold voltage (Vth ) due to the presence of n+ layer at source/channel junction [5]. But JL-TFET suffers from the issues of physical doping like costly thermal annealing techniques and fabrication complexity. That’s why doping less TFETs based on charge plasma [6] and electrically doped [7-8] concepts have been introduced. Both the ideas wear the advantages of low fabrication complexity and cheap thermal annealing budget. But doping less TFET suffers from poor DC [6-8], RF performances and ambipolarity ( the inherent problem of all TFETs). To resolve these issues several ideas have been investigated i.e. work-function engineering at drain and gate electrodes [9-10], placement of metal strip at source/channel junction within dielectric [11], use of high κ-dielectric [12] and gate overlapping over the drain region [13]. Fabrication complexity of dual metal drain/gate and metal strip at nano scale is complicated. Dual work functionality at gate electrode resolve the problem of ambipolarity up to a limited extends at 2

RI PT

ACCEPTED MANUSCRIPT

SC

Figure 1: Cross-sectional view of (a) electrically doped TFET (ED-TFET), (b) gateunderlap electrically doped TFET (GUL-ED-TFET) and (c) hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET)

AC C

EP

TE D

M AN U

the cost of device reliability (hot carrier effect) and limited RF performance [10]. Dual metal drain degrades the DC performance of device [9] on the Other hand high-κ materials and gate drain overlapping slightly increase the parasitic capacitance in comparison to the conventional device [13]. In this paper, to suppress the negative conduction (ambipolarity) and improve the DC/RF performance, the concept of gate-underlap [14]-[15] with hetero material [16] in electrically doped TFET (ED-TFET) have been analysed. The gate electrode is under lapped from electrical drain (ED) side, which is named as (GUL-ED-TFET) shown in Fig. 1(b). Further, the concept of gate-underlap combined with band gap engineering (Si0.5 Ge) at source region in the proposed device (HM-GUL-ED-TFET) given by the Fig.1(c). The CG and other two electrodes (ED and ES) can be grown by polysilicon. From fabrication point of view gate-underlap is similar to short gate deposition, which can be deposited by chemical vapor deposition (CVD) of silane (SiH4 ) at higher temperature as reported in [17]. Rest of the paper is arranged as follows: Section II describes device geometry, dimensions used for simulations and technology aided computer design (TCAD) models. Section III presents results and discussion which deals with the device characteristics and material optimization. The effect of gateunderlap on the Cgd of proposed device is discussed in section IV. Further, a comparison of gate-underlap and drain-underlap is given in the section V. Section VI tells about linearity analysis of all three structures comparatively. Finally, section VII and VIII is devoted to the discussion of junction misalignment and highlights of the paper as a conclusion respectively.

3

RI PT

ACCEPTED MANUSCRIPT

SC

Table 1: Device dimensions and structural parameters for TFETs Symbol

EDTFET

GULEDTFET

Substrate doping (cm−3 ) Length of electrical drain (nm ) Length of electrical source (nm) Workfunction of electrical drain (ED) (eV) Workfunction of electrical source (ES) (eV) Silicon body thickness (nm) Oxide thickness (nm) Control gate length (nm) Workfunction of control gate (eV) Gate to electrical source spacer length (nm) Gate to electrical drain spacer length (nm) Length of gateunderlap (nm) Drain source contact

ni

1×1015

1×1015

HMGULEDTFET 1×1015

LED

50

50

50

LES

50

50

50

φED

4.5

4.5

4.5

φES

4.5

4.5

4.5

tsi

10

10

10

tox

1.5

1.5

1.5

LCG

50

30

30

φCG

4.5

4.5

4.5

LGS

4

4

4

LGD

5

-

-

LGU L

-

20

20

-

NiSi

NiSi

NiSi

AC C

EP

TE D

M AN U

Parameters name/Unit

4

ACCEPTED MANUSCRIPT

2. Device Structures and Simulation Parameters

TE D

M AN U

SC

RI PT

All the device dimensions have been figure out into table 1. Source and drain regions are formed by applying voltages -1.2 V and +1.2 V over the intrinsic substrate respectively, for creating P + -I-N + structure. Fig. 1(a-c) shows the cross-sectional view of ED-TFET, GUL-ED-TFET, HM-GUL-EDTFET respectively. High-κ dielectric (HfO2 ) is used for half length of the device at gate source end. The innovative technology computer-aided design (CAD) simulations are carried out by using 2D-ATLAS, Silvaco international [18]. Several in build models are used by simulator; BTBT model accounts generation rate throughout the meshing points of the device. The quantum tunnelling regions have to define to bring the BTBT into the effect. Further, quantum confinement model is included by Schrodinger Poisson’s model which gives the self-consistent solution of equations within the simulator. Fermi is considered as static carrier model, which elaborates electron and hole concentrations. It specifies lateral field mobility by standard concentration mobility. Shockley-Read-Hall recombination (SRH) and Auger recombination models are used to account the carrier exchange energy and their carrier life time. For drain and source contact NiSi a mid-band gap material is used. To define the contact between the intrinsic substrate and NiSi Schottky model is adopted in the model statement. 3. Results and discussion

AC C

EP

3.1. DC characteristics In this section, we have investigated the DC characteristics of proposed device (HM-GUL-ED-TFET) comparatively with conventional ED-TFET and GUL-ED-TFET. Gate-underlap attributes weak electric field under ambipolar state near drain/channel interface for GUL-ED-TFET and HM-GULED-TFET shown in the Fig. 2(a). Further, Fig. 2(b) gives energy band distribution over the device length in the ambipolar state; from the comparative analysis, large tunnelling width is found at drain/channel junction in case of HM-GUL-ED-TFET and GUL-ED-TFET. Both the above-mentioned facts make it clear that the concept of gate-underlap suppresses ambipolar current up to the level of OFF-state current as presented in the Fig. 2(e). Transfer characteristic (same figure) proves the suppression of negative conductance (ambipolar current) for GUL-ED-TFET and HM-GUL-ED-TFET in comparison to conventional ED-TFET. The concept of gate-underlap suppresses 5

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

Figure 2: (a) Electric field under ambipolar state, variation in energy bands along the lateral length (b) in ambipolar state, (c) in ON-state, (d) electric field under ON-state and (e) transfer characteristics.

AC C

EP

TE D

ambipolar current in case of GUL-ED-TFET, but it does not improve the ON-state current because the tunnelling resistance dominates over the series channel resistance. However, the conventional ED-TFET suffers from poor DC performance (low ON-state current). Consequently, to get better DC performance (suppressed ambipolar current and high ON-state current) low band gap material (Si0.5 Ge) with gate-underlap have been proposed in HMGUL-ED-TFET. The use of Si0.5 Ge at source side reduces the tunnelling barrier at source/channel interface consequently; tunneling probability becomes higher because of shorter tunnelling width as presented in the Fig. 2(c). The figure gives the energy band diagram along the lateral length of the device in a comparative sense. Higher tunnelling probability of HM-GULED-TFET is also supported by the Fig. 2(d), where a higher electric field is found for HM-GUL-ED-TFET in comparison to other two structures at source/channel interface. It results improved ON-state current for proposed device; such behaviour is expressed in Fig. 2(e). All the numerical values of DC parameters are summarised in Table II. Apart from these, we have first time shown the effect of gate-underlap over gate leakage. Gate leakage current is contributed by direct tunnelling of electrons through oxide from the gate metal into the drain region at lower Vgs . Further as the Vgs increases tunnelling starts from the source region into the gate electrode by reversing the gate current direction, which is also an integral part of gate leakage [19]. 6

SC

RI PT

ACCEPTED MANUSCRIPT

M AN U

Figure 3: Variation in gate leakage with Vgs of all three devices.

In both the tunnelling mechanisms, the gate to drain tunnelling has a major Table 2: DC Results of all three devices Symbol

EDTFET

ON-state current (A/µm) OFF-state current (A/µm) Subthreshold point slope (mv/decade) Threshold voltage (V)

ION

IOF F

9.88 9.88×10−7 ×10−7 5.88×10−18 4.4×10−18 3.07×10−17

SS

22.05

22.05

19.13

Vth

0.75

0.75

0.63

TE D

Parameters name/Unit

GULEDTFET

HMGULEDTFET 8.40×10−6

AC C

EP

roll in gate leakage. Since HM-GUL-ED-TFET and GUL-ED-TFET have gate-underlap at drain side; small length of gate electrode provides a tiny area which is subjected to gate (metal)-semiconductor (drain/source) tunnelling region, which is responsible for gate leakage. Besides, gate-underlap at drain side causes lower electron concentration at drain/channel interface which offers higher barrier for tunnelling of electrons from gate metal into drain region in case of HM-GUL-ED-TFET and GUL-ED-TFET as shown in the Fig. 3. The figure describes variation in gate leakage current (Ig ) with Vgs and indicates suppression in Ig for HM-GUL-ED-TFET and GUL-EDTFET.

7

ACCEPTED MANUSCRIPT

TE D

M AN U

SC

RI PT

3.2. Material analysis The section contains a detailed analysis of source material and discloses reason for selecting the Si0.5 Ge as a low band gap material among the other materials. For selecting an appropriate source material among germanium (Ge), indium arsenide (In0.5 As) and Si0.5 Ge a comparative analysis is done with the help of Fig. 4(a) and Fig. 4(b). Ge reflects better transfer characteristic in comparison to other materials shown in Fig. 4(a), but Fig. 4(b) says that Ge has higher Cgd , which is the poor indication for Analog/RF performance. Moreover, both the figures consequence In0.5 As and Si0.5 Ge have almost same Cgd but In0.5 As has higher OFF-state current, which would increase the static power dissipation in the device. In addition the lattice constant of different materials are Si = 5.43 A, Ge = 5.66 A, Si0.5 Ge = 5.44 A and In0.5 As = 5.65 A; so from the literature we can see that lattice mismatch for Si and Si0.5 Ge is lesser in comparison to other materials. So, after comparing different perspectives (DC as well as RF performance) of Si0.5 Ge, it is preferred as a source material. In the course of a simulation, it is easy to analyze the wide range of mole compositions for SiGe which is investigated through the Fig. 4(c-d). Fig. 4(c) tells that as the mole fraction of Ge increases in the SiGe composition the ON- and OFF-state current also increases. Similarly Fig. 4(d) also narrates increment in Cgd with increment of Ge fraction in SiGe. So, to achieve optimum performance regarding DC as well as Analog/RF an equal fraction of Si and Ge is preferred in this article.

AC C

EP

3.3. RF analysis This section describes the RF figures of merit (FOMs) of the devices, which include transconductance (gm ), gate to drain capacitance (Cgd ), cutoff frequency (ft ), gain bandwidth product (GBP) and maximum oscillating frequency (fmax ). All the Analog/RF FOMs are calculated at 1 MHz small signal input frequency. For high-speed applications device should have a low value of total capacitance; TFET has Miller capacitance, where Cgd behave as the parasitic capacitance at lower Vgs and at higher Vgs the inversion capacitance come into the picture. The Fig. 5(a) evidenced that Cgd has increasing trends with Vgs for all the three structures; GUL-ED-TFET has lower Cgd in comparison to ED-TFET due to gate-underlap. Gate-underlap causes less accumulation of charges in the channel region under short gate electrode which provide a reduction in both parasitic and inversion capacitances. However, the use of hetero material increases the Vgs about 0.5 fF 8

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

Figure 4: Variation in (a) drain current, (b) gate to drain capacitance for different materials, (c) drain current and (d) gate to drain capacitance for different mole fraction

AC C

EP

TE D

for HM-GUL-ED-TFET which is very incremental as can be seen from the same figure. Detail analysis of these capacitances is provided in the next section of the paper. Among all the RF FOMs; gm plays a significant role to improve RF performance of the device. It is defined as the ability of a device to reflect gate voltage (Vgs ) in to drain current (Ids ). Fig. 5(b) indicates that gm of ED-TFET and GUL-ED-TFET is almost same; it means gateunderlap does not affect the gm . However, band gap engineering produces drastic improvement in gm for HM-GUL-ED-TFET which can be seen from the same figure. Intense increment in gm dominates over Cgd and outcomes a drastic improvement in ft as depicted in the Fig. 5(c). The figure shows superior performance of HM-GUL-ED-TFET over the conventional ED-TFET and GUL-ED-TFET due to the combined effect of gate-underlap which restricts increment in Cgd and hetero material at source region. Further Fig. 5(d) clarifies the variation in GBP with Vgs , high GBP illustrates larger gain as well as bandwidth for the HM-GUL-ED-TFET as compared to other two structures. GBP is formulated as: gm /20π(Cgs + Cgd ; graph of GBP also follows the trend of ft and the reason is very obvious from the formula. Further, fmax is described as the maximum oscillating frequency at which power gain is unity. It is transit frequency corresponds to maximum available gain and, it is a functional parameter p for optimization of amplifiers. The fmax is given by the formula: fmax = ft /(8πCgd Rgd ), here the ft dominates over the Cgd 9

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

Figure 5: Variation in (a) gate to drain capacitance, (b) transconductance, (c) cut-off frequency, (d) gain bandwidth product and (e) maximum oscillating frequency with Vgs .

TE D

due to higher gm of HM-GUL-ED-TFET as compared to GUL-ED-TFET, which is indicated in terms of higher fmax in the Fig. 5(e). Here, the figure provides a comparative analysis for all three structures in terms of fmax with respect to Vgs . 4. Sensitivity of Cgd for gate-underlap in HM-GUL-ED-TFET:

AC C

EP

The total gate to drain capacitance (Cgd ) consist of parasitic capacitance (Cgdpar ) and inversion capacitance (Cgdinv ), Cgd = Cgdpar + Cgdinv . The parasitic component of Cgd is given by the equation: Cgdpar = Cofr + Cifr + Cdol , Cofr , Cifr and Cdol are the outer fringing, inner fringing and drain over lap capacitances respectively, which dominates in sub-threshold region only [20]. As the Vgs increases beyond Vth the formation of inversion layer has been initiated under gate region and Cgdinv start dominating over Cgdpar [16]. Along with the gate-underlap formation of the inversion layer is restricted due to less coupling of gate voltage with the substrate. Therefore, the length of the inversion layer is also get reduced as shown in the Fig. 6(a). Figure notifies the continuous reduction in the length of inversion layer by ±2 percent tolerance with gate-underlap in HM-GUL-ED-TFET. It out-turns reduction in the inversion capacitance as reported in Fig. 6(b). Figure depicts continuous decrement in Cgdinv with increment in gate-underlap. In opposite to this, 10

RI PT

ACCEPTED MANUSCRIPT

SC

Figure 6: Variation in (a) Linv , (b) Cgdinv and (c) Cgdpar with gate-underlap for HM-GULED-TFET

M AN U

the gate-underlap does not has a significant impact on parasitic capacitance (Cgdpar ). Because Cgdpar comes into picture under sub-threshold region and inversion layer does not form in sub-threshold condition. It is clarified in Fig. 6(c), which presents the variation in Cgdpar with gate-underlap. The figure shows only 0.0003 fF variation in Cgdpar for 30 nm gate-underlap.

TE D

5. Comparative analysis of drain-underlap and gate-underlap in proposed device:

Table 3: DC and RF Parameters for different values of gate-underlap in proposed device UL = 10

UL = 15

UL = 20

UL = 25

UL = 30

UL = 35

UL = 40

9.53

9.52

9.52

9.50

9.44

8.84

8.5

55.6

55.5

55.4

55.2

54.6

48.1

45.3

0.99

0.86

0.74

0.62

0.49

0.35

0.23

82.7

90.2

100.6

110.2

119.2

138.6

180.3

13.1

14.2

15.5

16.8

18.9

19.8

28.5

8.27

9.02

9.82

10.06

11.92

13.86

18.03

6.14× 10−17

8.93× 10−19

1.87× 10−18

1.61× 10−18

1.46× 10−18

1.35× 10−18

1.21× 10−18

AC C

EP

DC/RF UL = Pa5 rameters/Unit Ion 9.53 (A/µm) gm 55.6 (µS) cgd 1.12 (fF) ft 76.9 (GHz) fmax 12.2 (MHz) GBP 7.69 (GHz) Iamb 5.93× (A/µm) 10−13

This section provides first time a comparative analysis between gateunderlap and drain-underlap with a hetero material at source side for electrically doped TFET (HM-GUL-ED-TFET). Table III contains variation in 11

ACCEPTED MANUSCRIPT

Table 4: DC and RF Parameters for different values of drain-underlap in proposed device UL = 15

UL = 20

UL = 25

UL = 30

UL = 35

9.53

9.52

9.51

9.50

9.48

9.46

55.6

55.5

55.4

55.2

55.0

54.7

1.24

1.24

1.23

1.23

1.22

1.22

85.2

87.6

89.2

90.4

91.2

91.8

13.5

13.8

14.1

14.3

14.4

14.5

14.5

8.52

8.76

8.92

9.04

9.12

9.18

9.16

6.27× 10−17

8.93× 10−19

1.86× 10−18

1.66× 10−18

UL = 40

RI PT

UL = 10

9.43 54.3

1.22 91.6

SC

M AN U

DC/RF UL = Pa5 rameters/Unit Ion 9.53 (A/µm) gm 55.6 (µS) cgd 1.24 (fF) ft 81.4 (GHz) fmax 12.9 (MHz) GBP 8.14 (GHz) Iamb 5.92× (A/µm) 10−13

1.41× 10−18

1.33× 10−18

1.21× 10−18

AC C

EP

TE D

DC as well as RF parameters along with the variation of gate-underlap. Whereas in Table IV the gate length is kept constant and length of electrical drain (ED) of HM-GUL-ED-TFET has been varied from 45 to 10 nm. Table III and Table IV tell that gate-underlap beyond 25 nm causes variations in Ion as well as gm ; variation in gm is some more with gate-underlap as compared to drain-underlap for HM-GUL-ED-TFET. Whereas, the drain-underlap has almost no effect on Ion and gm . Moreover, the impact of gate-underlap over Cgd is higher (Table III) because of change in length of inversion layer as described in section III. But, the Cgd is almost unaffected from the drainunderlap (Table IV). Continuous increment in gm and decrement in Cgd with gate-underlap results drastic improvement in RF parameters like ft , fmax and GBP as compared to drain-underlap shown in Table III and IV. This comparison concludes that gate-underlap is more efficient than drain-underlap to improve RF performance. 6. Linearity analysis Fig. 7 presents the lowest peak in gm3 for HM-GUL-ED-TFET, it signifies linear behavior of a device. Further the zero- cross over point of gm3 assist in setting DC biasing point, a lower difference of zero-cross over and DC point is helpful to achieve lower distortion [21]. Modern communication systems, wireless equipments and radio frequency IC designing need devices with less inter-modulation distortion. Optimization of inter-modulation dis12

SC

RI PT

ACCEPTED MANUSCRIPT

TE D

M AN U

Figure 7: Variation in gm3 with Vgs

AC C

EP

Figure 8: Variation in (a) VIP2 and (b) VIP3 with Vgs

Figure 9: Variation in (a) IIP3 and (b) IMD3 with Vgs

13

ACCEPTED MANUSCRIPT

EP

TE D

M AN U

SC

RI PT

tortion is lengthy and complex processes. Saturation characteristic of drain current and subthreshold parameters are not enough FOMs to define the linearity of device. Therefore, linearity is analyzed through metrics of higher order derivatives of transconductance (gm3 ), second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third order intermodulation distortion (IMD3) and third-order intercept point (IIP3) [17]. The lower limit of total distortion is defined by third order harmonics which is given by third order derivative of drain current with Vgs . Lower zero-cross over point for HM-GUL-ED-TFET symbolize lower DC biasing and higher linearity in comparison to other two devices. VIP2 is extrapolated input voltage where first and second order harmonics are equal, and the HM-GUL-EDTFET has higher VIP2 which is required behaviour to maintain the linearity. The VIP2 is plotted with Vgs in a comparative sense as shown in the Fig. 8(a). In addition, the VIP3 is extrapolated input voltage at which first and third order harmonics are same. Higher VIP3 present significant inversion conditions through Fig. 8(b) for HM-GUL-ED-TFET at 0.88 V of Vgs . Cancelation of third order non-linearity by device feed back around second order nonlinearity is notified by a peak of VIP3. Fig. 9(a) shows higher IIP3 for all the range of Vgs in the case of proposed device. Band gap engineering at source side provides the higher electric field which results in improvement in carrier transport as well as channel controllability. IMD3 is originated from the transfer characteristic of a device which presents third order harmonic distortion at which first and third order harmonic currents are same [21]. It is responsible for the degeneracy of wireless communication system; Fig. 9(b) clarifies desired variation in IMD3 with Vgs for HM-GUL-ED-TFET. 7. Analysis of herero-junction misalignment

AC C

The section tells about the effects of misalignment of hetero-junction from ES at source/channel interface. Junction misalignment is not applicable at drain/channel interface because of the drain region will form only up to the length of ED as shown in the Fig. 1. In this concern, the heterojunction in the HM-GUL-ED-TFET is shifted towards gate electrode with 1 nm step size by covering the gate to source spacer length (LGS ). The Fig. 10(a) indicates almost negligible effect on DC performance of device when hetero- junction misaligned with ES from 1 to 5 nm range. But, Fig. 10(b), (c) and (d) clearly reflects significant increment in Cgd , gm and RF parameter (ft ) respectively due to misalignment of hetero-junction from ES as 14

EP

TE D

M AN U

SC

RI PT

ACCEPTED MANUSCRIPT

AC C

Figure 10: Variation in (a) IIP3 and (b) IMD3 with Vgs

15

ACCEPTED MANUSCRIPT

RI PT

compared to aligned hetero-junction as given in Fig. 5(a-c). RF parameters has been improved because of dominating behavior of gm in spite of increment in Cgd . Apart from these, misalignment of hetero-junction from 1 nm to 5 nm causes minute variation in Cgd , gm and (ft ) as illustrated in Fig. 10(b), (c) and (d) respectively. Here, Fig. 10 concludes that due to misalignment of hetero-junction (moving towards gate electrode) is not much effective for DC performance but, it is significant for RF one.

SC

8. Conclusion

TE D

M AN U

In this paper, we have presented gate-underlap at drain side and band gap engineering at source region in proposed device (HM-GUL-ED-TFET). Gateunderlap results in suppression of gate leakage and ambipolar current, but this technique is not much significant for advancing DC and RF performance. So to include all these attributes in a device both the concepts (gate-underlap and low band gap material at source side) have been combined in HM-GULED-TFET. In addition to these, different materials are analysed and then Si0.5 Ge is chosen as source material. Gate-underap significantly reduces inversion capacitance as compared to parasitic capacitance. Further, through comparative analysis, it is proved that gate-underlap is more effective than drain-underlap to improve Analog/RF performance of proposed device. The linearity test confirms the utility of device for higher frequency applications. At last, the alignment analysis of hetero-junction results in effective for RF performance in comparison to DC one in the proposed device.

AC C

EP

[1] S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight, “Universality of short-channel effects in undoped-body silicon nanowire MOSFETs,” IEEE Electron Devices lett., vol. 31, no. 9, pp. 903-905, Sep. 2010. [2] International Technology Roadmap for Semiconductors (ITRS). [Online]. Available: www.itrs2.net. [3] S. O. Koswatta, M. S. Lundstrom, and D. E. Nikonov, “Performance comparison between p-i-n tunneling transistors and conventional MOSFETs,” IEEE Trans. Electron Devices, vol. 56, no. 3, pp. 456-465, Mar. 2009.

16

ACCEPTED MANUSCRIPT

RI PT

[4] Nattapol damrongplasit, C. Shin, S. H. Kim, R. A. Vega, and T. J. K. Liu, “Study of random dopant fluctuation effects in germanium-source tunnel FETs,” IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 35413548, Oct. 2011.

[5] B. Ghosh and M. W. Akram, “Junctionless tunnel field effect transistor,”IEEE Electron Device Lett., vol. 34, no. 5, pp. 584-586, May 2013.

SC

[6] M. J. Kumar and S. Janardhanan, “Doping-less tunnel field effect transistor: Design and investigation ” IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3285-3290, Oct. 2013.

M AN U

[7] M. Kumar and S. Jit, “Effects of electrostatically doped source/drain and ferroelectric gate oxide on subthreshold swing and impact ionization rate of strained-Si-on-insulator tunnel field-effect transistors,” IEEE Trans. Nanotechnol., vol. 14, no. 4, pp. 597-599, Jul. 2015. [8] A. Lahgere, C. Sahu and J. Singh,“Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications,”Electronics Letters, vol. 51, no. 16, pp. 1284-1286, Aug. 2015.

TE D

[9] Shivendra Yadav, Dheeraj Sharma, Deepak Soni and Mohd. Aslam, “Controlling of ambipolarity with improved RF performance by drain/gate workfunction engineering and using high-k dielectric material in electrically doped TFET: Proposal and optimization,”Journal of Computational Electronics, pp. 1-11, Jun. 2017.

AC C

EP

[10] Bhagwan Ram Raad, Dheeraj Sharma, Pravin Kondekar, Kaushal Nigam, and Dharmendra Singh Yadav, “Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation IEEE Trans. Electron Devices, vol. 63, no. 10, pp. 3950-3957, Oct. 2016.

[11] Bhagwan Ram Raad, Sukeshni Tirkey, Dheeraj Sharma, and Pravin Kondekar, “A New Design Approach of Dopingless Tunnel FET for Enhancement of Device Characteristics IEEE Trans. Electron Devices, vol. 64, no. 4, pp. 1830-1836, Apr. 2017.

17

ACCEPTED MANUSCRIPT

RI PT

[12] K. Boucart and A. M. Ionescu, “Double-gate tunnel FET with high-k gate dielectric, ”IEEE Trans. Electron Devices, vol. 54, no. 7, pp. 17251733, Jul. 2007.

SC

[13] Jaya Madan and Rishu Chaujar,“Gate drain-overlapped-asymmetric gate dielectric-GAA-TFET: a solution for suppressed ambipolarity and enhanced ON state behavior, Applied Physics A, vol. 122, no. 11, pp. 973-981, Oct. 2016.

M AN U

[14] Uygar E. Avci, et.al,“Energy Efficiency Comparison of Nanowire Heterojunction TFET and Si MOSFET at Lg=13nm, Including P-TFET and Variation Considerations, IEEE International Electron Devices Meeting, pp. 883-887, Jan. 2014. [15] Dharmendra Singh Yadav, et.al,“Impactful study of dual work function, underlap and hetero gate dielectric on TFET with different drain doping profile for high frequency performance estimation and optimization, Superlattices and Microstructures, vol. 96, no. 9, pp. 36-46, Apr. 2016.

TE D

[16] Sylvan Brocard, et.al,“Large On-Current Enhancement in HeteroJunction Tunnel-FETs via Molar Fraction Grading, IEEE Electron Device Lett., vol. 35, no. 2, pp. 184-186, Feb. 2014.

EP

[17] M. Sekiya, et.al,“High Performance Poly-Crystalline Silicon Thin Film Transistors Fabricated Using Remote Plasma Chemical Vapor Deposition of SiO2 , IEEE Electron Device Lett., vol. 15, no. 2, pp. 69-71, Feb. 1994. [18] ATLAS Device Simulation Software, Silvaco Int., Santa Clara, CA, USA, 2014.

AC C

[19] Poornendu Chaturvedi and M. Jagadesh Kumar, “Impact of gate leakage considerations in tunnel field effect transistor Design,”Japanese Journal of Applied Physics, vol. 53, no. 7, pp. 1-21, Nov. 2014. [20] Yue Yang, Xin Tong, Li-Tao Yang, Peng-Fei Guo, Lu Fan and YeeChia Yeo, “Tunneling field-effect transistor: Capacitance components and modeling,”IEEE Electron Device Letter, vol. 31 no. 7 pp. 752-754 Jul. 2010.

18

ACCEPTED MANUSCRIPT

AC C

EP

TE D

M AN U

SC

RI PT

[21] Pujarini Ghosh et al, “An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design,”IEEE Trans. Electron Devices, vol. 59, no. 12, pp. 3263-3268, Dec. 2012

19

ACCEPTED MANUSCRIPT

AC C

EP

TE D

M AN U

SC

RI PT

The authors would like to thank the Science and Engineering Research Board, Department of Science and Technology, Government of India (established through an act of parliament) for providing the financial support to carry out this work. As this work has been implemented under the project “Implementation of Sigma Delta Modulator Using Nanowire Electrically Doped Hetero Material Tunnel Field Effect Transistor (TFET) for Ultra Low Power Applications” which is funded by this board.

ACCEPTED MANUSCRIPT

Highlights

RI PT

1. Electrically doped TFET provides much reduced complex fabrication process. 2. But, poor electrostatics characteristics are still a major issue with charge plasma TFET.

SC

3. In this article, the impact of gate-underlap with hetero material (low band gap) has been investigated in terms of DC and Analog/RF parameters by proposed device named as hetero material gate-underlap electrically doped TFET (HM-GUL-ED-TFET)

M AN U

4. Gate-underlap resolves the problem of ambipolarity, gate leakage current (Ig) and slightly improves the gate to drain capacitance, but DC performance is almost unaffected.

5. Further, the use of low band gap material (Si0.5Ge) in proposed device causes a drastic improvement in the DC as well as RF figures of merit. We have investigated the Si0.5Ge as a suitable candidate among different low band gap materials.

AC C

EP

TE D

6. In addition, the sensitivity of gate-underlap in terms of gate to drain inversion and parasitic capacitances has been studied for HM-GUL-ED-TFET. Further, relatively it is observed that gate-underlap is a better way than drain-underlap in the proposed structure to improve DC as well Analog/RF performances.