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Ambipolar microcrystalline silicon transistors and inverters
Solid-State Electronics 53 (2009) 635–639
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Ambipolar microcrystalline silicon transistors and inverters Kah-Yoong Chan a,b,1, Dietmar Knipp b,*, Joachim Kirchhoff a, Aad Gordijn a, Helmut Stiebig a,2 a b
Research Center Jülich, IEF5-Photovoltaics, 52425 Jülich, Germany Jacobs University Bremen, School of Engineering and Science, 28759 Bremen, Germany
a r t i c l e
i n f o
Article history: Received 22 October 2008 Received in revised form 15 March 2009 Accepted 2 April 2009 Available online 5 May 2009 The review of this paper was arranged by Dr. Y. Kuk Keywords: TFTs Microcrystalline silicon Ambipolar transistor Ambipolar inverter
a b s t r a c t Hydrogenated microcrystalline silicon (lc-Si:H) has lately attracted considerable attention as a promising candidate for thin-film transistors (TFTs) in large area electronic applications due to its superior charge carrier mobility. Here, we present ambipolar TFTs and inverters based on microcrystalline silicon prepared by plasma-enhanced chemical vapor deposition at low deposition temperature of 160 °C. The electrical parameters of the ambipolar microcrystalline silicon TFTs and inverters will be described. The influence of contact effects on the operation of ambipolar microcrystalline silicon TFTs was investigated. Furthermore, the influence of the ambipolar transistor characteristics on the performance of the ambipolar inverter will be discussed. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction Thin-film transistors (TFTs) are key element for large area electronic applications. To date, TFTs based on amorphous silicon (aSi:H) are commonly used as pixel switches for display backplanes [1]. However, the realization of more complicated driver circuitry is not possible due to low charge carrier mobility and device instability of a-Si:H [1–3]. So far external drivers are needed or the circuitry has to be realized by polycrystalline silicon (poly-Si) TFTs with high charge carrier mobilities and stable threshold voltages [4]. However, the manufacturing cost of poly-Si TFTs is higher due to high processing temperatures or additional crystallization steps [4,5]. Hydrogenated nano or microcrystalline silicon (nc-Si:H or lcSi:H) is a promising alternative to existing technologies due to its high electron and hole charge carrier mobilities [6–8]. Microcrystalline silicon consists of amorphous phases, silicon crystallites and voids, and is usually deposited at low temperature by plasma-enhanced chemical vapor deposition (PECVD) using a high hydrogen dilution [9]. The high electron and hole charge carrier mobilities in microcrystalline silicon facilitate the realization of integrated thin-film circuits such as shift register or line and row
* Corresponding author. Tel.: +49 421 200 3570; fax: +49 421 200 3103. E-mail address: [email protected] (D. Knipp). 1 Now with Multimedia University, Faculty of Engineering, 63100 Cyberjaya, Selangor, Malaysia. 2 Now with Malibu GmbH & Co. KG, 33609 Bielefeld, Germany. 0038-1101/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.04.002
multiplexers. However, the realization of complementary metal– oxide-semiconductor (CMOS) based integrated circuits requires complex processing of the thin-film devices. Alternatively, ambipolar circuits have been proposed, which simplify the device fabrication [10]. The realization and characterization of top-gate staggered ambipolar TFTs based on microcrystalline silicon will be described in Section 2. The devices were prepared by PECVD at maximum temperatures of 160 °C. Electrons and holes are directly injected into the intrinsic (i) microcrystalline silicon channel of the ambipolar TFTs via chromium (Cr) drain and source contacts. Doped n- or p-layers were not inserted between the metal contacts and the microcrystalline silicon channel layer. The electrical characteristics and contact effects of the realized ambipolar microcrystalline silicon TFTs will be discussed in Section 3.1. The first results on ambipolar inverters realized at low temperatures will be presented in Section 3.2. The influence of the ambipolar transistor characteristics on the performance of the inverter will be also discussed. The results will be summarized in Section 4. 2. Experimental The schematic cross-section of an ambipolar microcrystalline silicon TFTs is depicted in Fig. 1. The drain and source metal contacts of the transistors were realized by electron-beam evaporated chromium (Cr) with a thickness of 30 nm on glass substrates. The channel material was formed by an intrinsic microcrystalline silicon (i-lc-Si:H) film with a thickness of 100 nm. The thickness of
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Fig. 2. The n-channel transfer characteristics are plotted for positive gate voltages, whereas the p-channel transfer characteristics are shown for negative gate voltages. The n-channel transfer characteristics were measured for drain voltages, VD, of 0.1 V and 1 V. An electron charge carrier mobility of 37 cm2/Vs and a threshold voltage of 2.7 V were extracted from the n-channel transfer characteristics of the ambipolar TFT in the linear region of operation using equation [17]: Fig. 1. Schematic cross-section of a top-gate staggered ambipolar microcrystalline silicon thin-film transistor.
the channel layer was chosen to be 100 nm to attain a compromise between a high quality microcrystalline silicon due to the presence of a nucleation layer [9,11] and a low series resistance between the drain/source contacts and the charge carrier accumulation region [12]. The intrinsic microcrystalline silicon channel layer was deposited by PECVD at a deposition temperature of 160 °C and plasma excitation frequency of 13.56 MHz, in the high pressure (1330 Pa) and high power (0.3 W/cm2) regime, which facilitates the deposition of material at high deposition rates of up to 25 nm/min [13,14]. The microcrystalline silicon channel layer was prepared in the transition to amorphous growth regime to ensure high device performance [15,16]. Following the deposition of the intrinsic microcrystalline channel layer, a gate dielectric (silicon oxide, SiO2) of 300 nm was prepared by PECVD at 150 °C. Finally, the gate metal electrode was formed by an electron-beam evaporated aluminum (Al) film with a thickness of 100 nm. To allow for the fast evaluation of the device properties, a simple two-mask photolithography process was used. In order to improve the device behavior all transistors were annealed at an elevated temperature of 150 °C for 30 min under ambient conditions. The characterizations of the realized ambipolar TFTs and the inverters were performed at room temperature under dark conditions. The sweep rate for the transistor and inverter measurements was 0.2 V/s. 3. Results and discussion 3.1. Ambipolar thin-film transistors The n-channel and p-channel transfer characteristics of an ambipolar microcrystalline silicon TFT with a channel length, L, of 20 lm and a channel width, W, of 1000 lm are shown in
ID ¼ l C G
ð1Þ
Here ID, l and CG are the drain current, the charge carrier mobility and the gate capacitance per unit area, respectively. VG and VT are the gate voltage and the threshold voltage, respectively. The transistor exhibits a subthreshold slope of 0.5 V/decade, which is extracted from the below-threshold regime of the measured transfer characteristics using the equation S = @VG/@(log(IDsub)) [18], where IDsub is the subthreshold current. The on/off ratio of the ambipolar TFT for the n-channel operation for low drain voltages (at low reverse gate voltage) is larger than 105. The p-channel transfer characteristics of the ambipolar microcrystalline silicon TFT with a channel length of 20 lm and a channel width of 1000 lm were measured for drain voltages, VD, of 1 V and 3 V. For p-channel operation, the ambipolar microcrystalline transistor exhibits a hole charge carrier mobility of 10 cm2/Vs. Therefore, the achieved electron charge carrier mobility for the ambipolar microcrystalline TFTs is about three to four times higher than the hole charge carrier mobility. The ratio of the electron to hole charge carrier mobility seems comparable to the electronic properties of crystalline silicon and to the ratio successfully applied for the modeling of microcrystalline silicon diodes [15]. The threshold voltage of the ambipolar microcrystalline silicon transistor in the p-channel operation mode is increased to 6 V in comparison to 2.7 V extracted for the ambipolar TFT in the n-channel operation mode. The TFT in the p-channel mode exhibits a subthreshold slope of 0.7 V/decade, and the on/off ratio for low drain voltages at low reverse gate voltage is larger than 104. Thin-film transistors with high electron and hole charge carrier mobilities can only be realized if electrons and holes are effectively injected in the microcrystalline silicon channel material. The formation of a distinct Schottky barrier in the drain and source contact region would hinder the effective injection of charges resulting in a high contact resistance. In order to qualitatively determine the contact properties of the ambipolar microcrystalline silicon TFTs, contact effects of the transistors in the n- and p-channel operation modes were investigated in the following. Fig. 3 shows the extracted linear electron and hole charge carrier mobility as a function of the channel length for the ambipolar TFTs in the n- and p-channel operation mode, respectively. For long channel TFTs (L = 200 lm), the electron and hole charge carrier mobilities reach 60 cm2/Vs and 18 cm2/Vs, respectively. Both the electron and hole charge carrier mobilities of the ambipolar TFTs, which were extracted using the Eq. (1), decrease with decreasing channel length due to the influence of the drain and source contact effects [8]. The experimental data in Fig. 3 were fitted according to the following modified transistor model, which takes the influence of the contact resistance on the extracted electron and hole charge charier mobilities into account [8]:
l ¼ l0
Fig. 2. n-Channel and p-channel transfer characteristics of the ambipolar microcrystalline silicon thin-film transistor with a channel width, W, of 1000 lm and a channel length, L, of 20 lm.
W VD VG VT V D: L 2
L : L þ l0 C G rC V G V T V2D
ð2Þ
Here l is the extracted charge carrier mobility for the TFTs using the standard transistor equation (Eq. (1)) which is influenced by the contact effects, l0 is the intrinsic charge carrier mobility for the microcrystalline silicon channel material which is free of
K.-Y. Chan et al. / Solid-State Electronics 53 (2009) 635–639
Fig. 3. Extracted electron and hole charge carrier mobilities as a function of the channel length for the ambipolar microcrystalline silicon thin-film transistors.
contact effects, and rC is the normalized drain and source contact resistance. The modified transistor model (Eq. (2)) was developed by taking the voltage drop across the drain and source contacts into account of Eq. (1). By fitting the charge carrier mobilities in Fig. 3 we extracted a normalized drain and source contact resistance, rC, in the range of 1 kX cm and 4 kX cm for the ambipolar microcrystalline silicon TFTs in the n- and p-channel operation mode, respectively. The intrinsic electron and hole charge carrier mobilities, l0, extracted from the fits are 64 cm2/Vs and 20 cm2/Vs, respectively. The higher normalized contact resistance for the ambipolar TFTs in the p-channel operation mode in comparison to the n-channel operation mode can be understood as the charge carrier mobilities of the ambipolar transistors have an influence on the contact resistance. The same behavior was observed for microcrystalline silicon thin-film transistors prepared at different deposition conditions. Transistors with high intrinsic charge carrier mobilities exhibit low contact resistances, whereas transistors with low intrinsic charge carrier mobilities show high contact resistances [16]. In general, the extracted contact resistances are fairly low given the fact that the highly doped n- or p-layers were not inserted between the drain and source metal contacts and the microcrystalline silicon channel layer. It has been proposed that the low contact resistances are caused by the formation of a highly conductive chromium silicide layer. Such layers are already formed at temperatures below 200 °C [19,20]. Further investigations of the formation process of such silicide layers and the injection of charges in the channel of the transistor have to be carried out in order to gain a better understanding of the charge transport in such devices. However, the high drain current observed in the nominal off-state of the transistors is a result of an effective injection of holes (electrons) in the channel of the n-type (p-type) transistor. The threshold voltage as a function of the channel length for the ambipolar microcrystalline silicon TFTs in the n- and p-channel operation mode are shown in Fig. 4. The threshold voltages were extracted from the measured transfer characteristics in the linear operational regime using Eq. (1). For the ambipolar TFTs in the nchannel operation mode, the extracted threshold voltages vary from 2 V to 4 V, while in the p-channel operation mode the threshold voltages are increased to approximately 6 V. It is known that TFTs fabricated at low temperatures are susceptible to bias stress effects. The effects are mainly caused by charge trapping in the silicon oxide and its interface with the lc-Si:H channel material [21]. The low temperature deposited silicon oxide is not as stable and compact as silicon oxide grown at higher temperature [21]. The charge trapping causes a shift in the device
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Fig. 4. Extracted threshold voltages as a function of the channel length for the ambipolar microcrystalline silicon thin-film transistors in n-channel and p-channel operation modes.
threshold voltage. For the ambipolar TFTs reported in this paper, we have not performed a systematic study of the transistors behavior under bias stress. However, subsequent measurements of the transistors lead to a shift of the device threshold voltage by 50–150 mV. 3.2. Ambipolar inverters Ambipolar transistors provide a simple route in realizing integrated circuits like radio frequency identification tags (RFID tags) or line and row drivers for display applications since separate patterning steps for n- and p-type doped layers can be eliminated. In the following the ambipolar transistors were used to realize inverters, which are the basic building blocks for many other integrated circuits. The circuit implementation of an ambipolar inverter is shown in Fig. 5 [22]. The inverter is realized by integrating two ambipolar thin-film transistors, one of which is meant for p-channel operation while the other is for n-channel operation. The upper ambipolar TFT is meant for p-channel operation while the lower ambipolar TFT is for n-channel operation. The input signal of the inverter, VIN, is applied to the gate terminals of both ambipolar TFTs, while the
Fig. 5. Schematic circuit of an ambipolar inverter, which is realized by integrating two ambipolar thin-film transistors (TFTs), one of which operates as a ‘p-channel’ TFT while the other operates as an ‘n-channel’ TFT.
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is not the case for ambipolar inverters. The increase of the output voltage with increasing operating voltage leads to a drop of the noise margin for high operating voltages. The given ambipolar inverter curves in Fig. 6 exhibit the highest noise margin for an operation voltage of 4 V, while maintaining a high voltage gain of the inverter. The noise margin of the ambipolar inverter based on the low temperature fabricated microcrystalline silicon is sensitive to the variation of the threshold voltage of the constituent TFTs. Future studies are necessary to systematically investigate the influence of the variation of the threshold voltage on the electrical characteristics of the inverter. It can be concluded that ambipolar inverters are an interesting addition to existing CMOS inverter technology. However, the specific disadvantages of the technology have to be taken into account when designing ambipolar inverter based circuitry. 4. Conclusions Fig. 6. Voltage transfer characteristics of an ambipolar inverter measured at supply voltages, VDD, of 3 V, 4 V, 5 V and 6 V. The inverter consists of an ambipolar thin-film transistor (TFT) with a channel width, W, of 1000 lm and a channel length, L, of 20 lm for p-channel operation, and an ambipolar TFT with a channel width of 200 lm and a channel length of 20 lm for n-channel operation.
drain terminal of the lower ambipolar TFT serves as output voltage, VOUT, for the inverter. The source terminal of the upper ambipolar TFT is connected to the supply voltage of the inverter, VDD. If the input signal is equal to VDD, which is considered as logical high, the lower ambipolar TFT is conducting while the upper TFT (which has its gate-source voltage, VGS, equal to 0 V) is cut off. Hence the output voltage of the inverter, VOUT, is approximately equal to 0 V, representing a logical low. When the input signal is at ground or equal to 0 V which is considered as logical low, the lower TFT is cut off while the upper TFT is conducting, so that the VOUT is very close to VDD, representing a logical high. The experimental voltage transfer characteristics of an ambipolar inverter measured for positive supply voltages, VDD, of 3 V, 4 V, 5 V and 6 V are shown in Fig. 6. The voltage transfer curve was measured from low supply voltage (0 V) to high supply voltage (8 V). The ambipolar inverter was realized using an ‘n-channel’ ambipolar TFT with a channel length of 20 lm and a channel width of 200 lm, and a ‘p-channel’ ambipolar TFT with a channel length of 20 lm and a channel width of 1000 lm. The increased channel width of the transistor meant for p-channel operation compensates for the reduced hole charge charier mobility of the ambipolar transistor. The voltage transfer curve exhibits the typical features of ambipolar inverters. The ambipolar inverter exhibits a high voltage gain comparable to CMOS inverters. The experimentally extracted voltage gain, which is defined to be vGAIN = @VOUT/@VIN, where VOUT and VIN are the output and input voltage of the inverter, respectively, is equal to 5–10 and a clear and abrupt transition for the inverter output voltage from the logical high- to low-state was observed. The voltage gain of the realized ambipolar inverter is higher than the voltage gain of n-channel metal–oxide-semiconductor (NMOS) inverters based on microcrystalline silicon fabricated under comparable processing conditions [23]. On the other hand, the output voltage of the ambipolar microcrystalline inverter in the logical low-state increases with increasing input voltage, which can be explained by the high off-current of the constituent p-channel ambipolar microcrystalline silicon transistor at high drain voltages. As a consequence the noise margin of the ambipolar inverter is reduced and the power consumption is increased, which limit the realization of complex thin-film circuitry. The problem can only be reduced by selecting the right operating voltages of the inverter. Conventional CMOS inverters exhibit an increase of the noise margin with increasing operating voltages. However, this
In summary, ambipolar microcrystalline silicon TFTs were realized at low temperature of 160 °C with distinctively high electron and hole charge carrier mobilities of 60 cm2/Vs and 18 cm2/Vs, respectively. Based on the ambipolar microcrystalline silicon TFTs, ambipolar inverters were demonstrated which exhibit high voltage gains of 5–10. The contact effects of the ambipolar microcrystalline TFTs is more pronounced in the p-channel operation mode in comparison to the n-channel operation mode due to a lower hole charge carrier mobility compared to electron charge carrier mobility. The ambipolar transistors and inverters provide a simple route in realization of large area integrated circuits at low cost based on microcrystalline silicon. Acknowledgements The authors like to acknowledge S. Bunte and Y. Mohr (IBN-PT) for preparation of the PECVD SiO2, M. Hülsbeck, T. Melle, S. Michel, and R. Schmitz for technical assistances and E. Bunte, R. Carius, D. Hrunski, and V. Smirnov for helpful discussions. References [1] Tsukada T. Technology and applications of amorphous silicon. In: Street RA, editor. Springer series in material science, vol. 37. Berlin (Germany): SpringerVerlag; 2000. [2] Wong WS, Ready SE, Lu JP, Street RA. Hydrogenated amorphous silicon thinfilm transistor arrays fabricated by digital lithography. IEEE Electron Dev Lett 2003;24(9):577–9. [3] Kavak H, Shanks H. Stability of hydrogenated amorphous silicon thin-film transistors on polyimide substrates. Solid-State Electron 2005;49:578–84. [4] Brotherton SD. Polycrystalline silicon thin film transistors. Semicond Sci Technol 1995;10:721–38. [5] Tsai CC, Lee YJ, Wang JL, Wei KF, Lee IC, Chen CC, et al. High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization. Solid-State Electron 2008;52: 365–71. [6] Cheng IC, Wagner S. Hole and electron field-effect mobilities in nanocrystalline silicon deposited at 150 °C. Appl Phys Lett 2002;80(3):440–2. [7] Lee CH, Sazonov A, Nathan A. High-mobility nanocrystalline silicon thin-film transistors fabricated by plasma-enhanced chemical vapor deposition. Appl Phys Lett 2005;86:222106. [8] Chan KY, Bunte E, Stiebig H, Knipp D. Influence of contact effect on the performance of microcrystalline silicon thin-film transistors. Appl Phys Lett 2006;89:203509. [9] Vetterl O, Finger F, Carius R, Hapke P, Houben L, Kluth O, et al. Intrinsic microcrystalline silicon: a new material for photovoltaics. Sol Energy Mater Sol Cells 2000;62:97–108. [10] Lee CH, Sazonov A, Rad MRE, Chaji GR, Nathan A. Ambipolar thin-film transistors fabricated by PECVD nanocrystalline silicon. Mater Res Soc Symp Proc 2006;910. 0910-A22-05. [11] Shirai H, Arai T, Nakamura T. Control of the initial stage of nanocrystallite silicon growth monitored by in-situ spectroscopic ellipsometry. Appl Surf Sci 1997;113/114:111–5. [12] Cheng IC, Allen S, Wagner S. Evolution of nanocrystalline silicon thin-film transistor channel layers. J Non-Cryst Solids 2004;338–340:720–4.
K.-Y. Chan et al. / Solid-State Electronics 53 (2009) 635–639 [13] Guo L, Kondo M, Fukawa M, Saitoh K, Matsuda A. High rate deposition of microcrystalline silicon using conventional plasma-enhanced chemical vapor deposition. Jpn J Appl Phys 1998;37:L1116–8. [14] Rech B, Roschek T, Repmann T, Müller J, Schmitz R, Appenzeller W. Microcrystalline silicon for large area thin film solar cells. Thin Solid Films 2003;427:157–65. [15] Brammer T, Stiebig H. Defect density and recombination lifetime in microcrystalline silicon absorbers of highly efficient thin-film solar cells determined by numerical device simulations. J Appl Phys 2003;94: 1035–42. [16] Chan KY, Knipp D, Gordijn A, Stiebig H. High-mobility microcrystalline silicon thin-film transistors prepared near the transition to amorphous growth. J Appl Phys 2008;104:054506. [17] Sze SM. Physics of semiconductor devices. 2nd ed. New York: Wiley; 1981. p. 441.
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[18] Greve DW. Field effect devices and applications: devices for portable, lowpower, and imaging systems. 1st ed. Englewood Cliffs (NJ): Prentice-Hall; 1998. p. 287. [19] Schlesinger TE, Cammarata RC, Prokes SM. Kinetics of silicide formation in chromium–amorphous silicon multilayered films. Appl Phys Lett 1991;59(4):449–51. [20] Kovsarian A, Shannon JM. Amorphous chromium silicide formation in hydrogenated amorphous silicon. J Electron Mater 1998;27(11):1268–71. [21] Cheng IC, Wagner S. Nanocrystalline silicon thin film transistors. IEE Proc Circ Dev Syst 2003;150(4):339–44. [22] Hodges DA, Jackson HG. Analysis and design of digital integrated circuits. New York: McGraw-Hill Book Company; 1983. p. 98. [23] Chan KY, Bunte E, Knipp D, Stiebig H. Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors. Solid-State Electron 2008;52:914–8.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Ambipolar microcrystalline silicon transistors and inverters Kah-Yoong Chan a,b,1, Dietmar Knipp b,*, Joachim Kirchhoff a, Aad Gordijn a, Helmut Stiebig a,2 a b
Research Center Jülich, IEF5-Photovoltaics, 52425 Jülich, Germany Jacobs University Bremen, School of Engineering and Science, 28759 Bremen, Germany
a r t i c l e
i n f o
Article history: Received 22 October 2008 Received in revised form 15 March 2009 Accepted 2 April 2009 Available online 5 May 2009 The review of this paper was arranged by Dr. Y. Kuk Keywords: TFTs Microcrystalline silicon Ambipolar transistor Ambipolar inverter
a b s t r a c t Hydrogenated microcrystalline silicon (lc-Si:H) has lately attracted considerable attention as a promising candidate for thin-film transistors (TFTs) in large area electronic applications due to its superior charge carrier mobility. Here, we present ambipolar TFTs and inverters based on microcrystalline silicon prepared by plasma-enhanced chemical vapor deposition at low deposition temperature of 160 °C. The electrical parameters of the ambipolar microcrystalline silicon TFTs and inverters will be described. The influence of contact effects on the operation of ambipolar microcrystalline silicon TFTs was investigated. Furthermore, the influence of the ambipolar transistor characteristics on the performance of the ambipolar inverter will be discussed. Ó 2009 Elsevier Ltd. All rights reserved.
1. Introduction Thin-film transistors (TFTs) are key element for large area electronic applications. To date, TFTs based on amorphous silicon (aSi:H) are commonly used as pixel switches for display backplanes [1]. However, the realization of more complicated driver circuitry is not possible due to low charge carrier mobility and device instability of a-Si:H [1–3]. So far external drivers are needed or the circuitry has to be realized by polycrystalline silicon (poly-Si) TFTs with high charge carrier mobilities and stable threshold voltages [4]. However, the manufacturing cost of poly-Si TFTs is higher due to high processing temperatures or additional crystallization steps [4,5]. Hydrogenated nano or microcrystalline silicon (nc-Si:H or lcSi:H) is a promising alternative to existing technologies due to its high electron and hole charge carrier mobilities [6–8]. Microcrystalline silicon consists of amorphous phases, silicon crystallites and voids, and is usually deposited at low temperature by plasma-enhanced chemical vapor deposition (PECVD) using a high hydrogen dilution [9]. The high electron and hole charge carrier mobilities in microcrystalline silicon facilitate the realization of integrated thin-film circuits such as shift register or line and row
* Corresponding author. Tel.: +49 421 200 3570; fax: +49 421 200 3103. E-mail address: [email protected] (D. Knipp). 1 Now with Multimedia University, Faculty of Engineering, 63100 Cyberjaya, Selangor, Malaysia. 2 Now with Malibu GmbH & Co. KG, 33609 Bielefeld, Germany. 0038-1101/$ - see front matter Ó 2009 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2009.04.002
multiplexers. However, the realization of complementary metal– oxide-semiconductor (CMOS) based integrated circuits requires complex processing of the thin-film devices. Alternatively, ambipolar circuits have been proposed, which simplify the device fabrication [10]. The realization and characterization of top-gate staggered ambipolar TFTs based on microcrystalline silicon will be described in Section 2. The devices were prepared by PECVD at maximum temperatures of 160 °C. Electrons and holes are directly injected into the intrinsic (i) microcrystalline silicon channel of the ambipolar TFTs via chromium (Cr) drain and source contacts. Doped n- or p-layers were not inserted between the metal contacts and the microcrystalline silicon channel layer. The electrical characteristics and contact effects of the realized ambipolar microcrystalline silicon TFTs will be discussed in Section 3.1. The first results on ambipolar inverters realized at low temperatures will be presented in Section 3.2. The influence of the ambipolar transistor characteristics on the performance of the inverter will be also discussed. The results will be summarized in Section 4. 2. Experimental The schematic cross-section of an ambipolar microcrystalline silicon TFTs is depicted in Fig. 1. The drain and source metal contacts of the transistors were realized by electron-beam evaporated chromium (Cr) with a thickness of 30 nm on glass substrates. The channel material was formed by an intrinsic microcrystalline silicon (i-lc-Si:H) film with a thickness of 100 nm. The thickness of
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Fig. 2. The n-channel transfer characteristics are plotted for positive gate voltages, whereas the p-channel transfer characteristics are shown for negative gate voltages. The n-channel transfer characteristics were measured for drain voltages, VD, of 0.1 V and 1 V. An electron charge carrier mobility of 37 cm2/Vs and a threshold voltage of 2.7 V were extracted from the n-channel transfer characteristics of the ambipolar TFT in the linear region of operation using equation [17]: Fig. 1. Schematic cross-section of a top-gate staggered ambipolar microcrystalline silicon thin-film transistor.
the channel layer was chosen to be 100 nm to attain a compromise between a high quality microcrystalline silicon due to the presence of a nucleation layer [9,11] and a low series resistance between the drain/source contacts and the charge carrier accumulation region [12]. The intrinsic microcrystalline silicon channel layer was deposited by PECVD at a deposition temperature of 160 °C and plasma excitation frequency of 13.56 MHz, in the high pressure (1330 Pa) and high power (0.3 W/cm2) regime, which facilitates the deposition of material at high deposition rates of up to 25 nm/min [13,14]. The microcrystalline silicon channel layer was prepared in the transition to amorphous growth regime to ensure high device performance [15,16]. Following the deposition of the intrinsic microcrystalline channel layer, a gate dielectric (silicon oxide, SiO2) of 300 nm was prepared by PECVD at 150 °C. Finally, the gate metal electrode was formed by an electron-beam evaporated aluminum (Al) film with a thickness of 100 nm. To allow for the fast evaluation of the device properties, a simple two-mask photolithography process was used. In order to improve the device behavior all transistors were annealed at an elevated temperature of 150 °C for 30 min under ambient conditions. The characterizations of the realized ambipolar TFTs and the inverters were performed at room temperature under dark conditions. The sweep rate for the transistor and inverter measurements was 0.2 V/s. 3. Results and discussion 3.1. Ambipolar thin-film transistors The n-channel and p-channel transfer characteristics of an ambipolar microcrystalline silicon TFT with a channel length, L, of 20 lm and a channel width, W, of 1000 lm are shown in
ID ¼ l C G
ð1Þ
Here ID, l and CG are the drain current, the charge carrier mobility and the gate capacitance per unit area, respectively. VG and VT are the gate voltage and the threshold voltage, respectively. The transistor exhibits a subthreshold slope of 0.5 V/decade, which is extracted from the below-threshold regime of the measured transfer characteristics using the equation S = @VG/@(log(IDsub)) [18], where IDsub is the subthreshold current. The on/off ratio of the ambipolar TFT for the n-channel operation for low drain voltages (at low reverse gate voltage) is larger than 105. The p-channel transfer characteristics of the ambipolar microcrystalline silicon TFT with a channel length of 20 lm and a channel width of 1000 lm were measured for drain voltages, VD, of 1 V and 3 V. For p-channel operation, the ambipolar microcrystalline transistor exhibits a hole charge carrier mobility of 10 cm2/Vs. Therefore, the achieved electron charge carrier mobility for the ambipolar microcrystalline TFTs is about three to four times higher than the hole charge carrier mobility. The ratio of the electron to hole charge carrier mobility seems comparable to the electronic properties of crystalline silicon and to the ratio successfully applied for the modeling of microcrystalline silicon diodes [15]. The threshold voltage of the ambipolar microcrystalline silicon transistor in the p-channel operation mode is increased to 6 V in comparison to 2.7 V extracted for the ambipolar TFT in the n-channel operation mode. The TFT in the p-channel mode exhibits a subthreshold slope of 0.7 V/decade, and the on/off ratio for low drain voltages at low reverse gate voltage is larger than 104. Thin-film transistors with high electron and hole charge carrier mobilities can only be realized if electrons and holes are effectively injected in the microcrystalline silicon channel material. The formation of a distinct Schottky barrier in the drain and source contact region would hinder the effective injection of charges resulting in a high contact resistance. In order to qualitatively determine the contact properties of the ambipolar microcrystalline silicon TFTs, contact effects of the transistors in the n- and p-channel operation modes were investigated in the following. Fig. 3 shows the extracted linear electron and hole charge carrier mobility as a function of the channel length for the ambipolar TFTs in the n- and p-channel operation mode, respectively. For long channel TFTs (L = 200 lm), the electron and hole charge carrier mobilities reach 60 cm2/Vs and 18 cm2/Vs, respectively. Both the electron and hole charge carrier mobilities of the ambipolar TFTs, which were extracted using the Eq. (1), decrease with decreasing channel length due to the influence of the drain and source contact effects [8]. The experimental data in Fig. 3 were fitted according to the following modified transistor model, which takes the influence of the contact resistance on the extracted electron and hole charge charier mobilities into account [8]:
l ¼ l0
Fig. 2. n-Channel and p-channel transfer characteristics of the ambipolar microcrystalline silicon thin-film transistor with a channel width, W, of 1000 lm and a channel length, L, of 20 lm.
W VD VG VT V D: L 2
L : L þ l0 C G rC V G V T V2D
ð2Þ
Here l is the extracted charge carrier mobility for the TFTs using the standard transistor equation (Eq. (1)) which is influenced by the contact effects, l0 is the intrinsic charge carrier mobility for the microcrystalline silicon channel material which is free of
K.-Y. Chan et al. / Solid-State Electronics 53 (2009) 635–639
Fig. 3. Extracted electron and hole charge carrier mobilities as a function of the channel length for the ambipolar microcrystalline silicon thin-film transistors.
contact effects, and rC is the normalized drain and source contact resistance. The modified transistor model (Eq. (2)) was developed by taking the voltage drop across the drain and source contacts into account of Eq. (1). By fitting the charge carrier mobilities in Fig. 3 we extracted a normalized drain and source contact resistance, rC, in the range of 1 kX cm and 4 kX cm for the ambipolar microcrystalline silicon TFTs in the n- and p-channel operation mode, respectively. The intrinsic electron and hole charge carrier mobilities, l0, extracted from the fits are 64 cm2/Vs and 20 cm2/Vs, respectively. The higher normalized contact resistance for the ambipolar TFTs in the p-channel operation mode in comparison to the n-channel operation mode can be understood as the charge carrier mobilities of the ambipolar transistors have an influence on the contact resistance. The same behavior was observed for microcrystalline silicon thin-film transistors prepared at different deposition conditions. Transistors with high intrinsic charge carrier mobilities exhibit low contact resistances, whereas transistors with low intrinsic charge carrier mobilities show high contact resistances [16]. In general, the extracted contact resistances are fairly low given the fact that the highly doped n- or p-layers were not inserted between the drain and source metal contacts and the microcrystalline silicon channel layer. It has been proposed that the low contact resistances are caused by the formation of a highly conductive chromium silicide layer. Such layers are already formed at temperatures below 200 °C [19,20]. Further investigations of the formation process of such silicide layers and the injection of charges in the channel of the transistor have to be carried out in order to gain a better understanding of the charge transport in such devices. However, the high drain current observed in the nominal off-state of the transistors is a result of an effective injection of holes (electrons) in the channel of the n-type (p-type) transistor. The threshold voltage as a function of the channel length for the ambipolar microcrystalline silicon TFTs in the n- and p-channel operation mode are shown in Fig. 4. The threshold voltages were extracted from the measured transfer characteristics in the linear operational regime using Eq. (1). For the ambipolar TFTs in the nchannel operation mode, the extracted threshold voltages vary from 2 V to 4 V, while in the p-channel operation mode the threshold voltages are increased to approximately 6 V. It is known that TFTs fabricated at low temperatures are susceptible to bias stress effects. The effects are mainly caused by charge trapping in the silicon oxide and its interface with the lc-Si:H channel material [21]. The low temperature deposited silicon oxide is not as stable and compact as silicon oxide grown at higher temperature [21]. The charge trapping causes a shift in the device
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Fig. 4. Extracted threshold voltages as a function of the channel length for the ambipolar microcrystalline silicon thin-film transistors in n-channel and p-channel operation modes.
threshold voltage. For the ambipolar TFTs reported in this paper, we have not performed a systematic study of the transistors behavior under bias stress. However, subsequent measurements of the transistors lead to a shift of the device threshold voltage by 50–150 mV. 3.2. Ambipolar inverters Ambipolar transistors provide a simple route in realizing integrated circuits like radio frequency identification tags (RFID tags) or line and row drivers for display applications since separate patterning steps for n- and p-type doped layers can be eliminated. In the following the ambipolar transistors were used to realize inverters, which are the basic building blocks for many other integrated circuits. The circuit implementation of an ambipolar inverter is shown in Fig. 5 [22]. The inverter is realized by integrating two ambipolar thin-film transistors, one of which is meant for p-channel operation while the other is for n-channel operation. The upper ambipolar TFT is meant for p-channel operation while the lower ambipolar TFT is for n-channel operation. The input signal of the inverter, VIN, is applied to the gate terminals of both ambipolar TFTs, while the
Fig. 5. Schematic circuit of an ambipolar inverter, which is realized by integrating two ambipolar thin-film transistors (TFTs), one of which operates as a ‘p-channel’ TFT while the other operates as an ‘n-channel’ TFT.
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is not the case for ambipolar inverters. The increase of the output voltage with increasing operating voltage leads to a drop of the noise margin for high operating voltages. The given ambipolar inverter curves in Fig. 6 exhibit the highest noise margin for an operation voltage of 4 V, while maintaining a high voltage gain of the inverter. The noise margin of the ambipolar inverter based on the low temperature fabricated microcrystalline silicon is sensitive to the variation of the threshold voltage of the constituent TFTs. Future studies are necessary to systematically investigate the influence of the variation of the threshold voltage on the electrical characteristics of the inverter. It can be concluded that ambipolar inverters are an interesting addition to existing CMOS inverter technology. However, the specific disadvantages of the technology have to be taken into account when designing ambipolar inverter based circuitry. 4. Conclusions Fig. 6. Voltage transfer characteristics of an ambipolar inverter measured at supply voltages, VDD, of 3 V, 4 V, 5 V and 6 V. The inverter consists of an ambipolar thin-film transistor (TFT) with a channel width, W, of 1000 lm and a channel length, L, of 20 lm for p-channel operation, and an ambipolar TFT with a channel width of 200 lm and a channel length of 20 lm for n-channel operation.
drain terminal of the lower ambipolar TFT serves as output voltage, VOUT, for the inverter. The source terminal of the upper ambipolar TFT is connected to the supply voltage of the inverter, VDD. If the input signal is equal to VDD, which is considered as logical high, the lower ambipolar TFT is conducting while the upper TFT (which has its gate-source voltage, VGS, equal to 0 V) is cut off. Hence the output voltage of the inverter, VOUT, is approximately equal to 0 V, representing a logical low. When the input signal is at ground or equal to 0 V which is considered as logical low, the lower TFT is cut off while the upper TFT is conducting, so that the VOUT is very close to VDD, representing a logical high. The experimental voltage transfer characteristics of an ambipolar inverter measured for positive supply voltages, VDD, of 3 V, 4 V, 5 V and 6 V are shown in Fig. 6. The voltage transfer curve was measured from low supply voltage (0 V) to high supply voltage (8 V). The ambipolar inverter was realized using an ‘n-channel’ ambipolar TFT with a channel length of 20 lm and a channel width of 200 lm, and a ‘p-channel’ ambipolar TFT with a channel length of 20 lm and a channel width of 1000 lm. The increased channel width of the transistor meant for p-channel operation compensates for the reduced hole charge charier mobility of the ambipolar transistor. The voltage transfer curve exhibits the typical features of ambipolar inverters. The ambipolar inverter exhibits a high voltage gain comparable to CMOS inverters. The experimentally extracted voltage gain, which is defined to be vGAIN = @VOUT/@VIN, where VOUT and VIN are the output and input voltage of the inverter, respectively, is equal to 5–10 and a clear and abrupt transition for the inverter output voltage from the logical high- to low-state was observed. The voltage gain of the realized ambipolar inverter is higher than the voltage gain of n-channel metal–oxide-semiconductor (NMOS) inverters based on microcrystalline silicon fabricated under comparable processing conditions [23]. On the other hand, the output voltage of the ambipolar microcrystalline inverter in the logical low-state increases with increasing input voltage, which can be explained by the high off-current of the constituent p-channel ambipolar microcrystalline silicon transistor at high drain voltages. As a consequence the noise margin of the ambipolar inverter is reduced and the power consumption is increased, which limit the realization of complex thin-film circuitry. The problem can only be reduced by selecting the right operating voltages of the inverter. Conventional CMOS inverters exhibit an increase of the noise margin with increasing operating voltages. However, this
In summary, ambipolar microcrystalline silicon TFTs were realized at low temperature of 160 °C with distinctively high electron and hole charge carrier mobilities of 60 cm2/Vs and 18 cm2/Vs, respectively. Based on the ambipolar microcrystalline silicon TFTs, ambipolar inverters were demonstrated which exhibit high voltage gains of 5–10. The contact effects of the ambipolar microcrystalline TFTs is more pronounced in the p-channel operation mode in comparison to the n-channel operation mode due to a lower hole charge carrier mobility compared to electron charge carrier mobility. The ambipolar transistors and inverters provide a simple route in realization of large area integrated circuits at low cost based on microcrystalline silicon. Acknowledgements The authors like to acknowledge S. Bunte and Y. Mohr (IBN-PT) for preparation of the PECVD SiO2, M. Hülsbeck, T. Melle, S. Michel, and R. Schmitz for technical assistances and E. Bunte, R. Carius, D. Hrunski, and V. Smirnov for helpful discussions. References [1] Tsukada T. Technology and applications of amorphous silicon. In: Street RA, editor. Springer series in material science, vol. 37. Berlin (Germany): SpringerVerlag; 2000. [2] Wong WS, Ready SE, Lu JP, Street RA. Hydrogenated amorphous silicon thinfilm transistor arrays fabricated by digital lithography. IEEE Electron Dev Lett 2003;24(9):577–9. [3] Kavak H, Shanks H. Stability of hydrogenated amorphous silicon thin-film transistors on polyimide substrates. Solid-State Electron 2005;49:578–84. [4] Brotherton SD. Polycrystalline silicon thin film transistors. Semicond Sci Technol 1995;10:721–38. [5] Tsai CC, Lee YJ, Wang JL, Wei KF, Lee IC, Chen CC, et al. High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallization. Solid-State Electron 2008;52: 365–71. [6] Cheng IC, Wagner S. Hole and electron field-effect mobilities in nanocrystalline silicon deposited at 150 °C. Appl Phys Lett 2002;80(3):440–2. [7] Lee CH, Sazonov A, Nathan A. High-mobility nanocrystalline silicon thin-film transistors fabricated by plasma-enhanced chemical vapor deposition. Appl Phys Lett 2005;86:222106. [8] Chan KY, Bunte E, Stiebig H, Knipp D. Influence of contact effect on the performance of microcrystalline silicon thin-film transistors. Appl Phys Lett 2006;89:203509. [9] Vetterl O, Finger F, Carius R, Hapke P, Houben L, Kluth O, et al. Intrinsic microcrystalline silicon: a new material for photovoltaics. Sol Energy Mater Sol Cells 2000;62:97–108. [10] Lee CH, Sazonov A, Rad MRE, Chaji GR, Nathan A. Ambipolar thin-film transistors fabricated by PECVD nanocrystalline silicon. Mater Res Soc Symp Proc 2006;910. 0910-A22-05. [11] Shirai H, Arai T, Nakamura T. Control of the initial stage of nanocrystallite silicon growth monitored by in-situ spectroscopic ellipsometry. Appl Surf Sci 1997;113/114:111–5. [12] Cheng IC, Allen S, Wagner S. Evolution of nanocrystalline silicon thin-film transistor channel layers. J Non-Cryst Solids 2004;338–340:720–4.
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