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Influence of crystalline volume fraction on the performance of high mobility microcrystalline silicon thin-film transistors
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Journal of Non-Crystalline Solids 354 (2008) 2505–2508 www.elsevier.com/locate/jnoncrysol
Influence of crystalline volume fraction on the performance of high mobility microcrystalline silicon thin-film transistors Kah-Yoong Chan a,b,*, Dietmar Knipp a, Aad Gordijn b, Helmut Stiebig b a
Jacobs University Bremen, School of Engineering and Science, 28759 Bremen, Germany b Research Center Ju¨lich, IEF5-Photovoltaics 52425 Ju¨lich, Germany Available online 31 January 2008
Abstract The influence of the crystalline volume fraction of hydrogenated microcrystalline silicon on the device performance of thin-film transistors fabricated at temperatures below 200 °C was investigated. Transistors employing microcrystalline silicon channel material prepared close to the transition to amorphous growth regime exhibit the highest charge carrier mobilities exceeding 50 cm2/V s. The device parameters like the charge carrier mobility, the threshold voltage and the subthreshold slope will be discussed with respect to the crystalline volume fraction of the intrinsic microcrystalline silicon material. Ó 2007 Elsevier B.V. All rights reserved. PACS: 85.30.De; 85.30.Tv Keywords: Silicon; Thin-film transistors
1. Introduction Thin-film transistors (TFTs) are essential in large area electronics. To date, TFTs based on amorphous silicon (a-Si:H) are widely used as pixel switches for display backpanels [1]. However, the realization of more complex peripheral circuitry is not possible due to low charge carrier mobility and device instability of a-Si:H [1–3]. So far external drivers are needed or the circuitry has to be realized by polycrystalline silicon (poly-Si) TFTs with high charge carrier mobilities and stable threshold voltages [1]. However, the fabrication cost of poly-Si TFTs is higher due to high fabrication temperatures or additional laser crystallization steps. Hydrogenated microcrystalline silicon (lc-Si:H) is a promising alternative to existing technologies due to its
* Corresponding author. Address: Jacobs University Bremen, School of Engineering and Science, 28759 Bremen, Germany. Tel.: +49 2461 61 2069; fax: +49 2461 61 3735. E-mail address: [email protected] (K.-Y. Chan).
0022-3093/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2007.09.035
high mobility. The material consists of amorphous phases, crystallites, and voids [4], and is usually deposited at low temperature by plasma-enhanced chemical vapor deposition (PECVD) using a high hydrogen dilution. The material properties are influenced by the silane concentration (SC) during the deposition (SC = SiH4/(SiH4 + H2), where SiH4 is the silane flow rate and H2 is the hydrogen flow rate) [4], the applied plasma power [4] and the plasma excitation frequency [5]. The microstructure of the lc-Si:H can be varied from highly crystalline to material where amorphous growth prevails. In recent years, lc-Si:H has been deployed as active material in TFTs and high charge carrier mobilities have been demonstrated [6–8]. This paper reports on the fabrication and characterization of high mobility top-gate staggered TFTs employing intrinsic (i) lc-Si:H as channel layer. The properties of the channel layer were varied from highly crystalline to material where amorphous growth prevails. We investigated the dependence of the device parameters like the electron charge carrier mobility, threshold voltage and subthreshold slope on the crystalline volume fraction (XC) of the lc-Si:H channel material.
K.-Y. Chan et al. / Journal of Non-Crystalline Solids 354 (2008) 2505–2508
2. Experiments A schematic cross-section of the investigated lc-Si:H TFTs is depicted in Fig. 1. The drain and source contacts of the TFTs were realized by chromium. Afterwards, a n-type lc-Si:H film with a dark conductivity of 10 S/cm (activation energy = 17 meV) was deposited by PECVD at 190 °C to form ohmic contacts between the drain and source electrodes and the i-lc-Si:H channel material. The i-lc-Si:H film with a thickness of 100 nm was prepared by PECVD at 160 °C, in the high pressure (1330 Pa) and high power (0.3 W/cm2) regime, which facilitates the deposition of material at high deposition rates of up to 25 nm/ min [9]. The thickness of the channel layer was chosen to be 100 nm to insure high quality microcrystalline silicon on the film surface, which forms the channel of the transistor [4,10]. On the other hand, the channel layer should be thin to minimize the series resistance between the drain/source electrode and the accumulation region close to the gate dielectric [11]. The crystalline volume fraction of the i-lcSi:H channel layer was varied by changing the silane concentration in the source gas mixture from 0.5% to 1.5%. Raman spectroscopy (laser wavelength = 488 nm) was employed to estimate the crystalline volume fraction of the i-layers according to the formula: I 500 þ I 520 XC ¼ ; I 480 þ I 500 þ I 520
ð1Þ
where I480, I500 and I520 are the areas of the corresponding Gaussian peaks used to fit the measured Raman spectra near 480 cm1 (associated with the amorphous phase), 500 cm1 and 520 cm1 (associated with the crystalline phase), respectively. The amorphous volume in the nucleation region of the intrinsic microcrystalline silicon film may contribute partly to the measured Raman signal. Therefore, the actual crystalline volume fraction of the channel can be underestimated, in particular for film with low XC. Upon increase of the SC from 0.5% to 1%, the i-lc-Si:H layer exhibits a decrease in the crystalline volume fraction from 66% to 47%. The crystalline volume fraction drops dramatically to around 5% when the SC is increased
to 1.3% and 1.5%. A silane concentration of 1% is considered as the transition to the amorphous growth regime. Solar cells prepared close to the transition regime yield the highest efficiency [9]. The n- and i-layers were prepared at an excitation frequency of 13.56 MHz. Following the deposition of the i-layer, a gate dielectric of 300 nm was prepared by PECVD at 150 °C. Finally, the gate electrode was formed by an aluminum film. To allow for the fast evaluation of the materials and the device properties, a simple two-mask photolithography process was developed. In order to improve the device behavior all transistors were annealed at an elevated temperature of 150 °C for 30 min under ambient conditions. A detailed description of the influence of thermal annealing on the device characteristics is given elsewhere [12]. In this study only transistors with a channel length of 200 lm were investigated as the influence of drain and source contact resistance on the device parameters is reduced for long channel transistors [13]. The device characterization was performed at room temperature under dark conditions. 3. Results and discussion The transfer characteristics of a lc-Si:H TFT (i-layer, XC = 54%) with a channel length of 200 lm and a channel width of 1000 lm is shown in Fig. 2. The transfer characteristics were measured for drain voltages, VD, of 0.1 V and 1 V. A linear charge carrier mobility of 55 cm2/V s and a threshold voltage of 3 V were extracted from the transfer characteristics. Even though the TFTs were realized at low temperatures the charge carrier mobility is 1E-4
L=200μm W/L=5
1E-5
VD=1V
=0.1V
Drain Current [A]
2506
1E-6
1E-7
1E-8
1E-9
XC=54% 1E-10
-4
-2
0
2
4
6
8
10
Gate Voltage [V] Fig. 1. Schematic cross-section of a top-gate staggered microcrystalline silicon thin-film transistor. The transistor was fabricated by using a twomask photolithographic process.
Fig. 2. Transfer characteristics of a microcrystalline silicon thin-film transistor with channel width of 1000 lm and channel length of 200 lm. The transfer curves were measured for drain voltage of 0.1 V and 1 V.
K.-Y. Chan et al. / Journal of Non-Crystalline Solids 354 (2008) 2505–2508
S¼
1
2
L=200μm W/L=5 VD =1V 0.1 0
10
20
30
40
50
60
70
1
0 80
Subthreshold Slope [V/decade]
3
Threshold Voltage [V]
4
ð2Þ
1018
1.2
5
10
oV G q kB T N T d S ¼ ; oðlogðI Dsub ÞÞ C G log10 ðeÞ
which directly correlates the extracted slope with the material parameters. Here IDsub is the drain current in the below threshold regime, and q, kB, T, NT, and dS are the electron charge, the Boltzmann constant, the temperature, the defect density in lc-Si:H, and the lc-Si:H channel layer thickness, respectively. Using Eq. (2), the defect densities for the TFTs with XC = 5%, 54% and 66% can be calculated to be 1017 cm3 eV1, 4 1016 cm3 eV1 and 7 1016 cm3 eV1, respectively. The defect density determined for material with a crystalline volume fraction of 54% is comparable
6
100
Mobility [cm2/Vs]
necessary to study the formation of the voids and the influence of these voids on the charge carrier mobility. No clear correlation is observed between the threshold voltage and the crystalline volume fractions (Fig. 3), since the threshold voltage depends not only on the defect density of the channel material, but also on the work function difference between the gate metal and the semiconductor and trapped charges within the gate oxide and its interface with the channel material [19]. The subthreshold slope as a function of the crystalline volume fraction of the channel material is shown in Fig. 4. The extracted subthreshold slope is high (>0.76 V/ decade) for TFTs employing channel material with a low crystalline volume fraction (XC 5%). For TFTs with a higher crystalline volume fraction (XC = 54% and 66%), the subthreshold slope decreases (0.34 V/decade and 0.58 V/decade, respectively). The subthreshold slopes extracted for TFTs with channel material grown close to the transition to amorphous growth regime are apparently lower compared to the highly crystalline regime. The subthreshold slope of the TFTs can be described by the following equation [19]:
L=200μm W/L=5
1.0
VD =1V 0.8
1017 0.6
0.4
0.2 0
10
20
30
40
50
60
70
80
Defect Density [cm-3eV-1]
significantly higher than the mobility of conventional a-Si TFTs (1 cm2/V s) prepared by PECVD. The on/off ratio of the TFT for low drain voltages is larger than 105. The observed gate leakage current is two to three orders of magnitude smaller than the corresponding drain current at high gate voltage. The electron mobility and threshold voltage of the TFTs as a function of the crystalline volume fraction of the i-lcSi:H channel material are shown in Fig. 3. The mobilities and threshold voltages were extracted from the transfer characteristics measured at a drain voltage of 1 V. For the TFTs employing an i-lc-Si:H channel layer with a low crystalline volume fraction (XC 5%), the extracted mobilities are below 1 cm2/V s, resembling the mobility values obtained for a-Si:H TFTs. The TFTs with a crystalline volume fraction of XC = 47% and 54% exhibit the highest charge carrier mobility of 52 cm2/V s and 55 cm2/V s, respectively. For TFTs with higher XC, the extracted mobility decreases. In the case of TFTs with XC = 66%, the extracted mobility drops to 34 cm2/V s. The mobility is highest for intrinsic material grown close to the transition to the amorphous growth regime. This behavior differs from the investigations of the Hall mobility for lc-Si:H bulk layers, which show that the Hall mobility increases with increasing crystalline volume fraction [14,15]. For the investigated lc-Si:H TFTs, the drop of the charge carrier mobility for high XC can be likely attributed to the high void fraction and the defects associated with cracks on the surface between the crystalline columns in the highly crystalline material [4,16,17]. This can affect the electron transport along the channel. The surface roughness itself can not be the reason for a decrease of the mobility since a lower roughness is observed for lc-Si:H grown in the highly crystalline regime in comparison to material grown close to the transition region [18]. However, further investigations are
2507
1016
Crystalline Volume Fraction [%]
Crystalline Volume Fraction [%]
Fig. 3. Extracted electron mobility (open squares) and threshold voltage (open circles) as a function of crystalline volume fraction of the channel material for microcrystalline silicon thin-film transistors. Lines are drawn as guides for the eyes.
Fig. 4. Extracted subthreshold slope (open squares) and calculated defect density (open circles) as a function of crystalline volume fraction of the channel material for microcrystalline silicon thin-film transistors. Lines are drawn as guides for the eyes.
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K.-Y. Chan et al. / Journal of Non-Crystalline Solids 354 (2008) 2505–2508
to the value reported by Lee et al. [20]. Furthermore, the determined defect density is in good agreement with values estimated by electron spin resonance (ESR) and detailed analysis of directly deposited microcrystalline silicon [21,22]. The measurement of the subthreshold slope and the corresponding defect density confirm the results observed for microcrystalline diodes, in which the lowest defect density is obtained for the lc-Si:H grown close to the transition to amorphous growth regime, where the crystalline phase is passivated by the amorphous phase [4,22]. For TFTs with XC 5%, the determined defect density is higher than the one estimated by ESR and device analysis. This can be explained by the influence of the nucleation layer on the electronic properties of the thin lc-Si:H channel layer investigated here. The nucleation region is thicker for lc-Si:H film prepared in the low crystalline regime compared to highly crystalline regime [23,24]. Therefore, the influence of the nucleation region on the electronic properties and material qualities of thin layers is more pronounced for films with low XC. Another reason that might partly explain the enhanced defect density in this low crystalline regime can be the altered interface properties of the SiO2 gate dielectric and the channel material [25]. 4. Summary Top-gate microcrystalline silicon TFTs were realized with high electron mobilities exceeding 50 cm2/V s and average threshold voltages in the range of 3 V. The experimental results reveal that the highest mobility is obtained when the intrinsic microcrystalline silicon channel material is grown close to the transition to amorphous growth regime. The defect densities determined from the subthreshold regime of the TFTs characteristics follow the data derived from material and diode investigations, of which the lowest defect density is observed for microcrystalline silicon channel material grown close to transition to amorphous growth regime. Acknowledgements The authors like to acknowledge S. Bunte and Y. Mohr (IBN-PT) for preparation of the PECVD SiO2, M. Hu¨lsbeck, J. Kirchhoff, T. Melle, S. Michel, and R. Schmitz
for technical assistances and E. Bunte, R. Carius, D. Hrunski, S. Reynolds and V. Smirnov for helpful discussions. References [1] T. Tsukada, in: R.A. Street (Ed.), Technology and Applications of Amorphous Silicon, Springer Series in Material Science, Vol. 37, Springer, Berlin, Germany, 2000. [2] Y.J. Choi, W.K. Kwak, K.S. Cho, S.K. Kim, J. Jang, IEEE Electr. Dev. Lett. 21 (1) (2000) 18. [3] B. Stannowski, R.E.I. Schropp, R.B. Wehrspohn, M.J. Powell, J. Non-Cryst. Solids 299–302 (2002) 1340. [4] O. Vetterl, F. Finger, R. Carius, P. Hapke, L. Houben, O. Kluth, A. Lambertz, A. Mu¨ck, B. Rech, H. Wagner, Sol. Energy Mater. Sol. Cells 62 (2000) 97. [5] F. Finger, P. Hapke, M. Luysberg, R. Carius, H. Wagner, M. Scheib, Appl. Phys. Lett. 65 (20) (1994) 2588. [6] I.-C. Cheng, S. Wagner, Appl. Phys. Lett. 80 (3) (2002) 440. [7] C.-H. Lee, A. Sazonov, A. Nathan, Appl. Phys. Lett. 86 (2005) 222106. [8] K. Kandoussi, A. Gaillard, C. Simon, N. Coulon, T. Pier, T. Mohammed Brahim, J. Non-Cryst. Solids 352 (2006) 1728. [9] B. Rech, T. Roschek, T. Repmann, J. Mu¨ller, R. Schmitz, W. Appenzeller, Thin Solid Films 427 (2003) 157. [10] H. Shirai, T. Arai, T. Nakamura, Appl. Surf. Sci. 113&114 (1997) 111. [11] I.-C. Cheng, S. Allen, S. Wagner, J. Non-Cryst. Solids 338–340 (2004) 720. [12] K.-Y. Chan, E. Bunte, H. Stiebig, D. Knipp, J. Appl. Phys. 101 (2007) 074503. [13] K.-Y. Chan, E. Bunte, H. Stiebig, D. Knipp, Appl. Phys. Lett. 89 (2006) 203509. [14] T. Bronger, R. Carius, Thin Solid Films (2007), doi:10.1016/ j.tsf.2006.11.091. [15] K. Shimakawa, J. Non-Cryst. Solids 266–269 (2000) 223. [16] M. Tzolov, F. Finger, R. Carius, P. Hapke, J. Appl. Phys. 81 (11) (1997) 7376. [17] R.W. Collins, B.Y. Yang, J. Vac. Sci. Technol. B 7 (5) (1989) 1155. [18] J. Kocka, T. Mates, H. Stuchlikova, J. Stuchlik, A. Fejfar, Thin Solid Films 501 (2006) 107. [19] D.W. Greve, Thin-Film Transistors, Field Effect Devices and Applications: Devices for Portable, Low-Power, and Imaging Systems, 1st Ed., Prentice Hall, 1998 (Chapter 7), p. 286. [20] C.-H. Lee, A. Sazonov, A. Nathan, Mater. Res. Soc. Symp. Proc. 862 (2005) A17.5.1. [21] F. Finger, J. Mu¨ller, C. Malten, H. Wagner, Philos. Mag. B 77 (1998) 805. [22] T. Brammer, H. Stiebig, J. Appl. Phys. 94 (2) (2003) 1035. [23] A.S. Ferlauto, R.J. Koval, C.R. Wronski, R.W. Collins, Appl. Phys. Lett. 80 (15) (2002) 2666. [24] H. Stiebig, T. Brammer, J. Zimmer, O. Vetterl, H. Wagner, J. NonCryst. Solids 266–269 (2000) 1104. [25] M. Powell, C. van Berkel, A.R. Franklin, S.C. Deane, W.I. Milne, Phys. Rev. B 45 (8) (1992) 4160.
Journal of Non-Crystalline Solids 354 (2008) 2505–2508 www.elsevier.com/locate/jnoncrysol
Influence of crystalline volume fraction on the performance of high mobility microcrystalline silicon thin-film transistors Kah-Yoong Chan a,b,*, Dietmar Knipp a, Aad Gordijn b, Helmut Stiebig b a
Jacobs University Bremen, School of Engineering and Science, 28759 Bremen, Germany b Research Center Ju¨lich, IEF5-Photovoltaics 52425 Ju¨lich, Germany Available online 31 January 2008
Abstract The influence of the crystalline volume fraction of hydrogenated microcrystalline silicon on the device performance of thin-film transistors fabricated at temperatures below 200 °C was investigated. Transistors employing microcrystalline silicon channel material prepared close to the transition to amorphous growth regime exhibit the highest charge carrier mobilities exceeding 50 cm2/V s. The device parameters like the charge carrier mobility, the threshold voltage and the subthreshold slope will be discussed with respect to the crystalline volume fraction of the intrinsic microcrystalline silicon material. Ó 2007 Elsevier B.V. All rights reserved. PACS: 85.30.De; 85.30.Tv Keywords: Silicon; Thin-film transistors
1. Introduction Thin-film transistors (TFTs) are essential in large area electronics. To date, TFTs based on amorphous silicon (a-Si:H) are widely used as pixel switches for display backpanels [1]. However, the realization of more complex peripheral circuitry is not possible due to low charge carrier mobility and device instability of a-Si:H [1–3]. So far external drivers are needed or the circuitry has to be realized by polycrystalline silicon (poly-Si) TFTs with high charge carrier mobilities and stable threshold voltages [1]. However, the fabrication cost of poly-Si TFTs is higher due to high fabrication temperatures or additional laser crystallization steps. Hydrogenated microcrystalline silicon (lc-Si:H) is a promising alternative to existing technologies due to its
* Corresponding author. Address: Jacobs University Bremen, School of Engineering and Science, 28759 Bremen, Germany. Tel.: +49 2461 61 2069; fax: +49 2461 61 3735. E-mail address: [email protected] (K.-Y. Chan).
0022-3093/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.jnoncrysol.2007.09.035
high mobility. The material consists of amorphous phases, crystallites, and voids [4], and is usually deposited at low temperature by plasma-enhanced chemical vapor deposition (PECVD) using a high hydrogen dilution. The material properties are influenced by the silane concentration (SC) during the deposition (SC = SiH4/(SiH4 + H2), where SiH4 is the silane flow rate and H2 is the hydrogen flow rate) [4], the applied plasma power [4] and the plasma excitation frequency [5]. The microstructure of the lc-Si:H can be varied from highly crystalline to material where amorphous growth prevails. In recent years, lc-Si:H has been deployed as active material in TFTs and high charge carrier mobilities have been demonstrated [6–8]. This paper reports on the fabrication and characterization of high mobility top-gate staggered TFTs employing intrinsic (i) lc-Si:H as channel layer. The properties of the channel layer were varied from highly crystalline to material where amorphous growth prevails. We investigated the dependence of the device parameters like the electron charge carrier mobility, threshold voltage and subthreshold slope on the crystalline volume fraction (XC) of the lc-Si:H channel material.
K.-Y. Chan et al. / Journal of Non-Crystalline Solids 354 (2008) 2505–2508
2. Experiments A schematic cross-section of the investigated lc-Si:H TFTs is depicted in Fig. 1. The drain and source contacts of the TFTs were realized by chromium. Afterwards, a n-type lc-Si:H film with a dark conductivity of 10 S/cm (activation energy = 17 meV) was deposited by PECVD at 190 °C to form ohmic contacts between the drain and source electrodes and the i-lc-Si:H channel material. The i-lc-Si:H film with a thickness of 100 nm was prepared by PECVD at 160 °C, in the high pressure (1330 Pa) and high power (0.3 W/cm2) regime, which facilitates the deposition of material at high deposition rates of up to 25 nm/ min [9]. The thickness of the channel layer was chosen to be 100 nm to insure high quality microcrystalline silicon on the film surface, which forms the channel of the transistor [4,10]. On the other hand, the channel layer should be thin to minimize the series resistance between the drain/source electrode and the accumulation region close to the gate dielectric [11]. The crystalline volume fraction of the i-lcSi:H channel layer was varied by changing the silane concentration in the source gas mixture from 0.5% to 1.5%. Raman spectroscopy (laser wavelength = 488 nm) was employed to estimate the crystalline volume fraction of the i-layers according to the formula: I 500 þ I 520 XC ¼ ; I 480 þ I 500 þ I 520
ð1Þ
where I480, I500 and I520 are the areas of the corresponding Gaussian peaks used to fit the measured Raman spectra near 480 cm1 (associated with the amorphous phase), 500 cm1 and 520 cm1 (associated with the crystalline phase), respectively. The amorphous volume in the nucleation region of the intrinsic microcrystalline silicon film may contribute partly to the measured Raman signal. Therefore, the actual crystalline volume fraction of the channel can be underestimated, in particular for film with low XC. Upon increase of the SC from 0.5% to 1%, the i-lc-Si:H layer exhibits a decrease in the crystalline volume fraction from 66% to 47%. The crystalline volume fraction drops dramatically to around 5% when the SC is increased
to 1.3% and 1.5%. A silane concentration of 1% is considered as the transition to the amorphous growth regime. Solar cells prepared close to the transition regime yield the highest efficiency [9]. The n- and i-layers were prepared at an excitation frequency of 13.56 MHz. Following the deposition of the i-layer, a gate dielectric of 300 nm was prepared by PECVD at 150 °C. Finally, the gate electrode was formed by an aluminum film. To allow for the fast evaluation of the materials and the device properties, a simple two-mask photolithography process was developed. In order to improve the device behavior all transistors were annealed at an elevated temperature of 150 °C for 30 min under ambient conditions. A detailed description of the influence of thermal annealing on the device characteristics is given elsewhere [12]. In this study only transistors with a channel length of 200 lm were investigated as the influence of drain and source contact resistance on the device parameters is reduced for long channel transistors [13]. The device characterization was performed at room temperature under dark conditions. 3. Results and discussion The transfer characteristics of a lc-Si:H TFT (i-layer, XC = 54%) with a channel length of 200 lm and a channel width of 1000 lm is shown in Fig. 2. The transfer characteristics were measured for drain voltages, VD, of 0.1 V and 1 V. A linear charge carrier mobility of 55 cm2/V s and a threshold voltage of 3 V were extracted from the transfer characteristics. Even though the TFTs were realized at low temperatures the charge carrier mobility is 1E-4
L=200μm W/L=5
1E-5
VD=1V
=0.1V
Drain Current [A]
2506
1E-6
1E-7
1E-8
1E-9
XC=54% 1E-10
-4
-2
0
2
4
6
8
10
Gate Voltage [V] Fig. 1. Schematic cross-section of a top-gate staggered microcrystalline silicon thin-film transistor. The transistor was fabricated by using a twomask photolithographic process.
Fig. 2. Transfer characteristics of a microcrystalline silicon thin-film transistor with channel width of 1000 lm and channel length of 200 lm. The transfer curves were measured for drain voltage of 0.1 V and 1 V.
K.-Y. Chan et al. / Journal of Non-Crystalline Solids 354 (2008) 2505–2508
S¼
1
2
L=200μm W/L=5 VD =1V 0.1 0
10
20
30
40
50
60
70
1
0 80
Subthreshold Slope [V/decade]
3
Threshold Voltage [V]
4
ð2Þ
1018
1.2
5
10
oV G q kB T N T d S ¼ ; oðlogðI Dsub ÞÞ C G log10 ðeÞ
which directly correlates the extracted slope with the material parameters. Here IDsub is the drain current in the below threshold regime, and q, kB, T, NT, and dS are the electron charge, the Boltzmann constant, the temperature, the defect density in lc-Si:H, and the lc-Si:H channel layer thickness, respectively. Using Eq. (2), the defect densities for the TFTs with XC = 5%, 54% and 66% can be calculated to be 1017 cm3 eV1, 4 1016 cm3 eV1 and 7 1016 cm3 eV1, respectively. The defect density determined for material with a crystalline volume fraction of 54% is comparable
6
100
Mobility [cm2/Vs]
necessary to study the formation of the voids and the influence of these voids on the charge carrier mobility. No clear correlation is observed between the threshold voltage and the crystalline volume fractions (Fig. 3), since the threshold voltage depends not only on the defect density of the channel material, but also on the work function difference between the gate metal and the semiconductor and trapped charges within the gate oxide and its interface with the channel material [19]. The subthreshold slope as a function of the crystalline volume fraction of the channel material is shown in Fig. 4. The extracted subthreshold slope is high (>0.76 V/ decade) for TFTs employing channel material with a low crystalline volume fraction (XC 5%). For TFTs with a higher crystalline volume fraction (XC = 54% and 66%), the subthreshold slope decreases (0.34 V/decade and 0.58 V/decade, respectively). The subthreshold slopes extracted for TFTs with channel material grown close to the transition to amorphous growth regime are apparently lower compared to the highly crystalline regime. The subthreshold slope of the TFTs can be described by the following equation [19]:
L=200μm W/L=5
1.0
VD =1V 0.8
1017 0.6
0.4
0.2 0
10
20
30
40
50
60
70
80
Defect Density [cm-3eV-1]
significantly higher than the mobility of conventional a-Si TFTs (1 cm2/V s) prepared by PECVD. The on/off ratio of the TFT for low drain voltages is larger than 105. The observed gate leakage current is two to three orders of magnitude smaller than the corresponding drain current at high gate voltage. The electron mobility and threshold voltage of the TFTs as a function of the crystalline volume fraction of the i-lcSi:H channel material are shown in Fig. 3. The mobilities and threshold voltages were extracted from the transfer characteristics measured at a drain voltage of 1 V. For the TFTs employing an i-lc-Si:H channel layer with a low crystalline volume fraction (XC 5%), the extracted mobilities are below 1 cm2/V s, resembling the mobility values obtained for a-Si:H TFTs. The TFTs with a crystalline volume fraction of XC = 47% and 54% exhibit the highest charge carrier mobility of 52 cm2/V s and 55 cm2/V s, respectively. For TFTs with higher XC, the extracted mobility decreases. In the case of TFTs with XC = 66%, the extracted mobility drops to 34 cm2/V s. The mobility is highest for intrinsic material grown close to the transition to the amorphous growth regime. This behavior differs from the investigations of the Hall mobility for lc-Si:H bulk layers, which show that the Hall mobility increases with increasing crystalline volume fraction [14,15]. For the investigated lc-Si:H TFTs, the drop of the charge carrier mobility for high XC can be likely attributed to the high void fraction and the defects associated with cracks on the surface between the crystalline columns in the highly crystalline material [4,16,17]. This can affect the electron transport along the channel. The surface roughness itself can not be the reason for a decrease of the mobility since a lower roughness is observed for lc-Si:H grown in the highly crystalline regime in comparison to material grown close to the transition region [18]. However, further investigations are
2507
1016
Crystalline Volume Fraction [%]
Crystalline Volume Fraction [%]
Fig. 3. Extracted electron mobility (open squares) and threshold voltage (open circles) as a function of crystalline volume fraction of the channel material for microcrystalline silicon thin-film transistors. Lines are drawn as guides for the eyes.
Fig. 4. Extracted subthreshold slope (open squares) and calculated defect density (open circles) as a function of crystalline volume fraction of the channel material for microcrystalline silicon thin-film transistors. Lines are drawn as guides for the eyes.
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to the value reported by Lee et al. [20]. Furthermore, the determined defect density is in good agreement with values estimated by electron spin resonance (ESR) and detailed analysis of directly deposited microcrystalline silicon [21,22]. The measurement of the subthreshold slope and the corresponding defect density confirm the results observed for microcrystalline diodes, in which the lowest defect density is obtained for the lc-Si:H grown close to the transition to amorphous growth regime, where the crystalline phase is passivated by the amorphous phase [4,22]. For TFTs with XC 5%, the determined defect density is higher than the one estimated by ESR and device analysis. This can be explained by the influence of the nucleation layer on the electronic properties of the thin lc-Si:H channel layer investigated here. The nucleation region is thicker for lc-Si:H film prepared in the low crystalline regime compared to highly crystalline regime [23,24]. Therefore, the influence of the nucleation region on the electronic properties and material qualities of thin layers is more pronounced for films with low XC. Another reason that might partly explain the enhanced defect density in this low crystalline regime can be the altered interface properties of the SiO2 gate dielectric and the channel material [25]. 4. Summary Top-gate microcrystalline silicon TFTs were realized with high electron mobilities exceeding 50 cm2/V s and average threshold voltages in the range of 3 V. The experimental results reveal that the highest mobility is obtained when the intrinsic microcrystalline silicon channel material is grown close to the transition to amorphous growth regime. The defect densities determined from the subthreshold regime of the TFTs characteristics follow the data derived from material and diode investigations, of which the lowest defect density is observed for microcrystalline silicon channel material grown close to transition to amorphous growth regime. Acknowledgements The authors like to acknowledge S. Bunte and Y. Mohr (IBN-PT) for preparation of the PECVD SiO2, M. Hu¨lsbeck, J. Kirchhoff, T. Melle, S. Michel, and R. Schmitz
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