Concurrent error detection in highly structure logic arrays

World Abstracts Papers published which are considered to be of technical merit will be abstracted and published in this, and subsequent issues of Microelectronics Journal. Integrated Circuit Technology Memories Microprocessors Optoelectronics Hybrids Discrete Devices Charged Coupled Devices Materials Production and Processing Testing Applications It is the intention of the Journal, to present readers with an easy reference to many of the important papers which have been published in journals throughout the world.

Integrated Circuit Technology Concurrent error detection in highly structured logic arrays W K FUCItS, C Y R CHEN, J A ABRAHAM (Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA) IEEE J. Solid State Circuits (USA), vol. SC-22, no. 4, pp. 583-594 (Aug. 1987) Two strategies for encoding the inputs and outputs of highly structured logic arrays (HSLAs) are introduced. The two schemes are particularly relevant for concurrent error detection of both permanent and nonpermanent errors in programmable logic arrays (PLAs) and read-only memories (ROMs). The first method of concurrent error detection (CED) is based on a comprehensive fault model and relies on detection of unidirection errors. The second approach relies on a detailed examined of decoder layouts resulting in fault tolerance through layout rules, which avoid failures causing undirectional errors. Efficient parity techniques are shown to provide a low-overhead solution to concurrent error detection when coupled with appropriate fault-avoidance techniques. (23 refs.) Applications of multi-valued logic to testing of binary and MVL circuits M SERRA (Dept. of Comput. Sci., Victoria Univ., BC, Canada) Int. J. Electron. (GB), vol. 63, no. 2, pp. 197-214 (Aug. 1987) Binary linear feedback shift registers (LFSRs) have acquired great importance in their implementation of a method of data compaction used in the testing of digital circuits. The author examines a new idea: using multiple valued LFSRs for the testing of MVL circuits and o.f binary circuits. For MVL circuits a non-binatT LFSR avoids the need of decoding the signals and its implementation requires fewer digits than the binary

tester. For binary circuits, a multi-valued LFSR tester shows higher effectiveness while maintaining a smaller implementation. An analysis is given of fault coverage for binary and multi-valued circuits, and optimal implementations of multi-valued LFSRs are presented. (11 refs.) Four-valued interface circuits for NMOS VLSI A D SINGH (DepL of Electr. & CompuL Eng., Massachusetts Univ., AmhersL MA, USA) Int. J. Electron. (GB), voh 63, no. 2, pp. 269-279 (Aug. 1987) Presents radix 4 to binary cncoder and decoder interface circuits for NMOS VLSI. The circuits can be implemented using standard binary NMOS fabrication processes and are designed to operate correctly over the entire target range of device parameters specified by MOSIS. They have been simulated using SPICE with the typical parameters provided by MOSIS, and found to work correctly. Thus these circuits can be readily used to reduce pinouts of binary NMOS logic chips, and thereby allow significant cost savings. (9 refs.) Ternary logic based on a novel MOS building block circuit H M AYTAC Int. J. Electron. (GB), vol. 63, no. 2, pp. 241-251 (Aug. 1987) A pair of ternary logic circuits which cyclically permute the logic levels 0, 1, 2 are described. The circuits are implemented in CMOS augmented with depletion loads. Practical ranges for logic levels and threshold voltages are shown to exist and time dependent behaviour is discussed. The logic properties of the circuits (called permutators) and their derivatives are described. This ternary logic family is shown to be a natural extension of the binary logic family based on

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