D Converter Using new Types of Switched-Current Memory Cells

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Copyright © IF AC Programmable Devices and Systems, Ostrava, Czech Republic, 2003

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HIGH-PERFORMANCE DESIGN APPROACH TO ALGORITHMIC AID CONVERTER USING NEW TYPES OF SWITCHED-CURRENT MEMORY CELLS

Ondrej ~ubrt and Petr Drechsler ASICefltrum s.r.o., Novodvorskd 994, 14221 Praha 4, Czech Republic phone: +420239043 647 e-mail: [email protected]

Abstract: This work contributes to high-performance approach in the design of switched current ND converter based on algorithmic binary search. The system accuracy was significantly improved applying some changes in the conventional circuit structure, namely implementing new types of switched-current memory cells, called S3I-GGAcasc. Concrete results are illustrated in the following example of 8-bit ND converter, whitch is realized by standard 2.4 ~m Mietec-Alcatel CMOS technology. The overall performance is affected both by the technology limits and the real circuit behaviour of the proposed structure, which is based on the newly developed memory cells. Thus, the frrst part of the contribution is devoted to detailed analysis of the S3I-GGA-casc structure, with respect to the most important non-ideal properties and ways of parameteroptimization. The second part describes some technology-based hints and tips which were successfully applied in order to further increase the overall performance. Simulation results done in Mentor Graphics software are presented. Copyright © 2003 IFAC Keywords: ND converters, Switched-Current, Successive approximation technique

to 8 bit or higher (assuming the standard 2.4 ~m technology). This performance limit can be overcomed in two ways - using more progressive technology (e.g. 0.7 ~m, but not available in our case) or improving the circuit structure in order to achieve a low-cost and powerful ADC design. Hence, the second way of design-flow was chosen and new types of high performance SI cells especially optimized for use in the ADC structure were successfully designed and tested.

I. INTRODUCTION This paper presents the possibilities of highperformance approach applied to the concrete circuit structure of switched-cutrent (SI) analog-to-digital converter, which uses one-bit successive approximation technique. This technique corresponds to the known principle of algorithmic binary search, as described in [1]. Therefore, the resulting architecture of the proposed ADC is simple and consists of only few SI memory cells, which realize all the algorithmic operations, i.e. multiplication, subtraction and comparison (the principle of operation will be explained in section 4). Since the SI cells are the basic building blocks of the ADC, their parameters have decisive influence to the converter performance. As discussed below, charge injection and input-output conductance ratio seem to be the most important parameters, which disable the realization of the algorithmic ADC of resolution up

2. NEW S3I-GGA-CASC MEMORY CELL ARCHITECTURE In this section, a new type of high precision SI memory cell will be introduced. The structure consists of three known SI cell architectures (S31, GGA and cascade), which were significantly

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Fig. I S3I-GGA-casc current memory cell: a) schematic, b) timing diagram rearranged and coupled together in order the new block becomes the particulary advantages of each cell type. The resulting cell is shown in Fig. la. The basic operation of the whole cell is controlled by the GGA-AMP section (transistors Tgga, Tp, Tn - see the dashed block), which creates the concept of negative feedback and detennines the circuit behaviour in the input (current-sampling) phase. The rest of the cell includes the S31 "fine" and "coarse" current memory [2], which are built on regulated cascode circuits comprising two transistors Tc and the memorizing transistor Tm. With respect to use two S31 current memories, the whole cell provides a two-step sampling process - see Fig. I b, where the first phase is divided into coarse and fine. On the coarse phase, the switches TG I to TG3 are closed and the circuit behaves like a standard GGA cell. The coarse memory and the GGA-AMP block introduce the feedback loop which establishes the drain current of the coarse memory transistor by keeping the input voltage close to a constant value. This effect results in a very small input resistance of the proposed S31GGA-casc cell which is the main advantage in comparison with the basic structures. On the fine input sampling phase, the TGI and TG3 are open and the resulting circuit behaves as the known S21 memory cell [2] providing effective technique of charge-injection cancellation. Finally, on the output phase, a very small output conductance of the cell is achieved due to regulated cascode-effects. Further details about the S31-GGA-casc operation are shown in the literature [3].

3. SIMULATED RESULTS AND PERFORMANCE OPTIMIZATION OF THE CELL In general, the description of non-ideal circuitbehaviour of the proposed S31-GGA-casc cell can bedivided into two sections called static and dynamic precision. The most important aspects of the dynamic precision are detennined by charge injection and settling time effects. In our design, the charge injection errors are suppressed in two ways - by optimum switch arrangement and by the S3I error cancellation process, as shown in the previous chapter. The optimum switch arrangement was the crucial part of our design [4]: several types of improved dummy-switch architectures were tested and carefully optimized (see components NDUMMY and P-DUMMY in Fig. la, which form the so-called complementary half-sized devices). The static precision is formed by the steady-state circuit behaviour. In our case, the most important error sources are the finite input-output conductance ratio (see the previous chapter) and the dc precision aspects, including the problems of current biasing. The dcaccuracy is optimized by high precision current biasing circuit described in [5], which successfully generates the Vp, Vn and Vgga voltages in the final ADC design. All described types of errors have the influence to the total cell performance, which is illustrated in Fig. 2. The first waveform named In I is the signal current, which flows into the cell during the input or the output phase, respectively. Other waveforms represent the timing forces connected to the corresponding switches TG I 220

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Fig. 2 Simulated waveforms and performance results of the S31-GGA-casc cell to TG5 (Fig. 1). As obvious from the V/(Fla), the maximum clock frequency was set to 400 kHz. Note that all the simulations were done setting the relative current precision of I ppm. The input phase of the linl wavefonn (which is already divided into coarse and fine) shows perfect cancellation of the charge injection errors: the original input current at beginning of the coarse-phase (cursor 3) is successfully replicated during the fine phase (cursor 4) with only small transient overshoot. During the output phase, settling time is approximately 3.9 Ils because longer time is needed to establish the active load (another cell input). In fact, the settling time determines the relationship between the maximum conversion rate versus accuracy (as shown in the next section). Note that the specified value of 3.9 ~ correspond to guaranteed cell accuracy more than 12 bits (reI. error less than 0.03 %).

4. THE ADC DESIGN using the proposed type of high precision S31GGA-casc memory cell is shown in Fig. 3a, the timing diagram is in Fig. 3b. As evident, the whole system uses only one multiple-output cell, which realizes all the operations of known algorithmic binary search [1]. In principle, the converter follows sequential algorithmic steps I to 4, specified in Fig. 3b. First, the current 1nl is loaded into NI cell (step 1), the switch S2 is opened and NI holds the input current. Then the same current 1n2 is loaded into N2 (step 2), which results in the current-doubling in PNI (step 3). Finally, in the 4th step the doubled current is compared with lref, closing the S8 switch and stotiny the difference in the so-called "additional cell" (see Fig. 3a). The sign of the current difference is then stored in the MX & LATCH circuit, which conditionally drives

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the reference subtracting for the next converted bit. The main advantage of the presented ADC architecture in comparison with the standard structure [1] is the improvement of accuracy and stability during the 4th phase, when the circuit essentially behaves as a closed loop current comarator. Simulated results in Mentor Graphics software successfully confirmed this assumption the absolute current error of the ADC cells is lower than 40 nA, within the specified current conversion range of 0 to 128 !lA. Thus, the cell performance achieves up to 11 bit, including the influence of comparison process. The dynamic accuracy of the ADC is therefore higher than 9 bit, estimating the total cycle error by formulae given in [1]. Note that the above-mentioned accuracy value represent a trade-off for achieving the current settling time within 500 ns. Thus, the minimum clock period (the duration of the coarse or fine phase multiplied by two) can reach up to 1 J.I.S and the whole ADC achieves the minimum conversion period of 8*4*1 !ls = 32 !ls, with respekt to eight bits and four subphases. In order to achieve this advantageous speed-to-performance ratio, some additional hints and tips, corresponding to physical circuit implementation were implemented. The mask layout [4] of the system provides strong unity of repeated sections (S3I-GGA-casc cells) with separated analog and digital power lines in order to achieve better CMRR. To further increase the target accuracy, specific layout techniques of dummy switches and current biasing blocks were applied ([I], [6]). Note that the whole chip was designed as a universal cell providing wide scale of testing possibilities because external clock signals and variable biasing are available.

REFERENCES Toumazou, C., Hughes, J. B., Battersby, N. C. (1993) Switched-Currents - an analogue technique for digital technology, Peter Peregrinus, United Kingdom Hughes 1. B., Moulding K. W. (1997) The S3I cell. In: Proc. IEEE con! ISCAS 1997, Hong Kong, pp. 113-116 Subrt, 0., Drechsler, P. (2001) High precision switched-current memory cells and their implementation in a 8-bit algorithmic AID converter. In: Proc. Con! ECS 200J, Bratislava, Slovakia, pp. 105-108 Subrt, 0., Drechsler, P. (2000) The ANA06 internal project documentation. ASICentrum Nedved, J. (2000) A precise current biasing circuit, personal documentation. ASICentrum Vittoz, E. A. (1994) Layout of analog circuits. In : EUROCHIP course in advanced analog-digital design, Louvain-La-Neuve, Belgium 1994

5. CONCLUSIONS The design of switched-current memory cells, with respect to their implementation in the circuit structure of ADC, was the main aim of this contribution. Especially, the capabilities of further increase the system performance using standard 2.4 !lm technology were successfully proven. Circuit and layout techniques developed for this purpose shows the way of efficient design optimization, using relatively low costs on hardware and technology. The ADC speed is predominantly limited by settling time of SI cells and by the whole conversion algorithm, which allows the maximum conversion rate suitable e.g. for speech processing applications. The system has an original circuit conception, some blocks are very versatile and thus generally suitable for use in other switched-current designs.

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