D-HEMTs on InP substrates

Solid-State Electronics 50 (2006) 758–762 www.elsevier.com/locate/sse

Fabrication and characterization of In0.52Al0.48As/In0.53Ga0.47As E/D-HEMTs on InP substrates J.H. Jang a

a,*

, S. Kim b, I. Adesida

b

Department of Information and Communications, Gwangju Institute of Science and Technology, 1 Oryongdong Bukgu, Gwangju 500712, Republic of Korea b Micro and Nanotechnology Laboratory and Department of Electrical and Computer Engineering, University of Illinois, 208 N. Wright St., Urbana, IL 61801, USA Received 13 June 2005; accepted 16 April 2006

The review of this paper was arranged by C. Tu

Abstract The design, fabrication, and electrical characterization of enhancement-mode HEMTs (E-HEMTs) and depletion-mode HEMTs (DHEMTs) on a common InP substrate are reported. The integration of E- and D-HEMTs (E/D-HEMTs) is a potentially useful technology for the realization of high-speed, low-power digital circuits. The layer structures for E/D-HEMTs were optimized in terms of the thicknesses of the spacer and Schottky layers and sheet carrier concentration in the channel. The buried-Pt gate technology was utilized to achieve the desired threshold voltages for both 0.15 lm gate E- and D-HEMTs. The fabricated devices exhibited threshold voltages of 0.3 and 0.1 V, peak transconductance (Gm,max) values that are higher than 1020 and 1050 mS/mm, and the voltages where the peak transconductances occurred (Vgp) were 0.0 and 0.4 V for D- and E-HEMTs, respectively. Unity gain cut-off frequencies (fT’s) above 190 and 180 GHz were obtained for D-HEMTs and E-HEMTs, respectively.  2006 Elsevier Ltd. All rights reserved. Keywords: E/D-HEMT; InP; HEMT; Enhancement-mode; Depletion-mode HEMT

1. Introduction InP-based HEMTs have demonstrated record fT’s over 550 GHz [1]. These devices have been utilized to build analog millimeter wave integrated circuits such as low noise amplifiers and power amplifiers [2–4]. Recently, there have been active investigations on their potential applications in the area of digital circuits especially those for optical fiber communications that operate in excess of 40 Gbps [5–8]. However, the circuit integration level is quite limited due partly to the difficulty in designing highly functional circuits with only depletion-mode HEMTs (D-HEMTs) and also due to the non-uniformity of device characteristics as compared with other competing technologies. Designing *

Corresponding author. Tel.: +82 629702209; fax: +82 629702204. E-mail address: [email protected] (J.H. Jang).

0038-1101/$ - see front matter  2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2006.04.029

with D-HEMTs only results in high power dissipation because of high standby current flow and the larger number of devices required for circuits with same functionalities. By integrating enhancement-mode HEMTs (E-HEMTs) and D-HEMTs together, simpler approaches can be taken to circuit design and the integration level can be increased significantly [9–11]. Mixed signal integrated circuits have been demonstrated with GaAs-based E/D-HEMT technologies and their integration level is up to 26,000 devices [9]. Designers also can have more degrees of freedom with dual threshold voltages when designing circuits with E/DHEMTs than with D-HEMTs only. Power consumption can also be reduced by designing circuits with the same functionality using approximately half the number of transistors. The difficulties in developing high performance E/ D-HEMTs were due to the stringent specifications of threshold voltages for D- and E-HEMTs.

J.H. Jang et al. / Solid-State Electronics 50 (2006) 758–762

To achieve high performance E-HEMTs, buried-Pt gate technologies were employed to overcome the problem of excess source access resistance which can be caused by deep gate-recess in the fabrication of E-HEMTs [11–13]. There have been many attempts to realize E/D-HEMTs on a common substrate with various material systems. Significantly more investigations have been conducted in realizing E/D-HEMTs in GaAs-based materials than in InP-based materials [9,10]. Recently, a few papers on InP-based E/ D-HEMT technologies were published. Ring oscillators with 23 stages were demonstrated with InAlAs/InGaAs/ InP HEMTs which exhibited very low-power performance [11]. In this paper, improved performance for InP-based E/ D-HEMT technologies are reported in terms of current driving capabilities and speed by carefully designing device heterostructures including vertical scaling and high sheet carrier concentrations. 2. Growth and fabrication of E/D-HEMTs To achieve high-speed E-HEMTs and D-HEMTs, device heterostructures and gate dimensions must be scaled down simultaneously and reliable fabrication processes must be developed. Fig. 1 shows the device heterostructures used for the realization of E/D-HEMTs, and compares the layer structures used in this study with that used in an earlier study [11]. As shown in the figure, device heterostructure was vertically scaled in terms of the thickness of the spacer layer (ds), the thickness of Schottky layer (dd) for D-HEMTs, and the thickness of Schottky layer (de) for E-HEMTs. The sheet carrier density in the channel (ns) was also increased from 1.0 · 1012 to 2.0 · 1012 cm2. The gate delay of an inverter logic implemented using HEMTs is given by DV logic ðC gs þ C gd þ C int Þ I d;avg

ð1Þ

where DVlogic is the voltage swing required for logic transition, Id,avg is the average drain current, and Cgs, Cgd, and Cint are gate–source capacitance and gate–drain capacitance, and interconnect capacitance, respectively. As shown in Eq. (1), the drain current density should be increased to reduce the gate delay for a device with the same gate width. High current driving capability can be achieved by increasing the sheet carrier density in the channel (ns). However, it is limited by the requirement of the threshold voltage. The positive threshold voltage required for enhancement-mode HEMTs sets the upper bound of the sheet carrier density. For a given sheet carrier density, the Schottky layer and spacer layer can be scaled down to achieve positive threshold voltage by reducing the effective distance from the gate to the channel. When the spacer layer thickness is scaled down, the channel electron mobility is reduced by excess Coulomb scattering between the donor atoms and the channel electrons. Considering these facts, heterostructure design for HEMTs is as shown in Fig. 1 where it is compared to that used in a previous study [11]. To improve the current driving capability, the sheet carrier density was increased up to 2 · 1012 cm2. This is the measured value with the highly doped InGaAs cap layer removed. To deplete the increased channel carriers and to achieve positive threshold voltages for E-HEMTs, de was vertically scaled down to 6 nm. To optimize the thickness of the spacer layer, the dependencies of electron mobility and sheet carrier density on the thickness of spacer layer were investigated. With 4 nm thick spacer layer thickness, we obtained the desired sheet carrier density as well as very high electron mobility of over 9000 cm2/V s as shown in Fig. 2. When the spacer layer thickness was scaled down below 4.0 nm, the channel electron mobility decreased very rapidly. Therefore, the spacer thickness was set to 4.0 nm in this work. As mentioned above, the Schottky layer thickness was scaled down from 12 to 6 nm to achieve a positive

12

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Hall mobility (cm / Vs)

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sdelay /

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7000 2 6000 5

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Doping density (1019cm-3) Fig. 1. Heterostructures for monolithically integrated E/D-HEMTs on InP substrates.

Fig. 2. Sheet carrier concentrations and electron mobilities for device heterostructures with various spacer layer thicknesses. Hall measurements were carried out without highly doped cap layers.

J.H. Jang et al. / Solid-State Electronics 50 (2006) 758–762

DC and RF performances of E/D-HEMTs were measured and the effect of gate annealing was studied. As shown in Fig. 3, the threshold voltages measured after gate annealing process were 0.35 and 0.12 V and Idss were 370 and 11 mA/mm at the drain bias of 1.5 V for D- and EHEMTs, respectively. The peak transconductance (Gm) values for D-HEMT and E-HEMT are 1020 and 1050 mS/mm, respectively. These are more than 20% improved values compared with those of previous E/DHEMTs [11,13]. The high Gm’s can be ascribed to the very high electron mobility in the channel which is over

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threshold voltage. With this very thin E-Schottky layer, excellent E-HEMTs were successfully fabricated without degradation of device performances exemplified by excess gate leakage currents and an increase in source access resistance as seen in the previous studies on E-HEMTs devices [14]. Previously, the thickness of the D-Schottky layer was 10 nm thick [11]. At this thickness, the threshold voltage of D-HEMTs was found to be 0.7 V. This is too negative for circuit design applications. The threshold voltage of DHEMTs is dictated by the requirement that Vgp (gate bias voltage where Gm has peak value) for D-HEMT should be 0 V. To achieve the desired Vgp, and Vth for D-HEMT devices, the thickness of D-Schottky layer (dd) was reduced to 3.5 nm. The AlAs etch stop layer thickness was increased from 2 to 2.5 nm to ensure the etching selectivities. The device fabrication procedure included mesa and sidewall-recess etching for isolation using a mixture of citric acid and hydrogen peroxide, AuGe/Ni/Au ohmic contact formation, and gate formation. After depositing AuGe/Ni/Au, thermal alloying was performed at 420 C for 1 min. The measured contact resistance was less than 0.1 X mm. After the delineation of the gate in a tri-layer resist system utilizing electron beam lithography, wet gate recess etching was carried out. For the recess process for D-HEMTs, mixture of sucinnic acid and hydrogen peroxide was utilized to selectively etch the highly doped n+ InGaAs on the InAlAs D-Schottky layer. The gate recess for EHEMTs was performed utilizing a mixture of citric acid and hydrogen peroxide to etch the highly doped n+ InGaAs cap layer and InAlAs D-Schottky layer and stopping on top of the AlAs etch stop layer, which was then removed by diluted HCl just before gate metallization. Pt/Ti/Pt/Au metallization scheme was used for E- and DHEMTs gates, while Ti/Au and Pt/Ti/Pt/Au metallizations were utilized for D- and E-HEMTs, respectively in [11]. After lift-off process, gate annealing was carried out at 360 C for one minute in a nitrogen ambience for both the gate metallizations. When the gates are annealed at an elevated temperature, the threshold voltage was shifted in the positive direction, and the peak transconductance values also changed a little bit due to the increased Schottky barrier heights as well as the reduced effective thickness of the Schottky layer.

Drain current density (A/mm)

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Gate-source voltage (V)

Fig. 3. DC I–V characteristics of D-HEMTs (a) and E-HEMTs (b). Dotted lines for devices before gate annealing process and solid lines for the devices after gate annealing process.

10,000 cm2/V s despite the high sheet carrier density of 2 · 1012 cm2 with cap-off condition. By scaling down the Schottky layer thickness of D-HEMTs (dd = 3.5 nm, which was previously 10 nm), the maximum Gm of D-HEMTs could be placed at gate bias voltage of 0 V despite the high sheet carrier density in the channel. When this D-HEMT is diode-connected as an active load it will be automatically biased to an optimum condition for high speed in a direct-coupled FET logic circuit technology. Other heterostructures with different sheet carrier concentrations were grown and devices were fabricated on them. When the sheet carrier concentration was increased to 3.0 · 1012 cm2, VTH and Vgp of D-HEMTs were found to be 0.52 and 0.25 V, respectively. Even though the carrier concentration increased by 50%, the current density did not increase due to the reduced electron mobility, but the threshold voltages were negatively shifted. A significant problem for these devices with high sheet carrier concentration involved very low breakdown voltages. When the gate bias was 0.1 V, soft breakdown behavior began to appear at Vds of 1.6 V. When the sheet carrier concentration was 1.5 · 1012 cm2, VTH and Vgp of D-HEMTs and E-HEMTs could be engineered, but the current density were found to be 450 mA/mm. Fig. 4(a) and (b) illustrates the DC I–V

J.H. Jang et al. / Solid-State Electronics 50 (2006) 758–762

0.8

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characteristics of fabricated D- and E-HEMTs, respectively. The drain current density of D-HEMT is greater than 800 mA/mm at drain and gate bias voltages of 1.5 and 0.7 V, respectively, and that of E-HEMT is greater than 600 mA/mm at drain and gate bias voltages of 1.5 and 0.7 V, respectively. These values demonstrate improved current driving capabilities in comparison with previously reported E/D-HEMT device performances. This is due to the increased sheet carrier density and high electron mobilities in the channel. Due to the gate annealing process, Vgp’s were positive shifted by +0.3 and +0.36 V for D- and E-HEMTs, respectively. As shown in Fig. 4(a) and (b), kink effects can be observed in E-HEMTs, while kink effects are not prominent in D-HEMTs. After gate anneal, kink effects were alleviated and the linearity of E-HEMTs improved. The more adverse kink phenomenon in E-HEMTs in comparison with D-HEMTs can be ascribed to a wider recess region due to the longer recess depth. There is also the probability that the interaction between surface states on

761

0.5

1.0

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InAlAs and the accumulated holes on the source side is much larger in E-HEMTs in comparison with the case of D-HEMTs. RF characteristics have been measured for both unannealed and annealed the E/D-HEMT devices. Fig. 5(a) and (b) shows the unity current gain cut-off frequencies (fT’s) for D-HEMTs and E-HEMTs are 191 and 180 GHz, respectively. These values are essentially the same for both annealed and unannealed devices. The fmax’s of unannealed devices were measured to be 242 and 302 GHz for E- and D-HEMTs, respectively. The fmax values were 10% lower for annealed devices at 220 and 270 GHz. The results obtained here demonstrated the highest fT’s ever achieved for E/D-HEMTs integrated on a common device platform. 4. Conclusion

Drain-source voltage (V)

Fig. 4. DC transfer characteristics of D-HEMTs (a) and E-HEMTs (b). Dotted lines for devices before gate annealing process and solid lines for the devices after gate annealing process.

Enhancement- and depletion-mode HEMTs with 0.15 lm-gates were fabricated on common InP substrates. Both devices employed buried-Pt gate technology to

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J.H. Jang et al. / Solid-State Electronics 50 (2006) 758–762

achieve positive VTH for E-HEMTs and zero Vgp for DHEMTs. High current driving capabilities greater than 600 mA/mm and 800 mA/mm were achieved for EHEMTs and D-HEMTs, respectively. Both D- and EHEMTs exhibited transconductance values higher than 1 S/mm and unity current cut-off frequencies, fT’s greater than 180 GHz. Acknowledgement This work was supported by Comprehensive Materials and Components Technology Support Program supervised by KMAC and ITRC program supervised by IITA (IITA2005-C1090-0502-0029). References [1] Yamashita Y, Endoh A, Shinohara K, Hikosaka K, Matsui T, Hiyamizu S, et al. Pseudomorphic In0.52Al0.48As/In0.7Ga0.3As HEMTs with an ultrahigh fT of 562 GHz. IEEE Electron Device Lett 2002;23:573–5. [2] Grundbacher R, Lai R, Nishimoto M, Chin TP, Chen YC, Barsky M, et al. Pseudomorphic InP HEMTs with dry-etched source visas having 190 mW output power and 40% PAE at V-band. IEEE Electron Device Lett 1999;20:517–9. [3] Tang, Liu SMJ, Chao PC, Kong WMT, Hwang KC, Nichols K, et al. Design and fabrication of a wideband 56- to 63-GHz monolithic power amplifier with very high power-added efficiency. IEEE Solid-State Circuits 2000;35:1298–306. [4] Kong WMT, Wang SC, Chao PC, Tu DW, Hwang KC, Tang OSA, et al. Very high efficiency V-band power InP HEMT MMICs. IEEE Electron Device Lett 2000;21:521–3.

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