Designing efficient QCA logical circuits with power dissipation analysis

Microelectronics Journal 46 (2015) 462–471

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Designing efficient QCA logical circuits with power dissipation analysis Shadi Sheikhfaal, Shaahin Angizi n, Soheil Sarmadi, Mohammad Hossein Moaiyeri, Samira Sayedsalehi School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran 1953833511, Iran

art ic l e i nf o

a b s t r a c t

Article history: Received 12 November 2014 Received in revised form 20 February 2015 Accepted 23 March 2015

Recently reported QCA logical and arithmetic designs have completely disregarded the power consumption issue of the circuits. In this paper, a comprehensive power dissipation analysis as well as a structural analysis over the previously published five-input majority gates is performed. During our experimentations, we found that these designs suffer from high power consumption and also structural weaknesses. Therefore, a new ultra-low power and low-complexity five-input majority gate is proposed. For examining our presented design in large array of QCA structures even parity generators, as instances of logical circuits with different lengths up to 32 bits are presented. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from implementation requirements and power consumption aspects. QCADesigner tool is used to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool. & 2015 Elsevier Ltd. All rights reserved.

Keywords: Nanoelectronics Quantum-dot cellular automata Five-input majority gate Power analysis Dissipated power Even parity generator

1. Introduction Shrinkage in feature size of CMOS circuits has become a controversial issue for designers to implement a circuit with low power consumption besides considerable decreasing in the size. Therefore, the necessity for an alternative technology which could offer revolutionary approach for working at Nano-scale was seemed more vital than ever [1]. Accordingly, Quantum-dot Cellular Automata (QCA) is presented which can perform with ultra-low power despite its high performance. The basic unit in this technology is a cell which consists of four dots and two excess electrons and all the logic gates and circuits can be made based on it. The computation in an array of QCA cells is performed through Coulombic interaction [2]. According to the considerable advances in semiconductor materials used in a existing CMOS fabrication process, semiconductor implementation of QCA is so promising. The type of used technology in this paper is semiconductor QCA which is composed of four quantum-dots manufactured by semiconductive materials [3]. Since there is no electrical current in QCA computations, the power consumption is considerably lower than conventional CMOS circuits. Nevertheless, it is necessary to characterize all aspects of a new technology, so several studies have been performed in the area of QCA power [4–8]. One of the most n

Corresponding author. Tel.: þ 98 9127238731. E-mail addresses: [email protected] (S. Sheikhfaal), [email protected] (S. Angizi), [email protected] (S. Sarmadi), [email protected] (S. Sayedsalehi). http://dx.doi.org/10.1016/j.mejo.2015.03.016 0026-2692/& 2015 Elsevier Ltd. All rights reserved.

accurate power dissipation models has been proposed by Timler and Lent [4] and an upper bound power dissipation for QCA circuits is estimated by Srivastava et al. [6] based on it. Furthermore, in recent years, lots of investigations have been launched in order to design various digital circuits based on this technology; new designs for five-input majority gate [10–13,27,28], structures for one-bit full-adder cell [10,11,21,22], designs for flip-flops and memory cells [14,15,23], QCA complex gate designs [29,32] and also studies on reversible circuits [24,25] have been presented. There are three main obstacles for exploiting complete potential of QCA circuits as is thoroughly discussed in [36]. The first and the most important problem is the realization of QCA circuits capable of processing at room temperature, however Nanomagnet based QCA circuits can be realized in mentioned temperature but with higher dimensions [37]. The second issue is the means by which the output or input cells could be fixed and measured. The third issue is circuit tolerance to possible fabrication faults. The mentioned obstacles motivated further studies in future. The main aim of our work is to analyze the power dissipation for proposing efficient QCA logical circuits. In the first step, a comprehensible study over power and structural subjects of the previously proposed five-input majority gates is made. To modify the structural weaknesses and reduce the power dissipation in the mentioned circuits, an ultra-low power and optimal five-input majority gate is proposed. In the second step, new even parity generators (up to 32-bit) as the instances of logical circuits are designed by employing the proposed gate. A detailed analysis on the power consumption of the presented logical circuits and the best reported ones in literatures is performed. Finally, considering

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the proposed designs a comparison between power consumption in QCA-18 nm and MOSFET-16 nm technologies is performed. The rest of this paper is organized as follow: a review on QCA elementary concepts, structures and power dissipation models is presented in Section 2. A novel design for five-input majority gate and its simulation in addition to structural and power analysis of the previous designs are addressed in Section 3. In Section 4, based on a new implementation of two-input XOR gate, the even parity generators with different lengths up to 32 bits are presented and simulated. Section 5 inspects power consumption and complexity of the proposed circuits and compares them to the counterparts, finally Section 6 concludes the paper.

463

the first QCA layout presented in [10] which is shown in Fig. 3(a), it is impossible to access two of the input cells (B and C) in a single layer. The output cell is surrounded by the other cells in the second design presented in [11], as shown in Fig. 3(b). Moreover, designers of two last structures (Fig. 3(c) presented in [12] and Fig. 3(d) presented in [13]) tried to overcome these drawbacks by proposing a novel device. Most of the presented designs are applied as a basic component in one-bit full-adder architecture. According to [11], a logical relation could be derived between a five-input majority gate, weight of input cells and their impacts on

2. QCA preliminaries A QCA cell is composed of four quantum-dots and two excess electrons situated in a square. According to the existing Coulombic interaction between the electronic charges, they can occupy diagonal antipodal sites through tunneling junctions, quantummechanically. Therefore, a single QCA cell can accept two completely polarized states called cell polarization (P ¼ þ1, P ¼  1) [1]. As shown in Fig. 1(a), by encoding these two ground states to Binary digits, first digital concept is defined. In a deeper look, the cell polarization can be exhibited as the following equation [2]: P¼

ðρ1 þ ρ3 Þ  ðρ2 þ ρ4 Þ ρ1 þ ρ2 þ ρ3 þ ρ4

ð1Þ

Fig. 1. (a) Two-basis polarization of a QCA cell and (b) binary wire.

where ρi represents the electronic charge in dot i. Since the tunneling energies are considerably less than Coulombic energies, the cell will be well polarized. If the tunneling energies take an equivalent value to Columbic energies, the QCA cell will lose its polarization and called unpolarized [2,4]. A QCA wire is constructed by placing QCA cells side-by-side as found in Fig. 1(b). 2.1. Elementary structures The fundamental logic gates available in QCA circuits are inverter and three-input majority gate as shown in Fig. 2 [2]. Inverting operation in QCA circuits is performed by diagonal arrangement of two cells. Moreover, by assuming A, B and C as three inputs of a majority gate, output function executes based on the following equation: MGðA; B; CÞ ¼ AB þ AC þ BC

Fig. 2. QCA fundamental logic gates: (a) inverter and (b) three-input majority gate.

ð2Þ

2.2. Review on the previous five-input majority gates According to the considerable area optimization in QCA implementation of the three-input majority gate as compared to siliconbased transistors, the researchers have also tried to theorize an optimal and minimized structure for five-input majority gate. The projected idea behind suggestion of such gates in the literatures is implementation of well-optimized full adder circuits which has been limited to three-input majority gates for two decades. Regardless of the five-input majority gate, the best proposed architecture for a full adder cell consumes five gates (3 threeinput majority gate in addition to 2 inverters). However the fiveinput majority gate-based designs in [10,11] are composed of only three gates. Regarding the same synchronization approach of three and five-input majority gates [14,22], the five-input majority gatebased structures are simpler and faster than conventional ones. As a new application, the authors of [33] have implemented a novel modular decoder using this gate. As yet, several implementations for five-input majority gate have been reported which perform based on the Eq. (3) [10–13]. In

Fig. 3. Five-input majority gates: (a) design in [10], (b) design in [11], (c) design in [12] and (d) design in [13].

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Fig. 6. The power flows in a pair of neighbor cells.

Fig. 4. Fault-tolerant five-input majority gates: (a) design in [27] and (b) design in [28].

Fig. 7. The proposed five-input majority gate (PM5): (a) schematic diagram (b) QCA implementation.

Table 1 Coherence vector parameters. Fig. 5. QCA clocking phases within clock zones.

the voter cell. As instances for Fig. 3(a), (b) and (c), three relations A þ2B þ2C þD þE, A þ 2Bþ 2Cþ2D þ2E and A þ Bþ C þD þE were mentioned, respectively. Fault-tolerant design in Quantum-dot cellular automata is an essential subject for representation of suitable functionality of the circuits. Fig. 4 illustrates two fault-tolerant designs of five-input majority gates proposed in the literatures in order to tolerate the whole system against three chief categories of faults in implementation process of QCA logics [27,28]. MGðA; B; C; D; EÞ ¼ ABC þ ABD þ ABE þ ACD þ ACE þ ADE þ BCD þ BCE þ BDE þ CDE

ð3Þ

2.3. Clocking concepts The adiabatic switching is firstly proposed by Lent et al. to remedy the metastable state which was one of the disadvantages of abrupt switching. In the adiabatic switching, QCA system will always remain in instantaneous ground state. This kind of switching is achieved by an underlying clocking circuit which needs only the slow discharging and charging of a capacitor [2,4,16]. As it is shown in Fig. 5, QCA clocking concept can be realized with tracing of four phases (Switch, Hold, Release and Relax) over the four clock zones [17]. Considering a 90-degree out-of-phase between

Parameter

Value

Cell size Dot diameter Center-to-center distance Temperature Relaxation time Time step Total simulation time Clock high Clock low Clock shift Clock amplitude factor Radius of effect Relative permittivity Layer separation

18n18 nm2 5 nm 20 nm 2.000000 K 4.1356675e  14 s 1.000000e  016 s 7.000000e  011 s 9.800000e  022 J 3.800000e  023 J 0.000000e þ000 2.000000 80.000000 nm 12.900000 11.500000 nm

successive phases, a QCA system is synchronized. In the switch phase, inter-dot barriers are steadily raised and the electrons can transfer between dots. By taking a certain polarization value during the hold phase, when the inter-dot barriers are completely high, the cell can only bias the neighboring cells. In the release and relax phases, the cell will lose its polarization [18]. 2.4. QCA power dissipation model First Quantum-dot cellular automata power formulism is developed by Timler and Lent [4]. The total energy and power of

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465

Fig. 8. Simulation result of PM5.

Table 2 Structural analysis result. Proposed circuits

Consumed Single layer Single layer accessibility to the accessibility to the cell count output cell input cells

Area occupation (nm2)

Fault tolerant design in [27] Fault tolerant design in [28] Design in [10] Design in [11] Design in [12] Design in [13] PM5

Yes

34444

Yes

42

a QCA cell can be measured using a Hamiltonian matrix. The Hamiltonian for an array of QCA cells using Hartree–Fock approximation [9] and by considering the Coulombic interaction between them by a mean-field approach is exposed as [4,5] 3 2 3 2  Ek P  Ek γ γ i C i f i;j 2 2 ðC j  1 þ C j þ 1 Þ 4 5 4 5 ¼ H¼ Ek P Ek γ γ i C i f i;j 2 2 ðC j  1 þ C j þ 1 Þ ð4Þ

No

No

51

38804

No

Yes

10

7644

Yes

No

10

4524

Yes

Yes

18

16284

Yes

Yes

13

9604

Yes

Yes

11

9604

where Ci is the polarization of the ith juxtaposed cell and fi,j is the geometrical factor specifying electrostatic interaction between cells (i and j) due to the geometrical distance. In the case of equally spaced neighboring cells, factor fi,j is absorbed into the Kink energy definition (Ek). This energy is associated with the energy cost of two QCA cells (i and j) having opposite polarizations and can be computed as [13] Ei;j ¼

4 4 X X

q q  i;n j;m  4Πε0 εr n ¼ 1 m ¼ 1 r i;n  r j;m  1

ð5Þ

The expectation value for QCA cell energy at each clock cycle is

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calculated as ℏ!! ð6Þ E ¼ 〈H〉 ¼ : Γ : λ 2 ! Here Γ is the energy environment vector of the cell! including its neighbors effects, ℏ is reduced Planck constant and λ represents Coherence vector. The Hamiltonian vector corresponding to Hamiltonian is given by !

Γ¼

 1  2γ ; 0; Ek ðC j  1 þ C j þ 1 Þ ; ℏ

ð7Þ

50 45 40 35 30 25 20 15 10 5 0 Design in Design in Design in Design in [10] [11] [12] [13]

Fault tolerant design in [27]

Fault tolerant design in [28]

PM5

Proposed circuits 0.5 Ek 1 Ek 1.5 Ek Fig. 10. The average leakage energy dissipation of the presented five-input majority gates under different tunneling energy levels (T ¼ 2.0 K, unit of energy consumption: eV).

Avg. switching energy dissipation (mev)

whereðC j  1 þC j þ 1 Þis the sum of neighboring polarizations. As illustrated in Fig. 6, the power flow of a QCA cell located in a binary wire is classified into the four main signal flows. As demonstrated in [4,6], the horizontal signal powers are equal, where Pin is the achieved signal power from the left neighboring cell and Pout is the released signal power to the right side cell. As noted earlier, during the switch phase, inter-dot barriers are gradually raised leading to transfer of a considerable amount of energy to the cell (Pclock) and in the release phase, these barriers are lowered, so the energy is returned to the clocking circuit.

Therefore, there is a negligible power dissipation in a clocking circuit called Pdiss [5–7].

Avg. leakage energy dissipation (mev)

466

120 100 80 60 40 20 0 Design in Design in Design in Design in [10] [11] [12] [13]

Fault Fault tolerant tolerant design in design in [27] [28]

PM5

Proposed circuits 0.5 Ek

1 Ek

1.5 Ek

Total energy consumption (mev)

Fig. 11. The average switching energy dissipation of the presented five-input majority gates under different tunneling energy levels (T ¼ 2.0 K, unit of energy consumption: eV).

160 140 120 100 80 60 40 20 0 Design Design Design Design Fault Fault PM5 in [10] in [11] in [12] in [13] tolerant tolerant design in design in [27] [28] Proposed circuits

Fig. 9. The power dissipation maps for five-input majority gates at 2 K temperature with 0.5 Ek (a) design in [10], (b) design in [11], (c) design in [12], (d) design in [13] and (e) PM5.

0.5 Ek

1 Ek

1.5 Ek els 1 Ek lev y 0.5 Ek g er ) en K ng 2.0 i l e = n n (T Tu

1.5 Ek

Fig. 12. Total energy consumption of the presented five-input majority gates under different tunneling energy levels (T ¼ 2.0 K, unit of energy consumption: eV).

Table 3 Power analysis results. Avg. leakage energy dissipation (meV) Proposed circuits Design in [10] Design in [11] Design in [12] Design in [13] Fault tolerant design in [27] Fault tolerant design in [28] PM5

0.5 Ek 1.28 1.35 3.44 3.38 8.2 6.33 2.99

1 Ek 4.14 4.25 10.67 8.95 26.14 17.34 7.73

1.5 Ek 7.69 7.8 19.52 15.03 49.15 38.22 12.35

Avg. switching energy dissipation (meV)

Total energy consumption (meV)

0.5 Ek 11.53 10.94 32.66 9.23 117.57 92.44 3.69

0.5 Ek 12.81 12.29 36.1 12.61 125.77 98.77 6.68

1 Ek 10.37 9.84 29.89 7.7 110.66 86.45 2.77

1.5 Ek 9.16 8.7 27.01 6.41 102.67 76.44 2.15

1 Ek 14.51 14.09 40.56 16.65 136.8 103.79 10.5

1.5 Ek 16.85 16.5 46.53 21.44 151.82 114.66 14.5

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Table 4 Power consumption comparison for the five-input majority gate designs in QCA and MOSFET technologies. Technology

Leakage power dissipation (W)

Total power consumption (W)

QCA-18 nm with 0.5 Ek MOSFET-16 nm

4.790n10  10

10.702n10  10

7.67701n10  7

1.0536n10  6

Fig. 14. QCA implementation of 4-bit even parity generator circuit using the proposed module in Fig. 13(b).

Fig. 13. New two-input XOR gate: (a) schematic diagram and (b) QCA implementation.

The instantaneous total power equation for a single QCA cell can be calculated as 2 3 2 !3 ! dE ℏ4d Γ !5 ℏ4! d λ 5 ¼ :λ þ Γ: ð8Þ Pt ¼ ¼ P1 þ P2 dt 2 dt 2 dt In Eq. (8), the term P1 includes two main components: first, the power gain achieved from difference of the input and output signal powers (Pin Pout) and second, the transferred clocking power to the cell (Pclock) and the term P2 represents dissipated power (Pdiss) [6]. Based on [4], the energy dissipation during one clock cycle T cc ¼ ½ T; T can be represented in terms of Hamiltonian and Coherence vectors as 0 1 ! !   Z Z T ! dΓ ℏ T !dλ ℏ@ ! ! T ð9Þ Γ : dt ¼ Γ:λ  λ : dt A Ediss ¼ 2 T 2 dt dt T T It is noteworthy that maximum energy dissipation will occur ! when the changing rate of Γ is maximum. So, by representing ! ! ! ! Γ þ and Γ  as Γ ð þ T Þand Γ ð  T Þ, the upper bound power dissipation model presented in [6] is given as P diss ¼

Ediss ℏ ! 〈 Γþ T cc 2T cc 2 0 ! 1 0 ! 13     ! ! ℏ Γ ℏ Γ 6 Γþ B  þ C Γ  B   C7 4  !  tanh@ A þ !  tanh@ A5     kB T kB T Γ þ  Γ  

ð10Þ

Here kB represents the Boltzmann constant and T is the temperature. In an array of similar QCA cells, the total dissipated power can be calculated by adding the dissipated power of all cells since the presented model for each QCA cell is identical [5]. By applying the mentioned concepts, the author of [8] have proposed a power dissipation model for QCA circuits with separating

the total power into two main components which called “leakage” and “switching”. Power losses during clock changes (from low to high or high to low) lead to leakage power and power loss due to the switching period leads to switching power. Based on this model a power estimation tool called QCAPro is developed. This tool evaluates the maximum, minimum and average power dissipation occurred in a QCA structure under non-adiabatic switching. Moreover, it can be used for verifying circuit functionality according to the Bayesian network analysis [8].

3. New QCA based five-input majority gate 3.1. Structural analysis Our proposed design for five-input majority gate called PM5 is composed of only 11 QCA cells as shown in Fig. 7. It is worth pointing out that all the input cells are implemented in a single layer with no need to additional layers to access. In addition, the input and output cells are not surrounded by the other cells. As the result, drawbacks of the previous designs are modified. To authenticate the proper functionality of PM5, Coherence vector engine of QCADesigner tool version 2.0.3 [26] is used with the options summarized in Table 1. It is clear from Fig. 8 that the expected highly polarized output waveform is achieved. In order to check the correct functioning and inspect the sensitivity of our proposed gate to minor displacements, 2 nm single-fault cell displacement and cell misalignment presented in [13,27] are applied to the input and output cells and similar precise output is achieved. A structural evaluation between all proposed five-input majority gates in the literatures and PM5 is prepared by considering various costs such as single layer accessibility to the input and output cells, cell count and area occupation, as shown in Table 2. However the presented designs in [10] and [11] consume less hardware requirements in comparison to other designs, but as mentioned earlier, the single layer accessibility is neglected for some of their cells. Only three structures presented in [12,13,27] take advantages of full accessibility to the input and output cells. Our proposed five-input majority gate (PM5) also supports the full accessibility same as these three designs with a significant improvements in terms of consumed cell and area occupation. It should be mentioned that based on the presented method in [11], our proposed gate can be considered with a similar relation as Fig. 3(c) with equivalent input cell's impacts on the voter cell.

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Fig. 15. QCA implementation of 32-bit even parity generator circuit.

Fig. 16. Simulation results: (a) the proposed two-input XOR gate and (b) the 4-bit parity generator circuit. (For interpretation of the references to color in this figure, the reader is referred to the web version of this article.)

3.2. Power analysis As noted before, in order to evaluate consumed power of the proposed design, we use QCAPro [8] as an acceptable power valuator tool. We examine our design as well as previous structures under three different tunneling energy levels (0.5 Ek, 1 Ek and 1.5 Ek) at 2 K temperature. The power dissipation maps of presented five-input majority gates in [10–13] with 0.5 Ek are shown in Fig. 9. It is clear

that high power dissipating cells are indicated using thermal hotspots with darker colors. Table 3 shows the total dissipated energy divided into leakage and switching energies for the five-input majority gates. Evidently in Fig. 9, the middle cells (or voter cells) in proposed designs in [10–13] have dissipated more power in contrast to other cells. As a result, the adjusted position of the input cells as the surrounding cells and their effects on the voter cell could be considered as one of the most significant factors in increasing power dissipations. Hence,

Table 5 Comparison result of the single layer two-input XOR gate designs. Circuit

Area (mm2)

Cell count

Latency (Clock cycle)

Cross-over type

XOR 2 [19] XOR 2 [20] XOR 2 [21] Proposed

0.09

60

1.5

Coplanar (rotated cells)

0.08

54

1.5

Coplanar (rotated cells)

0.06

67

1.25

0.02

32

1

Coplanar (clocking based) Not Required

No. of bits

No. of cells

Circuit Area in (mm2)

No. of clock cycles

Design in [19]

4 8 16 32 4 8 16 32 4 8 16 32 4

187 456 1024 2220 168 408 912 1968 188 369 847 1862 98

0.32 0.92 2.41 5.96 0.28 0.8 2.09 5.16 0.2 0.49 1.46 3.58 0.11

2.75 4 5.25 6.5 2.75 4 5.25 6.5 2.25 2.25 3.25 4.25 2

8 16 32

241 537 1167

0.37 1.04 2.67

3 4 5

Proposed design

4000 3500 3000 2500 2000 1500 1000 500 0

4-bit 8-bit 16-bit 32-bit Design in [19]

Design in [20]

Design in [21]

Proposed

Fig. 17. Power dissipation comparison between different-size parity generator circuits.

Circuits

Design in [21]

469

Even parity generators

Table 6 Comparison result of even parity generator designs.

Design in [20]

Power dissipation (ev)

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regarding the especial configuration of input cells in Fig. 9(e), we have achieved a reduced consistent power dissipation. This configuration imposes less possible energy to voter cell in comparison to the previously reported ones. Fig. 10 illustrates the average leakage energies of the designs over all input vector pairs. Based on this figure, PM5 has a superiority over the presented designs in [12,13,27,28], while the design in [10] shows least leakage energy. However, as is indicated in Fig. 11, PM5 has least switching energy in comparison to the other designs in [10–13,27,28] when the tunneling energy level has changed. The comprehensive comparison of total consumed energy in the seven structures is provided in Fig. 12 by calculating sum of the average leakage and switching energies for different tunneling energy levels. It is apparent that the proposed design (PM5) shows a considerable energyefficiency compared to others. Regarding these results PM5 represents a low-power five-input majority gate which enables designers to implement low-power and large scale QCA circuits with minimum consumed cells. In addition, a power consumption comparison for the five-input majority gate designs in QCA-18 nm and MOSFET-16 nm technologies is presented in Table 4. The efficient MOSFET-based structure of the 5input majority circuit [35] is adopted for comparison. The circuit is simulated using HSPICE and the 16 nm CMOS technology with high-K gate oxide, metal gate and strained-Si [34] at 0.7 V supply voltage and 1 GHz frequency and the total power consumption and the leakage power dissipation are measured.

receiver unit. Basic element of a parity generator circuit is an XOR gate, so in this section, we propose a new QCA structure for this gate based on PM5. This gate is suitable for cascading in the large scales. An efficient two-input XOR with minimum number of gates can be designed based on the schematic diagram shown in Fig. 13(a). The logical equation produced by this circuit can be written as XOR2 ¼ PM5ðA; B; 0; MGðA; B; 0Þ; MGðA; B; 0ÞÞ ¼ AB þ AB

ð11Þ

This structure is composed of only three main gates, an inverter, a three-input majority gate and a five-input majority gate. Considering the synchronization concepts, the proposed QCA layout in Fig. 13(b) has a symmetric structure which enables accessing the input and output cells in a single layer. As is clear in this figure, the ultra-compact and single layer circuit consumes one clock cycle to calculate the precious output. It is worth mentioning that the output cell's clock is adjusted in Clock 3 (forth clock zone) to meet the minimum wire length presented in [18]. With the aim of implementing different length even parity generator circuits (up to 32-bit), we need to use the presented module in Fig. 13(b). According to the lack of space, only the QCA layouts of 4-bit and 32-bit parity generator circuits are shown in Fig. 14 and Fig. 15, respectively. The produced bit from Out-labeled cell in discussed figures is considered as parity bit. The correct functionality of our novel structures is studied and verified through QCADesigner tool ver. 2.0.3 [26] with the similar parameters shown in Table 1. The simulation results of the proposed two-input XOR gate are shown in Fig. 16 (a). Based on this figure, the first meaningful output waveform displayed by black arrow is represented after 1 clock cycle (at clock 3). The simulation result of 4-bit parity generator circuit is shown in Fig. 16(b) using the bus representation. The red arrows show the output's binary value corresponding to the input value demonstrated as decimal. In addition, the first valid output waveform is shown using black arrow after 2 clock cycles. We have checked the functioning of the proposed even parity generator circuits under cell's displacement fault in the sensitive zones (which is shown with black squares in Fig. 14). It is worth pointing out that our designs tolerate 3 nm vertically displacements that could be an effective aspect in a cell placement process.

5. Discussions and comparison results 4. Proposed approach for designing even parity generator circuits In order to detect errors in digital data transmissions, parity bits are added to data in the sender unit and are checked in the

A detailed comparison between our proposed two-input XOR gate and previous single layer ones is performed in Table 5 with different aspects. Clearly, our design outperforms the proposed designs in [19–21] in area, cell amount and latency point of views. We have achieved 40% improvement in cell count as compared to

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Table 7 Comparison of delay and power consumption parameters for XOR-based structures in QCA and MOSFET technologies.

2 4 8 16 32

Delay (n10  12 s)

Total power consumption (n10  6 W)

Leakage power consumption (n10  9 W)

QCA-18 nm (1 THz)

MOSFET-16 nm

QCA-18 nm

MOSFET-16 nm

QCA-18 nm

MOSFET-16 nm

1.00 2.00 3.00 4.00 5.00

14.72 50.01 121.3 263.3 492.4

0.0083 0.0260 0.0701 0.1593 0.3716

0.147 0.515 1.311 3.147 7.528

1.6502 5.6556 13.3621 30.1689 60.0015

32.511 97.556 227.65 487.847 1008.24

the best reported design in [20] and 66% optimization in area occupation in comparison to the best one in [21]. In addition, 0.25 clock cycle reduction in latency is achieved as compared to the design in [21]. Comparison results between recently reported even parity generator circuits and our designs are provided in Table 6. Evidently, the proposed circuits with different number of bits have a significant superiority over prior designs in terms of cell count and occupation area. As an instance, the highly integrated well-optimized 32-bit parity generator circuit in Fig. 15 is composed of 1167 cells with 695 cells optimization in comparison to the best reported design in [21]. It is worth to mention that this design takes advantage of saving 1.19 mm2 area upon the presented one in [21]. To show the power efficiency of new XOR-based designs besides their beneficial structures, an extensive power analysis for different sizes even parity generator circuits (4-,8-,16- and 32-bit) is performed. As is shown in Fig. 17, our proposed architectures have least energy dissipation value in diverse sizes as compared to the circuits in [19– 21]. In addition a comparison of delay and power consumption parameters in QCA-18 nm and MOSFET-16 nm technologies is performed for XOR-based structures. The low-power and highperformance 8-transistor CMOS 2-input XOR circuit is adopted for the comparison [31]. The circuits are simulated using the 16 nm CMOS technology with high-K gate oxide, metal gate and strained-Si [34] at 0.7 V supply voltage and 1 GHz frequency and the worst-case delay, the total power consumption and the leakage power dissipation are reported in Table 7. Clearly, the proposed QCA-based architectures outperform MOSFET-based ones in circuit delay and power dissipation aspects. It is noteworthy that based on [18], the QCA circuits clock rate is in the range of 1–2 THz. Since there is no frequency adjustment in QCA simulation engines, Table 7 includes typical range of QCA clock rate. Accordingly the delay parameter can be estimated at these frequencies as is mentioned in [30]. The power consumption for QCA-18 nm and MOSFET-16 nm are estimated using QCAPro tool and HSPICE circuit simulator [34], respectively We have also performed an analysis over temperature fluctuations and its result on output polarization of proposed two-input XOR gate. According to Fig. 18, we can see that the output polarization is extremely slumped after 15 K. In addition the scalability of proposed designs is checked using QCADesigner tool by altering the scale parameter by 1, 0.5 and 0.25 and similar accurate results are achieved.

6. Conclusion In this paper for the first time, an extensive study on structural and power issues of the previously reported five-input majority gates was performed. The average leakage and switching power dissipations in these structures were investigated using an accurate QCA power dissipation model. Considering the drawbacks, a new low-complexity and low-power circuit for five-input majority gate was proposed and applied as a main gate into an efficient

Output polarization

# of bits

1.00E+00 9.00E- 01 8.00E- 01 7.00E- 01 6.00E- 01 5.00E- 01 4.00E- 01 3.00E- 01 2.00E- 01 1.00E- 01 0.00E+00

0

5

10

15

20

25

30

35

Temprature (k) Fig. 18. Correlation of temperature fluctuation and output polarization for 2-input XOR gate.

two-input XOR gate. In the next step, different length parity generator circuits up to 32 bits were designed and implemented using the proposed XOR gate. A detailed power consumption comparison was also performed between our proposed circuits and prior ones. The results confirmed the dominance of our designs over state-of-the-art designs in terms of power consumption, consumed cell count, area occupation and circuit delay.

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