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Towards ultra-efficient QCA reversible circuits
Accepted Manuscript
Towards Ultra-efficient QCA Reversible Circuits Amir Mokhtar Chabi , Arman Roohi , Hossein Khademolhosseini , Shadi Sheikhfaal , Shaahin Angizi , Keivan Navi , Ronald F. DeMara PII: DOI: Reference:
S0141-9331(16)30243-5 10.1016/j.micpro.2016.09.015 MICPRO 2484
To appear in:
Microprocessors and Microsystems
Received date: Revised date: Accepted date:
24 December 2015 22 July 2016 30 September 2016
Please cite this article as: Amir Mokhtar Chabi , Arman Roohi , Hossein Khademolhosseini , Shadi Sheikhfaal , Shaahin Angizi , Keivan Navi , Ronald F. DeMara , Towards Ultra-efficient QCA Reversible Circuits, Microprocessors and Microsystems (2016), doi: 10.1016/j.micpro.2016.09.015
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Towards Ultra-efficient QCA Reversible Circuits Amir Mokhtar Chabia, Arman Roohib, Hossein Khademolhosseinic, Shadi Sheikhfaald, Shaahin Angizid,*, Keivan Navid, Ronald F. DeMarab a
Department of Computer, Faculty of Engineering, Persian Gulf University, Bushehr, Iran Department of Electrical Engineering and Computer Science, University of Central Florida, Orlando, USA c Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran d School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran b
Abstract—Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future
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computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most costefficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.
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Keywords—Nanoelectronic; Combinational circuits; Sequential circuits; XOR gate; Reversible logic; Quantum cellular automata.
I. INTRODUCTION
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Emerging nanotechnologies have been developed to achieve a performance that is not accessible by CMOS due to its serious hurdle in reduction of feature sizes. Quantum- dot Cellular Automata (QCA) is one of these promising alternatives to transistor-based technologies in the near future [1]. Outstanding properties including extremely high density and fast operation speed at tera-hertz frequency range together with ultra-low power dissipation are the potential offered by this method of computation [2],[3],[4]. Since QCA is radically different from today‘s CMOS technology, different and clearly new design approaches are required.
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To date lots of attempts have been made for presenting efficient QCA architectures [5],[7],[11-14],[22]. Reversible computation has been proposed for its application in energy lossless computing. Landauer principle states that the erasure of one bit of information in computing, dissipates at least KBTln2 Joules, where KB is Boltzmann‘s constant and T is the temperature [2],[6],[26]; however, Bennett shows this can be avoided by means of reversible gates and hence, zero energy dissipation is possible only if all the utilized gates are reversible [3]. Reversible gates are building blocks of reversible logic. Reversible gates provide unique mapping between the input vectors and the output ones, thus the number of inputs must be equal to that of outputs [7],[16],[20].
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In this paper, a new two-input XOR gate and also a new approach to implement 2:1 multiplexer are presented. In addition, an efficient universal reversible gate based on the proposed XOR gate is designed. Considering this universal gate as the main building block, numerous QCA reversible benchmarks are implemented.
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The paper is organized as follows: Section II presents the background of QCA and some related works. Design and layout of the novel XOR gate is presented in Section III. In Section IV, design of an efficient reversible gate in QCA is provided. Section V describes the simulation parameters used to verify the designs along with the simulation results. Section VI addresses the proposed QCA latches and sequential circuits. Conclusions are given in Section VII. II. BACKGROUND
A. The QCA Basics A QCA cell consists of four quantum dots which are located in the corners of a square structure. A cell contains two extra free electrons which can tunnel between the dots within the cell. Through Columbic effects, two possible polarizations (the locations of the electrons in the cell) can be shaped. These two potential states can be considered as the binary states 1 and 0. A QCA cell is shown in Fig. 1. Two fundamental building blocks of each QCA circuit are the inverter and the majority gate. Fig. 2 shows the basic QCA devices. A straightforward and excellent tutorial can be found in [1], [23].
* Corresponding Author Email Addresses: [email protected] (A.M. Chabi), [email protected] (A. Roohi), [email protected] (H. Khademolhosseini, [email protected] (S. Sheikhfaal), [email protected] (S. Angizi), [email protected] (K.Navi), [email protected] (R. F. DeMara)
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Although the 3-input majority gate and the inverter gates were the fundamental elements in various preceding works, the evaluations have shown that the majority voter is not efficiently used during technology mapping. In order to overcome this drawback, various kinds of gates have been introduced [4],[22]. A four-phase clocking scheme for QCA (also known as Landauer clocking) generally used in QCA design has been proposed in [24], and the present work is also based on this clocking scheme. The consecutive clocking zones are indicated in our layouts by the different colors of the cells as shown in Fig. 3.
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Fig. 1. QCA Cell.
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Fig. 2. Basic QCA devices, (a) Inverter. (b) Majority Gate.
Fig. 3. The four clocking zones in a QCA wire corresponding to the four clock signals.
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B. Related Works Concurrently testable designs for the latches (D latch, T latch, JK latch, and SR latch) are presented in [16]. The Fredkin gate is used for implementing reversible latches in this paper. The use of a new reversible logic gate (CQCA) to design concurrently testable circuits in QCA was done in [5]. It is shown that the CQCA gate performs better than the original Fredkin gate in terms of area and speed. A new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) was presented in [6]. Despite the similar properties of the MX-cqca and the Fredkin gate as 2:1 multiplexers, the MX-cqca is not reversible. Two new reversible gates (denoted as QCA1 and QCA2) have been proposed in [7]. These reversible gates have been compared to Fredkin and Toffoli gates [8] and a comprehensive analysis were made through the test domain. III. THE NOVEL XOR GATE
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A diverse form of XOR layout has been offered so far [11],[12] and in most of the designs 3-input majority gate has been utilized. XOR gate is an essential element to build the Sum output in adder designs and moreover, due to the great importance of XOR gate in digital logic designs, several XOR-based circuits have been proposed so far. In [9], a binary tree made of XOR gates as a parity checker and also a general model for assessing power consumption under the two clocking methods (Landauer and Bennett) for QCA operation have been presented.
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Fig. 4(a) demonstrates the novel 2-input XOR gate. Contrary to previously reported designs for implementation of 2-input XOR, our proposed one uses explicit interactions between QCA cells to produce the expected result and it is not majority based. Hence, this highly integrated QCA layout can significantly reduce the cell count, area and delay. Table 1 displays the comparison between the proposed XOR gate and the former ones. As it is apparent from the table, our proposed XOR is more competitive in terms of cell count (complexity) and delay. It is worth mentioning that in constructing large circuits using the smaller designs, complexity and delay of the small building blocks are of much importance. The proposed structure for 2-input XOR gate (with 0.5 clock cycle delay) can be effectively utilized as a building block in designing multi-input XOR gates. A cost-effective 3-input XOR gate can be designed using only 2 cascaded 2-input XOR gates with 0.75 clock cycle. In the same way, an ultra-high speed 4-input XOR can be effectively designed using 3 cascaded gates working in 1 clock cycle as shown in Fig. 4(b). Without loss of generality, the delay of an n-input XOR gate based on our design can be written as: T XORN
n T XOR 2 ,n 2 2
(1) IV. DESIGN OF AN EFFICIENT REVERSIBLE GATE IN QCA
In this section, a new approach to implement a 2:1 multiplexer based on the novel XOR gate is presented. Moreover, a potent universal reversible gate using the proposed gates is designed. As mentioned previously, a logic gate (function) is
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called reversible if the mapping of its inputs to outputs is bijective (one-to-one correspondence) and hence, the number of inputs is equal to the number of outputs. The prevailing reversible gates are costly in QCA implementation. This motivated us to propose a novel reversible gate particularly suited for QCA implementation.
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XOR 2 [11] XOR 2 [12] XOR 2 [13]
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5
0.08
3 4 -
Cross-over Type Coplanar (rotated cells) Coplanar (rotated cells) Coplanar (clocking based)
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1.5
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1.5
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67
1.25
0.03
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XOR 2 [14] Proposed design
TABLE 1 COMPARISON OF XOR DESIGNS Gate Area Cell Latency Count (µm2) Count (Clock)
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Fig. 4. (a) Layout of the proposed 2-input XOR Gate. (b) 4-input XOR Gate.
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It should be noted that Toffoli shows that fan-out must be carefully treated when reversibility is the goal [8]. A reversible gate must be used as a copy gate wherever fan-out is needed. By contrast, in [15], authors show that it is possible in QCA to use the fan-out without concern. Furthermore, feedback paths are permitted in QCA.
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A. A New Reversible Gate in QCA Here, we will apply our proposed XOR gate to design a 2:1 multiplexer and then a new reversible gate in QCA based on the proposed multiplexer will be designed. The new approach to design a MUX using a 2-input XOR gate and a majority gate is expressed as follows:
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M(A B,B,C) =M(A‘B+AB‘,B,C) = (A‘B+AB‘)B+ (A‘B+AB‘)C+BC = A‘B+ A‘BC+ AB‘C+BC = Σ (2, 3, 3, 5, 3, 7) = Σ (2, 3, 5, 7) = A‘B+AC
Fig. 5 illustrates the layout of the MUX constructed based on the equation 2. Schematic of the proposed reversible gate mapping three inputs (A, B, and C) to three outputs (P = A, Q = A B C, and R = A‘B + AC) is also shown in Fig. 6(a). Table 2 shows the truth table of the proposed reversible gate, in addition. As it is clear, each distinct input yields a distinct output which presents reversibility (the input information can be fully reconstructed at any time from the outputs). According to Fig. 6, calculation of P does not require any gate; however, both Q and R involve 2 and 2 gates. Hence, the proposed reversible gate employs simply three gates to generate all the outputs.
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Fig. 5. Layout of the MUX using the proposed 2-input XOR gate.
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The QCA layout of the proposed reversible gate is shown in Fig. 6(b) in which the four-phase clocking scheme is used and the clocking zones are shown by different colors of the cells. Using the novel XOR gate along with the new multiplexer provides some considerable advantages for enhancing the performance of the gate. This feature can be easily seen in Fig. 6(b). A single layer wire crossing approach called logical crossing is employed in designing the reversible gate (Fig. 6(b)). This method is based on the interference of clocking phases and their effects on each other [13]. Fig. 6(c) exhibits the graphical symbol of the proposed reversible gate which we use hereafter. B. Realizing the Standard Functions with the Proposed Reversible Gate In order to compare the capability of the proposed reversible gate in constructing combinational logic with other reversible gates, thirteen standard three variable Boolean functions are implemented by the proposed reversible gate in QCA domain. The thirteen standard functions can be implemented as shown in Fig. 7. Any three-variable Boolean function (among the 256 possible functions) can be constructed utilizing one of these standard functions.
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We show that this new reversible gate offers some advantages specifically in the QCA design in terms of area, cell count, delay and overall cost. Table 3 shows a comparison among the proposed gate and the previous works. This comparison is carried out by synthesizing the 13 standard functions. The last row in Table 3 expresses the ability of the proposed gate to synthesize various logical functions with less logic elements. The lower average gate count of our proposed gate indicates its better performance.
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A comparative performance analysis is given in Table 4. Previously suggested reversible gates in QCA are compared in terms of average gate count, cell count, area occupation, delay, method of wire crossing, cost, and overall cost. Table 3 is employed to extract the average gate counts. Cell count, area, delay and method of crossing wire can be obtained from the QCADesigner CAD tool and each of these terms rely on the layouts and the structures of the designs. It should be noted that the layout of Fredkin gate in [16] has been used in calculations.
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Fig. 6. (a) Schematic of the proposed reversible gate, (b) Layout of the proposed reversible gate, and (c) Symbol of the proposed reversible gate. TABLE 2 TRUTH TABLE OF THE PROPOSED REVERSIBLE GATE A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
P 0 0 0 0 1 1 1 1
Q 0 1 1 0 1 0 0 1
R 0 0 1 1 0 1 0 1
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F7 ABC AB C Symbolic Implementation of the functions
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Logical Function
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F1 ABC
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F8 A
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F2 AB
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F9 AB AC BC
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F3 ABC ABC
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F10 AB BC
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F4 ABC ABC
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F11 AB BC
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F13 ABC ABC 13
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Fig. 7. Reversible implementation of the 13 standard functions.
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The reference [17] shows that the average power consumption per cell is about equal for diverse QCA adders. It indicates that cost of a circuit can be expressed as Power × Complexity (number of cells) [18]. It can be anticipated that the cost function of a QCA circuit relies on area, delay and power [19]. The function is as follows: Cost=Area×Delay×Power
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Furthermore, it can be assumed that the average cost for various logic function syntheses also depends on average gate count. Therefore, the overall cost can be assessed as follow: Overall Cost=(Area×Delay×Power)×average gate count (4) It is evident from Table 4 that the implementation cost and overall cost are drastically reduced in the proposed reversible gate. It has the lowest overall cost with reduction of 24% in comparison with the previous most cost-efficient design (CQCA) [5]. Thus, the proposed reversible gate excels the other investigated gates in all aspects with the exception of delay. As a result, the proposed reversible gate permits an efficient implementation option. Besides, our proposed reversible gate is the only one which uses logical cross-over in its structure while the conventional coplanar cross-over has been used in all the previously published works.
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Fredkin [7]
QCA1 [7]
CQCA [5]
AB‘C AB A‘BC+A‘B‘C‘ A‘BC+AB‘C‘ A‘B+BC‘ AB‘+A‘BC A‘BC+ABC‘+A‘B‘C‘ A AB+BC+CA A‘B+B‘C A‘B+BC+AB‘C‘ AB+A‘B‘ ABC‘+A‘B‘C‘+AB‘C+A‘BC Total Number of Gates Average Number of Gates
2 1 3 4 2 3 5 1 4 3 1 1 3 33 2.5384
2 1 3 2 2 2 4 1 4 1 4 2 4 31 2.3846
2 1 2 3 2 3 3 1 1 3 4 2 2 29 2.2307
2 1 3 6 2 5 6 1 1 3 6 4 3 43 3.3077
TABLE 4 COST COMPARISON OF THE REVERSIBLE GATES
Fredkin [7] QCA1 [7] CQCA [5] RUG [20] Mx-cqca [6] RM [21] Proposed
RM [21] 2 1 2 3 2 2 3 1 5 1 2 2 2 28 2.1538
Proposed 2 1 3 3 2 2 3 1 2 2 2 1 2 26 2
QCA Implementation in QCADesigner
Cost
Cell count
Area (µm2)
246 147 117 297 218 224 90
0.37 0.16 0.11 0.46 0.35 0.25 0.09
Delay
Cross-over Type
1 CLK 0.5 CLK 0.5 CLK 2 CLK 1 CLK 1 CLK 1 CLK
coplanar coplanar coplanar coplanar coplanar coplanar logical
91.02 11.76 6.435 273.24 76.3 56 8.1
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Reversible Gate
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Average No. of Gates for Standard Functions 2.3846 2.2307 3.3077 2.3077 2.1538 2
RUG [20] 3 1 2 3 3 3 3 1 1 3 3 1 3 30 2.3077
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1 2 3 4 5 6 7 8 9 10 11 12 13
Standard Function
Overall Cost
217.05 26.23 21.28 630.56 120.61 16.2
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C. Fault Characterization of the Proposed Reversible Gate As precisely mentioned in [7], QCA manufacturing faults can take place in both the chemical synthesis phase (in which the QCA cells are manufactured) and the placement or deposition phase (in which QCA cells are attached to a substrate). Possible faults including missing cell and the additional cell are more likely to occur in the deposition phase than in the chemical synthesis phase and this imperfect placement adversely affect whole QCA system performance [25]. Assuming a single fault in the active devices (proposed XOR gate and inverter) of the proposed reversible gate, we analyze robustness of the gate against 7 intentionally applied fault patterns. To do so, let ai denotes the 3-bit binary pattern whose decimal value is i (e.g. a2 = 010, a7 = 111). We have used ai → aj to demonstrate a reversible logic mapping between a set of inputs and outputs. FPi denotes the ith applied fault pattern to the under test reversible gate. Obviously, different faults can produce different faulty input-to-output mapping functions. There are 7 fault patterns observed in the QCA layout of the proposed reversible gate shown in Fig. 6(b) considering one missing/additional cell defect at the time. Table 5 shows the fault-free output pattern as well as 7 faulty patterns. According to the table, a minimal test vector set with cardinality of 3 should be considered in order to detect all test patterns (< a0, a2, a7 >= < 000, 010, 111 >). TABLE 5 FAULT PATTERNS OF THE PROPOSED REVERSIBLE GATE. .GATE
Input Vector a0 a1 a2 a3 a4 a5 a6 a7
Fault Free a0 a2 a3 a1 a6 a5 a4 a7
FP1 a2 a1 a3 a1 a6 a5 a4 a4
FP2 a0 a1 a3 a1 a6 a4 a6 a5
FP3 a1 a2 a1 a2 a7 a5 a4 a7
FP4 a2 a0 a3 a1 a5 a5 a7 a7
FP5 a0 a2 a3 a1 a4 a6 a4 a6
FP6 a0 a2 a2 a3 a6 a5 a4 a5
FP7 a0 a1 a2 a1 a6 a5 a5 a7
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A. CAD Tool and the Parameters The QCADesigner version 2.0.3 [10] was used to verify all the proposed devices. This tool is a well-known simulation engine developed for evaluating functioning of QCA circuits; this tool has two unlike simulation engines (The Bistable Approximation and Coherence Vector). The Bistable Approximation engine computes state of a QCA cell by a timeindependent approach using kink energy formula that determines cost of two cells having opposed polarizations. Furthermore, the simulation time in this engine is far less than the Coherence Vector engine which studies the time-dependent cells interactions through the same kink energy formula. Both the Bistable Approximation engine and the Coherence Vector one were employed in simulations and the applied parameters in each engine are shown in Table 6.
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B. Simulation of the Proposed Gates The simulation waveform of a gate is similar to the truth table of that gate which verifies the correctness of the design. Fig. 8 shows the simulation results of the proposed XOR gate whose QCA layout was shown earlier in Fig. 4(a). It can be seen that the output is generated after a delay of 2/4 clock cycle (2 clock phases) at Clock 1. The inputs are applied to the XOR gate at clock phase 0 and the output is available at clock phase 1. In addition, we have used an exhaustive vector set for our simulation. As is clear, the combinations of ‗00‘, ‗01‘,‘10‘, and ‗11‘ have been applied as the input values.
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The simulation result of the proposed reversible gate (see Fig. 6(b)) is shown in Fig. 9. The output is produced after a delay of 1 clock cycle (4 clock phases). Clearly, value of A input, has been mapped to the output P after 1 clock cycle. In addition, outputs Q and R are generated simultaneously in correct form.
TABLE 6 BISTABLE APPROXIMATION AND COHERENCE VECTOR PARAMETERS MODEL.
Parameters
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Cell size Layer separation Clock low Clock high Clock shift Clock amplitude factor Relative permittivity Radius of effect Number of samples Convergence tolerance Maximum iterations per sample Temperature
Bistable Approximation 18*18 nm2 11.5 nm 3.8e−023 J 9.8e−022 J 0 2 12.9 65 nm 50000 0.001
Coherence Vector 18*18 nm2 11.5 nm 3.8e−023 J 9.8e−022 J 0 2 12.9 80 nm -----
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1K 4.1356675e− 14 s 1e−016 s 7 e−011 s
Relaxation time
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Time step Total simulation time
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Fig. 8. Simulation results of the proposed 2-input XOR gate.
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Fig. 9. Simulation results of the proposed reversible gate.
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VI. DESIGN OF REVERSIBLE LATCHES
In this section, the reversible latches are designed by means of the proposed reversible gate. A. D latch
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The representative equation of the D latch can be written as Qn 1 DE EQn . This equation can be readily produced utilizing the proposed reversible gate. Fig. 10(a) shows the design of the D latch. B. T latch
The representative equation of the T latch can be written as Qn 1 (T Q) E EQn . This equation can be revised as Qn 1 (TE ) Qn . Fig. 10(b) illustrates the proposed design of a reversible T latch. The first proposed reversible gate produces (TE), which is delivered to the second gate to generate (TE ) Q . C. JK latch The representative equation of the JK latch can also be written as Qn 1 ( JQn KQn ) E EQn . Another way to design JK latch is to compute the equation J Q KQ at first and after that map it to the D Latch. Fig. 10(c) illustrates the proposed design of a reversible JK latch. The first proposed reversible gate produces K , which is mapped to the second proposed reversible gate to produce J Q KQ . The output J Q KQ produced by the second gate is mapped to the third gate rolling as a D latch.
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D. SR latch The representative equation of the SR latch can be written as Qn 1 (S RQn ) E EQn .The equation Qn 1 EQn ES RQn does not differ from the previous one. Fig. 10(d) shows the proposed design of a reversible SR latch. The first gate produces EQn ES while the second one produces RQn . Both of these functions are passed to the third gate in order to finally
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generate EQn ES RQn logical function.
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Fig. 10. (a) Design of the reversible D latch, (b) design of the reversible T latch, (c) design of the reversible JK latch, and (d) design of the reversible SR latch.
E. Generating complement of Q
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It is noteworthy to mention that all of the proposed latches can generate Q by attaching an extra proposed reversible gate to the latches. Fig. 11 illustrates a latch which produces both Q and Q simultaneously. Moreover, two Q lines are available below the Q (which can be considered as a fan-out for complement of Q). In addition, fan-out for Q can be effortlessly produced by readjusting the fixed input of the reversible gate.
Fig. 11. A reversible latch with both Q and Q'.
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F. Simulation of the proposed latches Fig. 12(a) and 12(b) illustrate the QCA layout and the simulation of the D latch, respectively. We get the correct output in 1 clock cycle (4 clock phases) after applying the inputs.
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Fig. 12. (a) QCA layout of the reversible D latch, and (b) Its simulation results.
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The QCA layout and the simulation results of the T latch are presented in Fig. 13(a) and Fig. 13(b), respectively. Since two reversible gates are cascaded serially, the valid output is shaped after 2 cycles (8 clock phases). In order to better understanding of the simulation results, Table 7 is prepared which provides a detailed guidance for Fig. 13(b). Correct functionality of the T latch can be seen in this table. The dotted arrow A represents the condition that when E = 1 and T = 1, the output Q is toggled to 1.
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Fig. 13. QCA layout of the reversible T latch, and (b) simulation results of T latch.
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TABLE 7 CONFIRMATION OF FUNCTIONALITY OF THE T LATCH. Output Dotted Line Input (after 2 clock cycles) A E=1 T=1 Q=0 Q=1 B E=1 T=1 Q=1 Q=0 C E=1 T=0 Q=0 Q=0 D E=0 T=1 Q=1 Q=1
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An extensive effort is required to design sequential circuits with correct functionality in QCA nanotechnology. In order for the designs to operate properly, all signals should arrive simultaneously at each gate. Hence, this issue should be considered carefully in all QCA designs and in our work as well. In the QCA layout of the T latch, the first reversible gate generates logical function TE with delay of one clock cycle. The feedback line Q is delayed by one clock cycle in the second reversible gate for synchronization. Hopefully, this delay can be readily formed by adjusting clock phases of cells in a wire. Fig. 14(a) and 14(b) show the QCA layout and the simulation results of the proposed JK latch, respectively. The correct output is obtained after 3 clock cycles. In the QCA layout of the JK latch, the first reversible gate creates the complement of the input K with delay of one clock cycle. The input J is delayed in the second reversible gate to become synchronized with the complement of input K produced in the first gate. In the same way, input E and feedback Q are delayed by 2 clock cycles in the third gate. Table 8 verifies the functionality of the JK Latch.
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Fig. 14. (a) QCA layout of the reversible JK latch, and (b) simulation results of JK latch.
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TABLE 8 CONFIRMATION OF FUNCTIONALITY OF THE JK LATCH. Output Dotted Line Input (after 3 clock cycles) A E=1 J=1 K=0 Q=0 Q=1 B E=1 J=0 K=1 Q=1 Q=0 C E=1 J=1 K=1 Q=1 Q=0
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The valid output is obtained after 3 clock cycles. Table 9 confirms the correctness of the proposed SR latch design shown in Fig. 15(a). The simulation results of the SR latch are depicted in Fig. 15(b). Table 10 shows the comparison between the reversible latches implemented by Fredkin gate and the ones implemented by the proposed reversible gates. In Table 10, since the numbers of clocking zones required to design the proposed latches are less, they are faster compared to the Fredkin gate based ones. We found a reduction of above 25% in average number of clocking phases. The last column in Table 10 shows the effective areas of the latches. We can assume that the wires between the gates do not have significant effect on the total area of a latch; thus, the area of a latch can be found by the following equation: Latch Area = (# of Reversible gates) × (Area of a Reversible gate) (5) Clearly, the proposed method of latch design achieves up to 74% area savings.
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(b) Fig. 15. (a) QCA layout of the reversible SR latch, and (b) simulation results of SR latch.
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TABLE 9 CONFIRMATION OF FUNCTIONALITY OF THE SR LATCH. Output Dotted Line Input (after 2 clock cycles) A E=1 S=0 R=1 Q=1 Q=0 B E=1 S=1 R=0 Q=0 Q=1 C E=1 S=0 R=0 Q=1 Q=1
Fredkin [16]
Proposed
TABLE 10 COMPARISON OF THE REVERSIBLE LATCHES.
Latch Category
No. of Reversible Gates
No. of Gates in Critical Path
Delay (No. of Clock Cycles)
D Latch T Latch JK Latch SR Latch D Latch T Latch JK Latch SR Latch
1 3 4 4 1 2 3 3
1 2 4 4 1 2 3 2
1 2 4 4 1 2 3 2
Area of the Gate used in the latches m2
0.37
0.09
Effective Area of the Latch (m2)
0.37 1.11 1.48 1.48 0.11 0.24 0.34 0.47
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In this paper, we have introduced a novel universal reversible gate. The study has a direct application in designing sequential and combinational circuits in QCA domain where reversibility is an objective. First, a novel 2-input XOR gate has been presented and then the new potent compact reversible gate has been proposed based on the XOR gate. The performance of the proposed reversible gate was verified by synthesizing standard benchmark combinational functions (13 standard functions). It was shown that the proposed reversible gate has the lowest overall cost and is associated with 24% reduction in cost when compared with the previous most cost-efficient designs.
REFERENCES
[10] [11] [12] [13] [14]
[15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26]
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P. D. Tougaw and C. S. Lent, "Logical devices implemented using quantum cellular automata," Journal of Applied physics, vol. 75, pp. 1818-1825, 1994. R. Landauer, ―Irreversibility and heat generation in the computational process,‖ IBM J. Res. Dev., vol. 5, pp. 183–191, 1961. C. H. Bennett, "Logical reversibility of computation," IBM journal of Research and Development, vol. 17, pp. 525-532, 1973. S. Sheikhfaal, S. Angizi, S. Sarmadi, M. H. Moaiyeri, and S. Sayedsalehi, "Designing efficient QCA logical circuits with power dissipation analysis," Microelectronics Journal, vol. 46, pp. 462-471, 2015. H. Thapliyal and N. Ranganathan, "Conservative QCA gate (CQCA) for designing concurrently testable molecular QCA circuits," in VLSI Design, 2009 22nd International Conference on, 2009, pp. 511-516. H. Thapliyal, N. Ranganathan, and S. Kotiyal, "Design of testable reversible sequential circuits," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 21, pp. 1201-1209, 2013. X. Ma, J. Huang, C. Metra, and F. Lombardi. 2006. ―Testing Reversible 1D Arrays for Molecular QCA,‖ In Proceedings of the 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '06). IEEE Computer Society, Washington, DC, USA, 71-79. T. Toffoli, ―Reversible computing,‖ MIT Laboratory for Computer Science, Technical Report,MIT/LCS/TM-151, Feb 1980. M. Ottavi, S. Pontarelli, E. P. DeBenedictis, A. Salsano, S. Frost-Murphy, P. M. Kogge, et al., "Partially reversible pipelined QCA circuits: combining low power with high throughput," Nanotechnology, IEEE Transactions on, vol. 10, pp. 1383-1393, 2011. QCADesigner. (2008). [Online]. Available at: http://www.qcadesigner.ca/ M. T. Niemier, Designing digital systems in quantum cellular automata [M.S. thesis], University of Notre Dame, 2004. S. Hashemi, R. Farazkish, and K. Navi, ―New quantum dot cellular automata cell arrangements,‖ Journal of Computational and Theoretical Nanoscience, vol. 10, no. 4, pp. 798–809, 2013. S. Angizi, E. Alkaldy, N. Bagherzadeh, and K. Navi, "Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata," Journal of Low Power Electronics, vol. 10, pp. 259-271, 2014. A. M. Chabi, S. Sayedsalehi, S. Angizi, and K. Navi, ―Efficient QCA Exclusive-or and Multiplexer Circuits Based on a Nanoelectronic-compatible Designing Approach‖, International Scholarly Research Notices, Hindawi, Volume 2014, Article ID 463967, pp. 1-9, 2014. J. Huang, X. Ma, and F. Lombardi, "Energy analysis of QCA circuits for reversible computing," in Nanotechnology, 2006. IEEENANO 2006. Sixth IEEE Conference on, 2006, pp. 39-42. H. Thapliyal and N. Ranganathan, "Reversible logic-based concurrently testable latches for molecular QCA," Nanotechnology, IEEE Transactions on, vol. 9, pp. 62-69, 2010. S. Srivastava, S. Sarkar, and S. Bhanja, ―Estimation of upper bound of power dissipation in QCA circuits,‖ IEEE Trans. Nanotechnol.,vol. 8, no. 1, pp. 116–127, Jan. 2009. M. Gladshtein, "Quantum-dot cellular automata serial decimal adder," Nanotechnology, IEEE Transactions on, vol. 10, pp. 13771382, 2011. V. G. Oklobdzija Ed, The Computer, Engineering Handbook. Boca Raton, FL: CRC Press, 2002, pp. 81–86. B. Sen, D. Saran, M. Saha, and B. K. Sikdar, "Synthesis Of Reversible Universal Logic Around QCA With Online Testability," in Electronic System Design (ISED), 2011 International Symposium on, 2011, pp. 236-241. B. Sen, M. Dutta, M. Goswami, and B. K. Sikdar, "Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability," Microelectronics Journal, vol. 45, pp. 1522-1532, 2014. S. Angizi, S. Sarmadi, S. Sayedsalehi, and K. Navi, "Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata," Microelectronics Journal, vol. 46, pp. 43-51, 2015. S. Sayedsalehi, M. R. Azghadi, S. Angizi, and K. Navi, "Restoring and non-restoring array divider designs in Quantum-dot Cellular Automata," Information Sciences, vol. 311, pp. 86-101, 2015. K. Hennessy and C. S. Lent, "Clocking of molecular quantum-dot cellular automata," Journal of Vacuum Science & Technology B, vol. 19, pp. 1752-1755, 2001. X. Ma, J. Huang, C. Metra, and F. Lombardi, "Detecting multiple faults in one-dimensional arrays of reversible QCA gates," Journal of Electronic Testing, vol. 25, pp. 39-54, 2009. A. M. Chabi, A. Roohi, R. F. DeMara, S. Angizi, K. Navi, and H. Khademolhosseini, "Cost-efficient QCA reversible combinational circuits based on a new reversible gate," in Computer Architecture and Digital Systems (CADS), 2015 18th CSI International Symposium on, 2015, pp. 1-6.
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Furthermore, as case studies, the proposed reversible gate was used to design the known types of latches (D latch, T latch, JK latch, and SR latch) which are essential elements in every sequential circuit. Almost 25% reduction in delay and above 70% reduction in area in comparison to the previous latch designs in which Fredkin gate (one of the most studied reversible logic gates) is used, are observed. Thus, it is expected that the proposed reversible gate and the latches presented in this paper will lead to conspicuous hardware savings in many QCA designs.
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Amir Mokhtar Chabi received his B. Sc. from Isfahan University of Technology, Isfahan, Iran in 2009 in hardware engineering and M.Sc. degree in computer engineering from Shahid Beheshti University, Tehran, Iran in 2011. His research interests include Nanoelectronics with emphasis on Emerging Technologies, Quantum-dot Cellular Automata, CNFET, Multi-Value Logic and Computer Architecture. He is currently is faculty of Computer Engineering, Department in Persian Gulf University Bushehr, Iran. He also is member of NQC Lab in Shahid Beheshti University, G. C., Tehran, Iran. received B.Sc. degree in computer engineering in 2008 from Shiraz University, also received his M.Sc. degree in computer architecture at Department of Computer Science and Research Branch of IAU, Tehran, Iran, in 2011. He is currently working degree in electrical engineering at the University of Central Florida, Orlando, USA. interests include Spin based computing Architectures, Reconfigurable Architecture, Arithmetic. He is a student member of IEEE.
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Arman Roohi Shiraz, Iran. He Engineering, toward the Ph.D. His research and Computer
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Hossein Khademolhosseini received B.Sc. degree in computer engineering in 2008 from Shiraz University, Shiraz, Iran. He also received his M.Sc. degree in computer architecture at Department of Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran, in 2011. He is currently working toward the Ph.D. degree in computer architecture engineering at the Science and Research Branch of IAU. His research interests are computer arithmetic, photonic NoC and electronics with emphasis on QCA and VLSI.
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Shadi Sheikhfaal received her B.Sc. in computer hardware engineering from Ardebil Branch of IAU, Ardebil, Iran in 2012 and her M.Sc. in computer engineering, computer architecture from Science and Research Branch, IAU, Tabriz, Iran in 2014. She is currently a research assistant at School of Computer Science of IPM, Tehran, Iran. Her research interests include low power design and nanoelectronic circuit design with emphasis on Quantum-dot cellular automata.
Shaahin Angizi received his B.Sc. in Computer Engineering, Hardware from South Tehran Branch of IAU, Tehran, Iran in 2012 and his M.Sc. in Computer Engineering, Computer Systems Architecture from Science and Research Branch of IAU, Tabriz, Iran in 2014. He is currently working toward the Ph.D. degree in Computer Engineering at University of Central Florida, Orlando, USA. His research interests include high performance and low power VLSI designs and Nanoelectronics with emphasis on Spintronic and QCA. He is a student member of IEEE.
Keivan Navi received the Ph.D. degree in computer architecture from Paris XI University, Paris, France, in 1995 and the M.Sc. degree in electronics engineering from Sharif University of Technology, Tehran, Iran in 1990. He is currently a Full Professor in Faculty of Electrical and Computer Engineering of Shahid Beheshti University and also a senior member of IEEE. He is in charge of the Nanotechnology and Quantum Computing Laboratory (NQC Lab.). His research interests include Nanoelectronics with emphasis on CNFET, QCA and SET, Computer Arithmetic, Interconnection Network Design and Quantum Computing and cryptography.
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Ronald F. DeMara received the Ph.D. degree in Computer Engineering from the University of Southern California in 1992. Since 1993, he has been a full-time faculty member at the University of Central Florida where he is Professor and Computer Engineering Program Coordinator. His research interests are in Computer Architecture with emphasis on Evolvable and Resilient Hardware, on which he has published approximately 170 articles. He is a Senior Member of IEEE and has served on the Editorial Boards of IEEE Transactions on VLSI Systems, ACM Transactions on Embedded Systems, Journal of Circuits, Systems, and Computers, the journal Microprocessors and Microsystems, various conference program committees, and is currently an Associate Editor of IEEE Transactions on Computers. He received the Joseph M. Bidenbach Outstanding Engineering Educator Award in 2008, the highest educational honor from IEEE in the Southeast United States.
Towards Ultra-efficient QCA Reversible Circuits Amir Mokhtar Chabi , Arman Roohi , Hossein Khademolhosseini , Shadi Sheikhfaal , Shaahin Angizi , Keivan Navi , Ronald F. DeMara PII: DOI: Reference:
S0141-9331(16)30243-5 10.1016/j.micpro.2016.09.015 MICPRO 2484
To appear in:
Microprocessors and Microsystems
Received date: Revised date: Accepted date:
24 December 2015 22 July 2016 30 September 2016
Please cite this article as: Amir Mokhtar Chabi , Arman Roohi , Hossein Khademolhosseini , Shadi Sheikhfaal , Shaahin Angizi , Keivan Navi , Ronald F. DeMara , Towards Ultra-efficient QCA Reversible Circuits, Microprocessors and Microsystems (2016), doi: 10.1016/j.micpro.2016.09.015
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Towards Ultra-efficient QCA Reversible Circuits Amir Mokhtar Chabia, Arman Roohib, Hossein Khademolhosseinic, Shadi Sheikhfaald, Shaahin Angizid,*, Keivan Navid, Ronald F. DeMarab a
Department of Computer, Faculty of Engineering, Persian Gulf University, Bushehr, Iran Department of Electrical Engineering and Computer Science, University of Central Florida, Orlando, USA c Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran d School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran b
Abstract—Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future
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computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most costefficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.
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Keywords—Nanoelectronic; Combinational circuits; Sequential circuits; XOR gate; Reversible logic; Quantum cellular automata.
I. INTRODUCTION
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Emerging nanotechnologies have been developed to achieve a performance that is not accessible by CMOS due to its serious hurdle in reduction of feature sizes. Quantum- dot Cellular Automata (QCA) is one of these promising alternatives to transistor-based technologies in the near future [1]. Outstanding properties including extremely high density and fast operation speed at tera-hertz frequency range together with ultra-low power dissipation are the potential offered by this method of computation [2],[3],[4]. Since QCA is radically different from today‘s CMOS technology, different and clearly new design approaches are required.
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To date lots of attempts have been made for presenting efficient QCA architectures [5],[7],[11-14],[22]. Reversible computation has been proposed for its application in energy lossless computing. Landauer principle states that the erasure of one bit of information in computing, dissipates at least KBTln2 Joules, where KB is Boltzmann‘s constant and T is the temperature [2],[6],[26]; however, Bennett shows this can be avoided by means of reversible gates and hence, zero energy dissipation is possible only if all the utilized gates are reversible [3]. Reversible gates are building blocks of reversible logic. Reversible gates provide unique mapping between the input vectors and the output ones, thus the number of inputs must be equal to that of outputs [7],[16],[20].
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In this paper, a new two-input XOR gate and also a new approach to implement 2:1 multiplexer are presented. In addition, an efficient universal reversible gate based on the proposed XOR gate is designed. Considering this universal gate as the main building block, numerous QCA reversible benchmarks are implemented.
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The paper is organized as follows: Section II presents the background of QCA and some related works. Design and layout of the novel XOR gate is presented in Section III. In Section IV, design of an efficient reversible gate in QCA is provided. Section V describes the simulation parameters used to verify the designs along with the simulation results. Section VI addresses the proposed QCA latches and sequential circuits. Conclusions are given in Section VII. II. BACKGROUND
A. The QCA Basics A QCA cell consists of four quantum dots which are located in the corners of a square structure. A cell contains two extra free electrons which can tunnel between the dots within the cell. Through Columbic effects, two possible polarizations (the locations of the electrons in the cell) can be shaped. These two potential states can be considered as the binary states 1 and 0. A QCA cell is shown in Fig. 1. Two fundamental building blocks of each QCA circuit are the inverter and the majority gate. Fig. 2 shows the basic QCA devices. A straightforward and excellent tutorial can be found in [1], [23].
* Corresponding Author Email Addresses: [email protected] (A.M. Chabi), [email protected] (A. Roohi), [email protected] (H. Khademolhosseini, [email protected] (S. Sheikhfaal), [email protected] (S. Angizi), [email protected] (K.Navi), [email protected] (R. F. DeMara)
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Although the 3-input majority gate and the inverter gates were the fundamental elements in various preceding works, the evaluations have shown that the majority voter is not efficiently used during technology mapping. In order to overcome this drawback, various kinds of gates have been introduced [4],[22]. A four-phase clocking scheme for QCA (also known as Landauer clocking) generally used in QCA design has been proposed in [24], and the present work is also based on this clocking scheme. The consecutive clocking zones are indicated in our layouts by the different colors of the cells as shown in Fig. 3.
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Fig. 1. QCA Cell.
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Fig. 2. Basic QCA devices, (a) Inverter. (b) Majority Gate.
Fig. 3. The four clocking zones in a QCA wire corresponding to the four clock signals.
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B. Related Works Concurrently testable designs for the latches (D latch, T latch, JK latch, and SR latch) are presented in [16]. The Fredkin gate is used for implementing reversible latches in this paper. The use of a new reversible logic gate (CQCA) to design concurrently testable circuits in QCA was done in [5]. It is shown that the CQCA gate performs better than the original Fredkin gate in terms of area and speed. A new conservative logic gate called multiplexer conservative QCA gate (MX-cqca) was presented in [6]. Despite the similar properties of the MX-cqca and the Fredkin gate as 2:1 multiplexers, the MX-cqca is not reversible. Two new reversible gates (denoted as QCA1 and QCA2) have been proposed in [7]. These reversible gates have been compared to Fredkin and Toffoli gates [8] and a comprehensive analysis were made through the test domain. III. THE NOVEL XOR GATE
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A diverse form of XOR layout has been offered so far [11],[12] and in most of the designs 3-input majority gate has been utilized. XOR gate is an essential element to build the Sum output in adder designs and moreover, due to the great importance of XOR gate in digital logic designs, several XOR-based circuits have been proposed so far. In [9], a binary tree made of XOR gates as a parity checker and also a general model for assessing power consumption under the two clocking methods (Landauer and Bennett) for QCA operation have been presented.
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Fig. 4(a) demonstrates the novel 2-input XOR gate. Contrary to previously reported designs for implementation of 2-input XOR, our proposed one uses explicit interactions between QCA cells to produce the expected result and it is not majority based. Hence, this highly integrated QCA layout can significantly reduce the cell count, area and delay. Table 1 displays the comparison between the proposed XOR gate and the former ones. As it is apparent from the table, our proposed XOR is more competitive in terms of cell count (complexity) and delay. It is worth mentioning that in constructing large circuits using the smaller designs, complexity and delay of the small building blocks are of much importance. The proposed structure for 2-input XOR gate (with 0.5 clock cycle delay) can be effectively utilized as a building block in designing multi-input XOR gates. A cost-effective 3-input XOR gate can be designed using only 2 cascaded 2-input XOR gates with 0.75 clock cycle. In the same way, an ultra-high speed 4-input XOR can be effectively designed using 3 cascaded gates working in 1 clock cycle as shown in Fig. 4(b). Without loss of generality, the delay of an n-input XOR gate based on our design can be written as: T XORN
n T XOR 2 ,n 2 2
(1) IV. DESIGN OF AN EFFICIENT REVERSIBLE GATE IN QCA
In this section, a new approach to implement a 2:1 multiplexer based on the novel XOR gate is presented. Moreover, a potent universal reversible gate using the proposed gates is designed. As mentioned previously, a logic gate (function) is
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called reversible if the mapping of its inputs to outputs is bijective (one-to-one correspondence) and hence, the number of inputs is equal to the number of outputs. The prevailing reversible gates are costly in QCA implementation. This motivated us to propose a novel reversible gate particularly suited for QCA implementation.
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XOR 2 [11] XOR 2 [12] XOR 2 [13]
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Cross-over Type Coplanar (rotated cells) Coplanar (rotated cells) Coplanar (clocking based)
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TABLE 1 COMPARISON OF XOR DESIGNS Gate Area Cell Latency Count (µm2) Count (Clock)
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Fig. 4. (a) Layout of the proposed 2-input XOR Gate. (b) 4-input XOR Gate.
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It should be noted that Toffoli shows that fan-out must be carefully treated when reversibility is the goal [8]. A reversible gate must be used as a copy gate wherever fan-out is needed. By contrast, in [15], authors show that it is possible in QCA to use the fan-out without concern. Furthermore, feedback paths are permitted in QCA.
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A. A New Reversible Gate in QCA Here, we will apply our proposed XOR gate to design a 2:1 multiplexer and then a new reversible gate in QCA based on the proposed multiplexer will be designed. The new approach to design a MUX using a 2-input XOR gate and a majority gate is expressed as follows:
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M(A B,B,C) =M(A‘B+AB‘,B,C) = (A‘B+AB‘)B+ (A‘B+AB‘)C+BC = A‘B+ A‘BC+ AB‘C+BC = Σ (2, 3, 3, 5, 3, 7) = Σ (2, 3, 5, 7) = A‘B+AC
Fig. 5 illustrates the layout of the MUX constructed based on the equation 2. Schematic of the proposed reversible gate mapping three inputs (A, B, and C) to three outputs (P = A, Q = A B C, and R = A‘B + AC) is also shown in Fig. 6(a). Table 2 shows the truth table of the proposed reversible gate, in addition. As it is clear, each distinct input yields a distinct output which presents reversibility (the input information can be fully reconstructed at any time from the outputs). According to Fig. 6, calculation of P does not require any gate; however, both Q and R involve 2 and 2 gates. Hence, the proposed reversible gate employs simply three gates to generate all the outputs.
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Fig. 5. Layout of the MUX using the proposed 2-input XOR gate.
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The QCA layout of the proposed reversible gate is shown in Fig. 6(b) in which the four-phase clocking scheme is used and the clocking zones are shown by different colors of the cells. Using the novel XOR gate along with the new multiplexer provides some considerable advantages for enhancing the performance of the gate. This feature can be easily seen in Fig. 6(b). A single layer wire crossing approach called logical crossing is employed in designing the reversible gate (Fig. 6(b)). This method is based on the interference of clocking phases and their effects on each other [13]. Fig. 6(c) exhibits the graphical symbol of the proposed reversible gate which we use hereafter. B. Realizing the Standard Functions with the Proposed Reversible Gate In order to compare the capability of the proposed reversible gate in constructing combinational logic with other reversible gates, thirteen standard three variable Boolean functions are implemented by the proposed reversible gate in QCA domain. The thirteen standard functions can be implemented as shown in Fig. 7. Any three-variable Boolean function (among the 256 possible functions) can be constructed utilizing one of these standard functions.
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We show that this new reversible gate offers some advantages specifically in the QCA design in terms of area, cell count, delay and overall cost. Table 3 shows a comparison among the proposed gate and the previous works. This comparison is carried out by synthesizing the 13 standard functions. The last row in Table 3 expresses the ability of the proposed gate to synthesize various logical functions with less logic elements. The lower average gate count of our proposed gate indicates its better performance.
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A comparative performance analysis is given in Table 4. Previously suggested reversible gates in QCA are compared in terms of average gate count, cell count, area occupation, delay, method of wire crossing, cost, and overall cost. Table 3 is employed to extract the average gate counts. Cell count, area, delay and method of crossing wire can be obtained from the QCADesigner CAD tool and each of these terms rely on the layouts and the structures of the designs. It should be noted that the layout of Fredkin gate in [16] has been used in calculations.
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Fig. 6. (a) Schematic of the proposed reversible gate, (b) Layout of the proposed reversible gate, and (c) Symbol of the proposed reversible gate. TABLE 2 TRUTH TABLE OF THE PROPOSED REVERSIBLE GATE A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
P 0 0 0 0 1 1 1 1
Q 0 1 1 0 1 0 0 1
R 0 0 1 1 0 1 0 1
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F7 ABC AB C Symbolic Implementation of the functions
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Fig. 7. Reversible implementation of the 13 standard functions.
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The reference [17] shows that the average power consumption per cell is about equal for diverse QCA adders. It indicates that cost of a circuit can be expressed as Power × Complexity (number of cells) [18]. It can be anticipated that the cost function of a QCA circuit relies on area, delay and power [19]. The function is as follows: Cost=Area×Delay×Power
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Furthermore, it can be assumed that the average cost for various logic function syntheses also depends on average gate count. Therefore, the overall cost can be assessed as follow: Overall Cost=(Area×Delay×Power)×average gate count (4) It is evident from Table 4 that the implementation cost and overall cost are drastically reduced in the proposed reversible gate. It has the lowest overall cost with reduction of 24% in comparison with the previous most cost-efficient design (CQCA) [5]. Thus, the proposed reversible gate excels the other investigated gates in all aspects with the exception of delay. As a result, the proposed reversible gate permits an efficient implementation option. Besides, our proposed reversible gate is the only one which uses logical cross-over in its structure while the conventional coplanar cross-over has been used in all the previously published works.
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Fredkin [7]
QCA1 [7]
CQCA [5]
AB‘C AB A‘BC+A‘B‘C‘ A‘BC+AB‘C‘ A‘B+BC‘ AB‘+A‘BC A‘BC+ABC‘+A‘B‘C‘ A AB+BC+CA A‘B+B‘C A‘B+BC+AB‘C‘ AB+A‘B‘ ABC‘+A‘B‘C‘+AB‘C+A‘BC Total Number of Gates Average Number of Gates
2 1 3 4 2 3 5 1 4 3 1 1 3 33 2.5384
2 1 3 2 2 2 4 1 4 1 4 2 4 31 2.3846
2 1 2 3 2 3 3 1 1 3 4 2 2 29 2.2307
2 1 3 6 2 5 6 1 1 3 6 4 3 43 3.3077
TABLE 4 COST COMPARISON OF THE REVERSIBLE GATES
Fredkin [7] QCA1 [7] CQCA [5] RUG [20] Mx-cqca [6] RM [21] Proposed
RM [21] 2 1 2 3 2 2 3 1 5 1 2 2 2 28 2.1538
Proposed 2 1 3 3 2 2 3 1 2 2 2 1 2 26 2
QCA Implementation in QCADesigner
Cost
Cell count
Area (µm2)
246 147 117 297 218 224 90
0.37 0.16 0.11 0.46 0.35 0.25 0.09
Delay
Cross-over Type
1 CLK 0.5 CLK 0.5 CLK 2 CLK 1 CLK 1 CLK 1 CLK
coplanar coplanar coplanar coplanar coplanar coplanar logical
91.02 11.76 6.435 273.24 76.3 56 8.1
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Standard Function
Overall Cost
217.05 26.23 21.28 630.56 120.61 16.2
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C. Fault Characterization of the Proposed Reversible Gate As precisely mentioned in [7], QCA manufacturing faults can take place in both the chemical synthesis phase (in which the QCA cells are manufactured) and the placement or deposition phase (in which QCA cells are attached to a substrate). Possible faults including missing cell and the additional cell are more likely to occur in the deposition phase than in the chemical synthesis phase and this imperfect placement adversely affect whole QCA system performance [25]. Assuming a single fault in the active devices (proposed XOR gate and inverter) of the proposed reversible gate, we analyze robustness of the gate against 7 intentionally applied fault patterns. To do so, let ai denotes the 3-bit binary pattern whose decimal value is i (e.g. a2 = 010, a7 = 111). We have used ai → aj to demonstrate a reversible logic mapping between a set of inputs and outputs. FPi denotes the ith applied fault pattern to the under test reversible gate. Obviously, different faults can produce different faulty input-to-output mapping functions. There are 7 fault patterns observed in the QCA layout of the proposed reversible gate shown in Fig. 6(b) considering one missing/additional cell defect at the time. Table 5 shows the fault-free output pattern as well as 7 faulty patterns. According to the table, a minimal test vector set with cardinality of 3 should be considered in order to detect all test patterns (< a0, a2, a7 >= < 000, 010, 111 >). TABLE 5 FAULT PATTERNS OF THE PROPOSED REVERSIBLE GATE. .GATE
Input Vector a0 a1 a2 a3 a4 a5 a6 a7
Fault Free a0 a2 a3 a1 a6 a5 a4 a7
FP1 a2 a1 a3 a1 a6 a5 a4 a4
FP2 a0 a1 a3 a1 a6 a4 a6 a5
FP3 a1 a2 a1 a2 a7 a5 a4 a7
FP4 a2 a0 a3 a1 a5 a5 a7 a7
FP5 a0 a2 a3 a1 a4 a6 a4 a6
FP6 a0 a2 a2 a3 a6 a5 a4 a5
FP7 a0 a1 a2 a1 a6 a5 a5 a7
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A. CAD Tool and the Parameters The QCADesigner version 2.0.3 [10] was used to verify all the proposed devices. This tool is a well-known simulation engine developed for evaluating functioning of QCA circuits; this tool has two unlike simulation engines (The Bistable Approximation and Coherence Vector). The Bistable Approximation engine computes state of a QCA cell by a timeindependent approach using kink energy formula that determines cost of two cells having opposed polarizations. Furthermore, the simulation time in this engine is far less than the Coherence Vector engine which studies the time-dependent cells interactions through the same kink energy formula. Both the Bistable Approximation engine and the Coherence Vector one were employed in simulations and the applied parameters in each engine are shown in Table 6.
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B. Simulation of the Proposed Gates The simulation waveform of a gate is similar to the truth table of that gate which verifies the correctness of the design. Fig. 8 shows the simulation results of the proposed XOR gate whose QCA layout was shown earlier in Fig. 4(a). It can be seen that the output is generated after a delay of 2/4 clock cycle (2 clock phases) at Clock 1. The inputs are applied to the XOR gate at clock phase 0 and the output is available at clock phase 1. In addition, we have used an exhaustive vector set for our simulation. As is clear, the combinations of ‗00‘, ‗01‘,‘10‘, and ‗11‘ have been applied as the input values.
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The simulation result of the proposed reversible gate (see Fig. 6(b)) is shown in Fig. 9. The output is produced after a delay of 1 clock cycle (4 clock phases). Clearly, value of A input, has been mapped to the output P after 1 clock cycle. In addition, outputs Q and R are generated simultaneously in correct form.
TABLE 6 BISTABLE APPROXIMATION AND COHERENCE VECTOR PARAMETERS MODEL.
Parameters
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Cell size Layer separation Clock low Clock high Clock shift Clock amplitude factor Relative permittivity Radius of effect Number of samples Convergence tolerance Maximum iterations per sample Temperature
Bistable Approximation 18*18 nm2 11.5 nm 3.8e−023 J 9.8e−022 J 0 2 12.9 65 nm 50000 0.001
Coherence Vector 18*18 nm2 11.5 nm 3.8e−023 J 9.8e−022 J 0 2 12.9 80 nm -----
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1K 4.1356675e− 14 s 1e−016 s 7 e−011 s
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Fig. 8. Simulation results of the proposed 2-input XOR gate.
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Fig. 9. Simulation results of the proposed reversible gate.
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VI. DESIGN OF REVERSIBLE LATCHES
In this section, the reversible latches are designed by means of the proposed reversible gate. A. D latch
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The representative equation of the D latch can be written as Qn 1 DE EQn . This equation can be readily produced utilizing the proposed reversible gate. Fig. 10(a) shows the design of the D latch. B. T latch
The representative equation of the T latch can be written as Qn 1 (T Q) E EQn . This equation can be revised as Qn 1 (TE ) Qn . Fig. 10(b) illustrates the proposed design of a reversible T latch. The first proposed reversible gate produces (TE), which is delivered to the second gate to generate (TE ) Q . C. JK latch The representative equation of the JK latch can also be written as Qn 1 ( JQn KQn ) E EQn . Another way to design JK latch is to compute the equation J Q KQ at first and after that map it to the D Latch. Fig. 10(c) illustrates the proposed design of a reversible JK latch. The first proposed reversible gate produces K , which is mapped to the second proposed reversible gate to produce J Q KQ . The output J Q KQ produced by the second gate is mapped to the third gate rolling as a D latch.
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D. SR latch The representative equation of the SR latch can be written as Qn 1 (S RQn ) E EQn .The equation Qn 1 EQn ES RQn does not differ from the previous one. Fig. 10(d) shows the proposed design of a reversible SR latch. The first gate produces EQn ES while the second one produces RQn . Both of these functions are passed to the third gate in order to finally
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generate EQn ES RQn logical function.
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Fig. 10. (a) Design of the reversible D latch, (b) design of the reversible T latch, (c) design of the reversible JK latch, and (d) design of the reversible SR latch.
E. Generating complement of Q
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It is noteworthy to mention that all of the proposed latches can generate Q by attaching an extra proposed reversible gate to the latches. Fig. 11 illustrates a latch which produces both Q and Q simultaneously. Moreover, two Q lines are available below the Q (which can be considered as a fan-out for complement of Q). In addition, fan-out for Q can be effortlessly produced by readjusting the fixed input of the reversible gate.
Fig. 11. A reversible latch with both Q and Q'.
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F. Simulation of the proposed latches Fig. 12(a) and 12(b) illustrate the QCA layout and the simulation of the D latch, respectively. We get the correct output in 1 clock cycle (4 clock phases) after applying the inputs.
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Fig. 12. (a) QCA layout of the reversible D latch, and (b) Its simulation results.
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The QCA layout and the simulation results of the T latch are presented in Fig. 13(a) and Fig. 13(b), respectively. Since two reversible gates are cascaded serially, the valid output is shaped after 2 cycles (8 clock phases). In order to better understanding of the simulation results, Table 7 is prepared which provides a detailed guidance for Fig. 13(b). Correct functionality of the T latch can be seen in this table. The dotted arrow A represents the condition that when E = 1 and T = 1, the output Q is toggled to 1.
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Fig. 13. QCA layout of the reversible T latch, and (b) simulation results of T latch.
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TABLE 7 CONFIRMATION OF FUNCTIONALITY OF THE T LATCH. Output Dotted Line Input (after 2 clock cycles) A E=1 T=1 Q=0 Q=1 B E=1 T=1 Q=1 Q=0 C E=1 T=0 Q=0 Q=0 D E=0 T=1 Q=1 Q=1
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An extensive effort is required to design sequential circuits with correct functionality in QCA nanotechnology. In order for the designs to operate properly, all signals should arrive simultaneously at each gate. Hence, this issue should be considered carefully in all QCA designs and in our work as well. In the QCA layout of the T latch, the first reversible gate generates logical function TE with delay of one clock cycle. The feedback line Q is delayed by one clock cycle in the second reversible gate for synchronization. Hopefully, this delay can be readily formed by adjusting clock phases of cells in a wire. Fig. 14(a) and 14(b) show the QCA layout and the simulation results of the proposed JK latch, respectively. The correct output is obtained after 3 clock cycles. In the QCA layout of the JK latch, the first reversible gate creates the complement of the input K with delay of one clock cycle. The input J is delayed in the second reversible gate to become synchronized with the complement of input K produced in the first gate. In the same way, input E and feedback Q are delayed by 2 clock cycles in the third gate. Table 8 verifies the functionality of the JK Latch.
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Fig. 14. (a) QCA layout of the reversible JK latch, and (b) simulation results of JK latch.
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TABLE 8 CONFIRMATION OF FUNCTIONALITY OF THE JK LATCH. Output Dotted Line Input (after 3 clock cycles) A E=1 J=1 K=0 Q=0 Q=1 B E=1 J=0 K=1 Q=1 Q=0 C E=1 J=1 K=1 Q=1 Q=0
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The valid output is obtained after 3 clock cycles. Table 9 confirms the correctness of the proposed SR latch design shown in Fig. 15(a). The simulation results of the SR latch are depicted in Fig. 15(b). Table 10 shows the comparison between the reversible latches implemented by Fredkin gate and the ones implemented by the proposed reversible gates. In Table 10, since the numbers of clocking zones required to design the proposed latches are less, they are faster compared to the Fredkin gate based ones. We found a reduction of above 25% in average number of clocking phases. The last column in Table 10 shows the effective areas of the latches. We can assume that the wires between the gates do not have significant effect on the total area of a latch; thus, the area of a latch can be found by the following equation: Latch Area = (# of Reversible gates) × (Area of a Reversible gate) (5) Clearly, the proposed method of latch design achieves up to 74% area savings.
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(b) Fig. 15. (a) QCA layout of the reversible SR latch, and (b) simulation results of SR latch.
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TABLE 9 CONFIRMATION OF FUNCTIONALITY OF THE SR LATCH. Output Dotted Line Input (after 2 clock cycles) A E=1 S=0 R=1 Q=1 Q=0 B E=1 S=1 R=0 Q=0 Q=1 C E=1 S=0 R=0 Q=1 Q=1
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TABLE 10 COMPARISON OF THE REVERSIBLE LATCHES.
Latch Category
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Delay (No. of Clock Cycles)
D Latch T Latch JK Latch SR Latch D Latch T Latch JK Latch SR Latch
1 3 4 4 1 2 3 3
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Area of the Gate used in the latches m2
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Effective Area of the Latch (m2)
0.37 1.11 1.48 1.48 0.11 0.24 0.34 0.47
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In this paper, we have introduced a novel universal reversible gate. The study has a direct application in designing sequential and combinational circuits in QCA domain where reversibility is an objective. First, a novel 2-input XOR gate has been presented and then the new potent compact reversible gate has been proposed based on the XOR gate. The performance of the proposed reversible gate was verified by synthesizing standard benchmark combinational functions (13 standard functions). It was shown that the proposed reversible gate has the lowest overall cost and is associated with 24% reduction in cost when compared with the previous most cost-efficient designs.
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Furthermore, as case studies, the proposed reversible gate was used to design the known types of latches (D latch, T latch, JK latch, and SR latch) which are essential elements in every sequential circuit. Almost 25% reduction in delay and above 70% reduction in area in comparison to the previous latch designs in which Fredkin gate (one of the most studied reversible logic gates) is used, are observed. Thus, it is expected that the proposed reversible gate and the latches presented in this paper will lead to conspicuous hardware savings in many QCA designs.
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Amir Mokhtar Chabi received his B. Sc. from Isfahan University of Technology, Isfahan, Iran in 2009 in hardware engineering and M.Sc. degree in computer engineering from Shahid Beheshti University, Tehran, Iran in 2011. His research interests include Nanoelectronics with emphasis on Emerging Technologies, Quantum-dot Cellular Automata, CNFET, Multi-Value Logic and Computer Architecture. He is currently is faculty of Computer Engineering, Department in Persian Gulf University Bushehr, Iran. He also is member of NQC Lab in Shahid Beheshti University, G. C., Tehran, Iran. received B.Sc. degree in computer engineering in 2008 from Shiraz University, also received his M.Sc. degree in computer architecture at Department of Computer Science and Research Branch of IAU, Tehran, Iran, in 2011. He is currently working degree in electrical engineering at the University of Central Florida, Orlando, USA. interests include Spin based computing Architectures, Reconfigurable Architecture, Arithmetic. He is a student member of IEEE.
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Arman Roohi Shiraz, Iran. He Engineering, toward the Ph.D. His research and Computer
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Hossein Khademolhosseini received B.Sc. degree in computer engineering in 2008 from Shiraz University, Shiraz, Iran. He also received his M.Sc. degree in computer architecture at Department of Computer Engineering, Science and Research Branch of Islamic Azad University, Tehran, Iran, in 2011. He is currently working toward the Ph.D. degree in computer architecture engineering at the Science and Research Branch of IAU. His research interests are computer arithmetic, photonic NoC and electronics with emphasis on QCA and VLSI.
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Shadi Sheikhfaal received her B.Sc. in computer hardware engineering from Ardebil Branch of IAU, Ardebil, Iran in 2012 and her M.Sc. in computer engineering, computer architecture from Science and Research Branch, IAU, Tabriz, Iran in 2014. She is currently a research assistant at School of Computer Science of IPM, Tehran, Iran. Her research interests include low power design and nanoelectronic circuit design with emphasis on Quantum-dot cellular automata.
Shaahin Angizi received his B.Sc. in Computer Engineering, Hardware from South Tehran Branch of IAU, Tehran, Iran in 2012 and his M.Sc. in Computer Engineering, Computer Systems Architecture from Science and Research Branch of IAU, Tabriz, Iran in 2014. He is currently working toward the Ph.D. degree in Computer Engineering at University of Central Florida, Orlando, USA. His research interests include high performance and low power VLSI designs and Nanoelectronics with emphasis on Spintronic and QCA. He is a student member of IEEE.
Keivan Navi received the Ph.D. degree in computer architecture from Paris XI University, Paris, France, in 1995 and the M.Sc. degree in electronics engineering from Sharif University of Technology, Tehran, Iran in 1990. He is currently a Full Professor in Faculty of Electrical and Computer Engineering of Shahid Beheshti University and also a senior member of IEEE. He is in charge of the Nanotechnology and Quantum Computing Laboratory (NQC Lab.). His research interests include Nanoelectronics with emphasis on CNFET, QCA and SET, Computer Arithmetic, Interconnection Network Design and Quantum Computing and cryptography.
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Ronald F. DeMara received the Ph.D. degree in Computer Engineering from the University of Southern California in 1992. Since 1993, he has been a full-time faculty member at the University of Central Florida where he is Professor and Computer Engineering Program Coordinator. His research interests are in Computer Architecture with emphasis on Evolvable and Resilient Hardware, on which he has published approximately 170 articles. He is a Senior Member of IEEE and has served on the Editorial Boards of IEEE Transactions on VLSI Systems, ACM Transactions on Embedded Systems, Journal of Circuits, Systems, and Computers, the journal Microprocessors and Microsystems, various conference program committees, and is currently an Associate Editor of IEEE Transactions on Computers. He received the Joseph M. Bidenbach Outstanding Engineering Educator Award in 2008, the highest educational honor from IEEE in the Southeast United States.