Towards the hierarchical design of multilayer QCA logic circuit

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Towards the hierarchical design of multilayer QCA logic circuit Bibhash Sen a,∗ , Anirban Nag b , Asmit De a , Biplab K. Sikdar c a

Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India School of Computing, The University of Utah, Utah, UT 84102, United States c Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology, Shibpur, India b

a r t i c l e

i n f o

Article history: Received 21 February 2015 Received in revised form 31 August 2015 Accepted 26 September 2015 Available online xxx Keywords: Quantum-dot Cellular Automata Multiplexer Radius of effect Multilayer design Hierarchical design

a b s t r a c t As a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises efficient digital design with high device density and low power dissipation in the future. This work targets the development of multi-layered architecture in the QCA framework with the goal to build an efficient methodology for QCA based digital logic design. A strategy for modelling, digital devices around QCA multiplexer is framed, which directs to the conception of complex digital circuits with high device density and low latency (i.e., more quick functioning). The proposed multilayer design also points to inherent aspects of radius of effect of QCA cells and the layer spacing in multilayer architecture. Minimum clock zone (2 clock) with high compaction (0.01 ␮m2 ) is achieved for the multiplexer designed in QCA framework. A heuristic approach to synthesize multilayer synchronized QCA logic circuit is also proposed. Experimental results illustrate significant improvements in design level in terms of circuit area, cell count and clock over that of conventional design approaches. © 2015 Elsevier B.V. All rights reserved.

1. Introduction Current CMOS-based architecture is on the verge of reaching the limit of feature size reduction. Its high power consumption also prevents the energy efficient realization of complex logic circuits at nano-scale. Also, downscaling of CMOS circuitry does not necessarily produce corresponding gains in device density [1]. Quantum-dot Cellular Automata (QCA), an emerging alternative nanotechnology [2], is introduced to create nano-scale devices with high compaction density [3], capable of performing computation at very high switching speed [4]. The small dimension of QCA cells causes QCA interconnects to shrink thereby increasing device density. One of the inevitable steps in systematic logic design is wirecrossing [5,6]. In the classic binary QCAs, wire-crossing is realized either considering rotated QCA cells in a wire (coplanar wire crossing) or with multilayer crossing. A coplanar crossing is susceptible to random external effects where as multilayer wire-crossing can be a promising alternative to it. Further, unlike present CMOS integrated circuits, where metal layers can’t perform any intelligent functions but to connect discontinuous sections of a circuit, an extra

∗ Corresponding author. E-mail addresses: [email protected] (B. Sen), [email protected] (A. Nag), [email protected] (A. De), [email protected] (B.K. Sikdar).

layer in the multi-layered QCA architecture can be used as the active component of the circuit [7]. To achieve a compact device density in QCA, the possibility of realizing multi-layered wire-crossings in QCA is identified in [1,7–10]. It enforces the need for provisioning the additional layer in QCA circuitry to support scaling at system level. Multi-layered wire crossing is an established concept in QCA literature which plays very important role in building basic blocks of logic design [5,11–16]. The work reported in [8] is indeed a direction towards the realization of multilayer design. It provides an alternate geometry of QCA cells in 3D and proposes a non-coplanar arrangement. Initially, a five input majority logic in multilayer is established in [17] to utilise its capability in synthesizing a compact multilayer adder. Multilayer sequential circuits in QCA is explored in [14]. Recently, an idea of two dimensional clocking-scheme for multilayer QCA is proposed in [18]. Also, a multi-layered configurable logic block (CLB) unit for field programmable gate arrays (FPGAs) is proposed in [19]. Fabrication of multilayer crossing has been investigated in [20] using magnetic QCA cells. The design is made in multiple layers which help to process information simultaneously, in different layers. The cell layout and timing constraints play a significant role in mapping a digital design to majority logic-based QCA circuit. However, such investigations are limited mostly to co-planner QCA layout. A few designs exist that utilize multilayered structure only to avoid crosstalk of wire-crossing in coplanar architecture. But the impact of multilayer in logic synthesis along with various design

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Fig. 1. (a) A QCA cell, (b) QCA cell with two different polarization, and (c) clocking.

parameters, like layer spacing, radius of effect and cell size etc., has not been taken into consideration yet. Thus, the growing research on physical characteristic of QCA demands a special design process of circuits that can address the above issues. All this factors motivate us to design an efficient multilayer QCA architecture with proper analysis of the different design constraints imposed by layered structure. A scheme for modelling digital devices around QCA multiplexer has been framed with the target to achieve high device density. The major contributions of this work can be summarized as follows: • Design of a cost effective multi-layered structure for a digital circuit, like multiplexer, is explored. • Use of different layer as active circuit component followed by robust wire crossing. • Impact of different inherent aspects of QCA, like layer separation limit and radius of effect on multilayer are explored for the first time in the literature. • An algorithm using binary tree is proposed to obtain the three layer synchronised QCA logic. • Finally, synthesis of complex logic circuit using the proposed multiplexer is investigated. The paper is organised as follows. Section 2 deals with preliminaries including a brief overview of QCA technology. Related works on this QCA architecture is explored in Section 3. The basics of multilayer design is covered in Section 4. The proposed multilayer design of QCA multiplexer is presented in Section 5. Stability of the proposed circuit is checked in Section 5.1. The heuristic approach to synthesize multilayer synchronised QCA logic circuit is explained in 6. In Section 7, different QCA circuits such as 4:1 multiplexer, D-latch, XOR-logic and a comparator are synthesized using 2:1 multiplexer. Discussion and conclusion are given in Section 9. 2. Preliminaries In QCA based design, a single device (QCA-cell) is used for the construction of all components of a circuit (computational elements and wires). The schematic diagram of a four-dot QCA cell is shown in Fig. 1. The cell consists of four quantum dots positioned at the corners of a square and contains two free

electrons [21]. A quantum dot is a region where an electron is quantum-mechanically confined (Fig. 1(a)). Coulombic repulsion will cause classical models of the electrons to occupy only the corners of the QCA cell, resulting either in polarization P = −1 (logic 0) or in P = +1 (logic 1) as shown in Fig. 1(b). Timing/synchronization in QCA is accomplished by the cascaded clocking of four distinct and periodic phases as shown in Fig. 1(c) [22]. In the first (switch) phase, the tunnelling barrier between two dots of a QCA cell starts to rise. This is the phase during which computation takes place. The second (hold) phase is reached when the tunnelling barriers are high enough to prevent electrons from tunnelling. In third (release) phase barrier falls from high to low. The final phase (relax) ensures there is no inter dot barrier and the cell remains unpolarized. Each cell has to pass through all of these clocking phases. 2.1. QCA logic gate The basic structure realized with QCA is the 3-input majority gate, MV(A, B, C) = Maj(A, B, C) = AB + BC + CA (Fig. 2(a)). The majority gate can also function as a 2-input AND or a 2-input OR by fixing one of the three input cells to P = −1 or P = 1 respectively. Although some 5-input majority gates or more complex 3-input gates exist, they are difficult to implement in a design. Inversion can be done in QCA within the wire with two different configurations as shown in Fig. 2(b). In [23], the constraints imposed by the radius of effect of each cell is described. It defines the distance d that can affect the operation of certain structures in QCA array. That is two in-line QCA cells interact if d = dN = w + s

(1)

w is the width (and height) of (square) cell, and s is the measure of separation between two consecutive cells (Fig. 2(e)). The other different radius of effects for nearest diagonal/next to neighbour is described in [23]. In QCA, two kinds of QCA wire-crossing are possible- coplanar (Fig. 2(c)) and multilayer (Fig. 2(d)). Coplanar wire-crossing in QCA requires cells of two different orientations, a 90◦ (× − cell) and a 45◦ (+ − cell) structure whereas multilayer wire crossing has no such strict orientation constraints. A multilayer crossover is quite straightforward from the design perspective and the signal connection is steadier. The probability of undesirable crosstalk between

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3

1

Input A

Ouput 0

0 Device cell

0 1

Input B

Input C

Fig. 3. Multilayer majority logic gate in [8].

Fig. 2. (a) Majority voter, (b) inverter, (c) coplanar wire-crossing, (d) multilayer wire-crossing, and (e) area under induced effect of majority cell.

any two coplanar crossing lines can be avoided by introducing multilayer wire-crossing. Also, in a coplanar crossing, there is a possibility of a loose binding of the signal which causes a discontinuity of signal propagation and there is the possibility of back-propagation from the far side constant input. So introduction of proper clock zones between the ‘×’-cells and the ‘+’-cells are required. This article considers multilayer wire-crossing. 3. Related work Different fabrication technologies [20,24–26] have been explored to implement QCA devices. The growing research on the physical characteristics of QCA demands cost effective design of QCA cell layout. Mapping a digital design to majority logicbased QCA circuit is controlled with the constraints imposed by QCA layout and timing [27]. In coplanar approach, the layout area of a complex circuit, involving considerable number of complex Boolean functions, becomes too huge to be practically acceptable in nano-scale arena. The problem of large effective circuit area (mostly wire crossing and large number of logic gates) can be reduced by the introduction of multilayer architecture. Although, a two layer approach is explored for QCA ternary logic [9] but multilayer approach for classic QCA (binary) is yet to be explored. A few research works considered multilayer architecture only for its advantages in wire-crossing [5,12,13,28]. Due to the unique clocking scheme (four phase clocking zone) used in QCA, its became very critical issue to minimise the clock zone for cost effective multilayer design. Recently, an alternative multilayer implementation of QCA and its fabrication issues have been addressed in [8], where the authors have discussed the implementation of non-coplanar QCA devices as an alternative to conventional coplanar structures. It further proposes that this design “simplifies fabrication significantly” [8]. It has been shown that fabrication of non-coplanar devices, although challenging, can be made possible using bi-planar cells as shown in Fig. 3. In [8] it has been shown that non-coplanar devices, synthesized using a combination of facing cells and edge-wise cells, are more efficient in implementing advanced logic functions in terms of area. Recently, the implementation of a QCA framework for a designing a cost effective coplanar multiplexer is explored in [29]. The performance of the proposed multiplexer in [29] is compared with

all the previous popular QCA multiplexers. But the idea of treating each layer as the active layer for function realization, unlike CMOS, has not been investigated (which is of primary interest to us in this paper). Multi-layered wire crossing is an established concept in QCA literature [17–19,30,16]. Initially, a five input majority logic in multilayer is established in [17] to utilise its capability in synthesizing a compact multilayer adder. In [16], the concept of multilayer wire crossing has been extended to design logic gates using a 5input majority gate in a multilayer. Another five input majority gate design in five layers for multi-layered circuit designs and verification of clocking scheme using 4:1 MUX and full adder designs is established in [18]. A multi-layered configurable logic block (CLB) unit for field programmable gate arrays (FPGAs) is proposed in [19] which is made in multiple layers to process information simultaneously, in different layers. However, the feasibility of fabrication for all those attempts in QCA is yet to be experimentally supported. Possible promising implementation of multi-layered wire crossing is proposed in [1,10]. But, no such systematic design methodology addressing the multilayer constraints to synthesize a QCA circuit is established (which is of prime interest of this work). 4. Multilayer design This section introduces the proposed multi-layered architecture of digital design in QCA framework. Initially, the effectiveness of multilayer design is analysed with a majority voter (Fig. 4(a)). A majority voter has 3 input cells and an output cell. In multilayer, it can be realized by placing these cells in vertically above and/or below the device cell. The basic coplanar structure of the 3-input majority gate has been tweaked to implement it in multilayer. It realizes different functions based on the position of input and C

A

B

B

A

M

B M = AB + BC +CA

M

C M = AB + BC’+ C’A

(a)

(b)

A

C

M M = ( AB + BC + CA )’ (c)

B

B

layer 3 A layer 2

A

M

A

C

A’ layer1 A

C M = AB’ + B’C’ + C’A (d)

M M = ( AB’ + B’C + CA )’ (e)

(f)Multilayer effect on a cell

Fig. 4. Multilayer design and its effect.

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Fig. 5. QCA implementation of proposed 2:1 multiplexer and its simulation result.

output cells. The Fig. 4(b) and (c) shows the implementations in 2-layer architecture. On the other hand, Fig. 4(d) and (e) shows the implementations in 3-layer architecture. The multilayer majority voter has more device density (2 × 3/1×3 cell size) compared to that of coplanar majority voter (3 × 3 cell size). A negation of the transferred logic value occurs during switch from one layer to the other (Fig. 4(f)). When designing a wire crossing, this has no adverse effect as eventually the transferred logic value will be negated when received at the original layer again. However, when processing is to be performed on different layers, this negation effect plays a vital role in designing the circuit.

5. Design of an efficient 2:1 QCA multiplexer ¯ where A The output of a 2:1 multiplexer is, F = A.S + B.S, and B are the two data inputs and S is the selection line. The majority gate representation of this multiplexer is, F = ¯ B, 0), 1). Here, 3 majority gates and 1 M3(M1(S, A, 0), M2(S, inverter are required to realize the 2:1 multiplexer (Fig. 6). Lemma 5.1. The minimum number of clock zones required to realize a 2 × 1 multiplexer using QCA majority primitives is two. Proof. The majority gate representation of 2:1 multiplexer func¯ B, 0), 1), i.e., it needs three majority tion is F = M3(M1(S, A, 0), M2(S, gates and one inverter. One clock zone is required for the majority gate to implement OR function. There are two other majority gates for which atleast one more clock zone is required for stable output. Buffer cells are added in between the input cells/constant cells and the device cell such that the signal propagates through equal number of cells. This would ensure correct voting of the three signals at the device cell of the AND gates in presence of a single clock. Since the signals driven by the inputs and constants are in one direction, the states of intermediate cells in the same clock zone cannot be affected by both the inputs and outputs. Hence at least two clock zones are required for the multiplexer.䊐

Therefore, a 2-to-1 multiplexer is proposed here with the target of minimum clock zones as stated above. The top view and different cell layers of the 3-layer model of the multiplexer are shown in Fig. 5(a). Layer stacking from top to bottom in Fig. 5(a) is Layer 3, Layer 2 and Layer 1. M1 consists of cells 2, 3, 4, 7 and 12 and are arranged as in Fig. 4(b). M2 consists of cells 14, 17, 18, 19 and 20 and are arranged as in Fig. 4(a). M3 consists of cells 4, 5, 6, 8, and 13 and are arranged as in Fig. 4(b). The Input line A (cell 1) and Selection line S (cell 9) are placed in Layer 1, whereas the Input line B (cell 16) is placed in Layer 2. The Output F (cell 6) is obtained from Layer 1. Cell 21 (in Layer 2) and cell 22 (in Layer 3) are constant inputs of −1.00 polarization, and cell 23 (in Layer 3) is a constant of +1.00 polarization. Cells 4, 5, 6, 8 and 13 are in Clock Zone 1, while the rest of the cells are in Clock Zone 0. Similarly, a 4-layer architecture of QCA 2:1 MUX is synthesized and its top view and layers are shown in Fig. 5(b). The proposed designs are verified in QCADesigner [31] simulator version 2.0.3. Fig. 7 displays simulation result of 3-layered 2:1 QCA MUX. It can be seen that when S is 0, input B appears at the output and when S is 1, input A is selected. The output appears in cell 6, which is in clock zone 1, i.e., the correct output is obtained only when clock 1 undergoes transition. The design specifications and simulation settings are given in Table 2. Table 1 shows a comparison between coplanar approach and multilayer approach for designing a 2:1 multiplexer. It gives an account of the number of cells used in the designs, the grid area

B Sel

M1 1

−1

M3

F

M2 A Fig. 6. Multiplexer realised with majority voter.

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5

max: 1.00e+000 A min: -1.00e+000 max: 1.00e+000 S min: -1.00e+000 max: 1.00e+000 B min: -1.00e+000 max: 9.54e-001 F min: -9.55e-001 max: 9.80e-022 CLOCK 0 min: 3.80e-023 max: 9.80e-022 CLOCK 1 min: 3.80e-023 0

495

990

1485

1980

2475

2970

Fig. 7. Simulation result of proposed 2:1 multiplexer.

Table 1 Comparison of recent 2:1 multiplexer designs. Design

Cell count

Matrix

Clock zones

Area (␮m2 )

In [32]’07 In [33]’08 In [34]’08 In [35]’08 In [36]’11 In [29]’12 Proposed 3 layer arch. Proposed 4 layer arch.

46 35 36 67 27 19 23 22

13 × 11 13 × 8 13 × 8 18 × 14 9×8 8×6 6×6 5×6

4 4 4 4 3 3 2 2

0.06 0.04 0.04 0.10 0.03 0.02 0.01 0.01

Table 2 Specifications and simulation settings for 2:1 multiplexer designs. Specifications Area Matrix Cell count Cell size Dot diameter Cell separation Simulation engine Radius of effect Layer separation

3 Layer arch.

4 Layer arch.

11,564.00 nm2 5×6 22 18 nm × 18 nm 5 nm 2 nm Coherence Vector (Euler’s Method) 65 nm 11.5 nm

(i.e. the cell matrix within which each layer is bounded), the number of clock zones used, and the chip area (in ␮m2 ) of the total grid size in each layer. The chip area is translated based on the grid area considering a default cell size of 18 × 18 nm2 and coplanar inter-cell separation of 2 nm in all cases. The comparison among the coplanar, 3-layer and 4-layer architectures clearly shows that the multilayer architecture of 2:1 multiplexer leads to high device density (50% improvement). Since each clock zone used in a design introduces a delay of 0.25 * (Time Period of the Clock), it is observed that the performance of the proposed multi-layered design is significantly more than the coplanar design due to less delay (33.33% improvement) as it requires only two clock zones (the least number of clock zones). No such coplanar multiplexer with two clock zones is found till date.

2

13,924.00 nm 6×6 23

5.1. Stability of proposed multilayer architecture Polarization at the output signifies the stability of a QCA circuit. For this purpose the proposed design is verified with different cell size and radius of effect and its polarization at the output is reported in Table 3. It shows that the proposed 3-layer and 4-layer architectures are more stable configurations, giving polarization values

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Table 3 Polarization in proposed 2:1 multiplexers.

Function

# Layer

I1

Design

Cell size

RoE (nm)

LS (nm)

Polarization

Three layer arch.

18 × 18 22 × 22 26 × 26 30 × 30

80 80 80 80

12 14 16 18

0.951/−0.953 0.937/−0.944 0.922/−0.932 0.905/−0.919

18 × 18 22 × 22 26 × 26 30 × 30

65 65 65 65

11.5 13.5 15.5 17.5

0.943/−0.957 0.930/−0.947 0.916/−0.935 0.894/−0.923

Four layer arch.

Circuit

No

T1 I0

O

M1J(I0,I1,I2,O) =I0I1+I1I2+I0I2

1

M2J1(I0’,I1,I2,O) =I0’I1+I1I2+I0’I2

2

M2J2(I0,I1,I2,O’) =(I0I1+I1I2+I0I2)’

2

M3J1(I0’,I1,I2’,O) =I0’I1+I1I2’+I0’I2’

3

M3J2(I0’,I1,I2,O’) =(I0’I1+I1I2+I0’I2)’

3

I2 I0

T2 I0

O I2 O

RoE, radius of induced effect; LS, layer separation.

T3 Table 4 Fault tolerance of proposed 3-layer 2:1 MUX under single cell displacement defect.

I0

I0 I2

Cell

Left

Right

Up

Down

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

2.1 2.5 0.6 5.0 1.0 6.6 2.3 2.0 6.7 4.3 2.8 5.8 5.4 2.1 7.1 1.0 3.5 0.6 1.9 2.9 4.3 6.2 7.7

14.6 2.7 1.8 6.7 1.2 1.3 5.0 2.1 14.7 2.1 2.8 3.7 5.1 2.5 3.9 1.7 1.1 1.1 7.6 2.2 4.3 6.2 7.7

4.2 3.1 2.1 2.8 0.8 4.4 2.1 2.0 4.0 3.8 3.5 5.4 5.7 1.3 3.8 3.1 1.8 4.6 4.3 1.0 1.4 6.2 7.8

4.3 2.5 2.4 1.4 1.8 3.0 7.0 2.7 6.0 1.1 0.8 4.4 5.2 2.4 7.0 3.1 2.9 0.5 3.5 1.9 2.2 6.2 7.7

greater than 0.9. These are obtained for an optimal radius of effect of 80 nm for the 3-layer model and 65 nm for the 4-layer model. The layer separation is set at an optimal value within the available range for that particular cell size. The cell size is varied from 18 nm × 18 nm to 30 nm × 30 nm. The positive value of polarization represents the positive peak while the negative value represents the negative peak polarization of the output cell. 5.2. Fault tolerance of 3-layer multiplexer under cell displacement Cell displacement errors are also quite frequent during fabrication of a design. In such cases, a QCA cell is misplaced from its original position. Hence better design strategies need to be adopted to make the design fault tolerant. A detailed simulation based fault tolerance of the cells with respect to displacement from their original positions is evaluated in Table 4. The values are obtained for the 3-layer model with the default 18 nm × 18 nm cell technology

I2

T4 I1

O

I0 O

T5 I1

I2

I0

Fig. 8. QCA majority logic for multilayer circuit.

and coplanar inter-cell separation of 2 nm in each layer. In Fig. 5(a), the cells 3, 5, 18 (the device cells of the majority gates) are vulnerable to displacement, whereas cells like 1, 2, 9, 12, 13, 15, 22, 23 (not integrated with the inner part of the design) are more tolerant to displacement. For example, when cell 3 is shifted more than 0.6 nm to the left, the design produces erroneous output. On the contrary, cell 22 can be shifted to a maximum displacement of 6.2 nm without affecting the output. Although fault tolerance for displacement in each direction is individually computed in Table 4, fault usually does not occur in only one direction. Multi-directional fault analysis is a complex process, and out of the scope of this work. 6. Multilayer (three) synchronization of QCA logic circuit using binary tree The design elements used to synthesize multilayer circuits are coplanar majority voter (Fig. 8(T1)), two layer majority voter 1 (Fig. 8(T2)), two layer majority voter 2 (Fig. 8(T3)), three layer majority voter 1 (Fig. 8(T4)) and three layer majority voter 2 (Fig. 8(T5)). In the following paragraph, we describe synthesis of a function following Algorithm 1. ¯ Example 1. Input expression: F = B¯ C¯ + ABC¯ + ABC. Since the expression is on reduced SOP form, so we can directly apply Algorithm 1 to synthesize the equivalent QCA logic circuit.

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Algorithm 1.

Generation of multilayer synchronised QCA circuit

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Algorithm 2.

Initial Formulation

Procedure routingIO() C

B’C’ M3J1 −1

B

A

A’B M2J1 −1

B’C’

A

C

B

A’B B

B (a)

(d)

A’B

A −1

−1

AB

A’BC

M1J

AB A

B

B

A’BC

A

+1 M3J1

(A’+B’)’

A’B

M1J

C

M3J1

B

C

((A’B)’+C’) A’B

C (e) AB

AB

C

+1

(b)

ABC’

C

M2J1

ABC’ −1

(c)

Fig. 10. Formation of sub-trees in central processing zone.

Algorithm 3.

Procedure clockSync()

The graph G created in Step 2 is shown in Fig. 9. Here the circular nodes and associated links form the binary tree B and the square nodes together with B form the connected graph G. The centralPro¯ BP2 (with cessing section thus has 3 sub-trees BP1 (with node B¯ C), ¯ ¯ nodes ABC¯ and AB) and BP3 (with node ABC and AB).

.

B’C’+ABC’ +

. B’C’

.

ABC’

. AB

BP1

A’BC A’B

.

BP2

A C B Fig. 9. Binary tree with associated link.

BP3

Central Processing

+ B’C’+ABC’+A’BC

Input routing

Output routing

F

In the centralProcessing section, initially the sub-tree BP1 for the node B¯ C¯ is formulated (Fig. 10(a)). Since both inputs of the AND gate are complemented inputs, the inversions are inherently incorporated in the inputs by using multilayer majority voter M3J1. The MV formulation is done as (B at layer 1, C at layer 3, −1 at layer 2, O/P at layer 2). Thus the output B¯ C¯ is obtained. ¯ initially the Next, to create the sub-tree BP2 for the node AB C, tree corresponding to AB is created (Fig. 10(b)). For formulation of AB, two options are available. (i) Using M1J as A at layer 1, B at layer 1, −1 at layer 1, O/P at layer 1. (ii) Using M3J1 as A at layer 1, B at ¯ at layer 1. The second option is also taken layer 3, +1 at layer 2, O/P into consideration since it is a multilayer design. However, in the ¯ B. The second option, we obtain the complemented output i.e. A + final sub-tree for the node is created by adding the input C to the tree (Fig. 10(c)). It is formulated using M2J1 as AB at layer 1, C at layer 2, −1 at layer 1, O/P at layer 1. ¯ initially Similarly, to create the sub-tree BP3 for the node ABC, ¯ is created (Fig. 10(d)). It is formulated the tree corresponding to AB using M2J1 as A at layer 1, B at layer 2, -1 at layer 2, O/P at layer 2. The final sub-tree for the node is created by adding the input C to the tree (Fig. 10(e)). Here, two options are also available. (i) Using ¯ at layer 1, C at layer 1, -1 at layer 1, O/P at layer 1. (ii) M1J as AB ¯ at layer ¯ at layer 1, C at layer 3, +1 at layer 2, O/P Using M3J1 as AB 2. The second option is also taken into consideration since it is a multilayer design. However, in the second option, we obtain the ¯ complemented output i.e. A BC. Now, to fix the input variables in layers, occurrence of each input variable is counted in each layer, according to our temporary node formulations in Step 2. Input variable A occurs three times in layer 1, so input layer of A = 1, i.e., input A is placed in Layer 1. Input variable B occurs two times in Layer 1, once in Layer 2 and once in Layer 3, however, input variable B is placed to layer 3 because of input B occurs maximum number of times in Layer 1, and Layer 3 and Layer 1 are interchangeable [condition (ii)]. By selecting Layer 3 for Input B, another advantage is achieved - the 3 Layer M3J1 can easily be used to formulate the node AB. Input variable C occurs twice in Layer 3, once in Layer 2 and once in Layer 1, however, input C is placed in Layer 1 like A input. Another reason for choosing Layer ¯ B and C cannot be in the same layer, and 1 for C is that for node B¯ C, B has already been fixed at Layer 3. Optimization in routing is done by reformulating the majority voters of nodes in Step 2 according to the layer fixed for the inputs in Step 3. The reformulation is done as follows – For sub-tree BP1, node B¯ C¯ is formulated using M3J1 as B at layer 3, C at layer 1, −1 at

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B. Sen et al. / Journal of Computational Science xxx (2015) xxx–xxx Table 5 Multilayer synthesis of 13 standard benchmark function.

Re−formulated nodes A’BC

ABC’ AB

C C

A

A

B

ABC’

+1

layer 2

−1

B

B

−1

layer 3

A’B layer 3

B A

+1

A

layer 1

C

diagonal not (A’+B’)’

diagonal not

A

Sl No

Function F

Layer

Clock zone

MVs layer routing

1

ABC

3

2

2 3

AB ABC+AB’C’

1 3

1 4

4

ABC+A’B’C’

3

4

5

AB+BC

3

3

6

AB+A’B’C

3

4

7

3

5

8 9

ABC+A’BC’+ AB’C’ A AB+BC+CA

1 3

1 5

10

AB+B’C

3

3

11

AB+BC+A’B’C’

3

5

12

AB+A’B’

3

3

13

ABC+A’B’C+ AB’C’+A’BC’

3

6

M3J1, M2J1 L1:A, C, o/p, L3:B M1J L1:A, B, C, o/p M3J1, M2J1:4 L1:B, C, o/p, L3:A M3J1:2, M2J1:3 L1:B, C, o/p, L3:A M3J1:2, M1J:1 L1:A, B, C L3:o/p M3J1:2, M1J:2 L1:A, L3:B, L2:C, o/p M3J1:2, M2J1:4, M1J:2 L1:A, L2:B, o/p, L3: C M1J:1 L1:A, o/p M3J1:2, M2J1:1, M1J:2 L3:A, C, o/p, L1:B M3J1:1, M2J1:1, M1J:1 L3:A, L1:B, l2: o/p, C M3J1:3, M2J1:1, M1J:2 L1:A, C, L2: o/p, L3: B M3J1:2, M1J:1 L3:A, L1:B, L2:o/p, C M3J1:2, M2J1:4, M1J:5 L3:A, L1:B, L2: C, o/p

layer 2

A’

layer 1 C

9

(b)

(a)

Fig. 11. Re-formulated node optimizing layer for input.

layer 2, O/P at layer 2. For sub-tree BP2, (i) Node AB is formulated ¯ at layer 2, (ii) using M3J1 as A at layer 1, B Layer 3, +1 at layer 2, O/P Node ABC¯ is formulated using M2J1 as AB at layer 2, C at layer 1, −1 at layer 2, O/P at layer 2 (See Fig. 11(a)). For sub-tree BP3, (i) Node ¯ is formulated using M2J1 as A at layer 2, B at layer 3, −1 at layer AB ¯ ¯ at 3, O/P at layer 3, (ii) Node ABC is formulated using M3J1 as AB ¯ at layer 2. In sub-tree BP2, the layer 3, C Layer 1, +1 at layer 2, O/P ¯ of node AB obtained in Layer 2 is transferred to inverted output AB node ABC¯ by initially making a diagonal NOT in Layer 2 as shown in Fig. 11(b). A new binary tree BO is constructed using the nodes in the outputRouting section of Graph G. In the tree BO, node B¯ C¯ + ABC¯ is formulated using M1J as B¯ C¯ at layer 2, ABC¯ at layer 2, +1 at layer ¯ 2, O/P at layer 2, and node B¯ C¯ + ABC¯ + ABC is formulated using M1J ¯ at layer 2, +1 at layer 2, O/P at layer as (B¯ C¯ + ABC¯ at layer 2, ABC ¯ ¯ obtained from output of sub-tree BP3 2). The inverted output ABC in Layer 2 is initially inverted using a diagonal NOT and then fed as input to the final majority gate formed from the root node of BO. Step 6: In the inputRouting section, the following connectivity are established using QCA wires /wire-crossings between the input cells and nodes in the tree B: For input variable A in Layer 1, (i) to majority input for node AB ¯ in Layer 2 (diagonal in Layer 1. (ii) to majority input for node AB NOT, then layered NOT). For input variable B in Layer 3, (i) to majority input for node B¯ C¯ in Layer 3. (ii) to majority input for node AB in Layer 3. (iii) to ¯ in Layer 3. majority input for node AB For input variable C in Layer 1, (i) to majority input for node B¯ C¯ in Layer 1. (ii) to majority input for node ABC¯ in Layer 1. (iii) to major¯ ity input for node ABC in Layer 1. The corresponding schematic diagram after input routing and central processing is shown in Fig. 12. The clock zones in the design are established as follows- Clock zone 0 → Inputs cells A, B and C, and associated wires from them; Clock zone 1 → Cells of majority voter formed from node AB; Clock ¯ ABC ¯ and zone 2 → Cells of majority voters formed from nodes B¯ C, ¯ Clock zone 3 → Cells of majority voters formed from nodes ABC;

¯ Clock zone 0 → Cells of majority voter formed B¯ C¯ + ABC¯ and ABC; ¯ from node B¯ C¯ + ABC¯ + ABC and output cell F. Experimentation : To evaluate the performance/effectiveness of QCA circuits synthesis, thirteen 3-variable standard functions [37] are considered as QCA logic benchmarks. These functions cover such issues that increase the complexity of logic design. The thir3 teen standard functions represent all 256 (22 ) 3-variable Boolean functions. To determine the standard functions, we follow the cube representation of Boolean functions as stated in [38]. A logic gate that can effectively implement the thirteen standard functions can be considered as effective for realization of all the 3-variable Boolean functions as well as for digital logic implementation. The effectiveness of the proposed algorithm is established by synthesizing the 13 standard functions as presented in Table 5. ¯ as shown in the 2nd For function 6, the expression is F = AB + A¯ BC column of Table 5. The corresponding expression tree can be constructed as shown in Fig. 13. The nodes A¯ B¯ and AB are synthesized ¯ are synthesized using M1J. using M3J1, and nodes A¯ B¯ and AB + A¯ BC Thus number of M1J used is 2 and number of M3J1 used is 2, as shown in the 5th column of Table 5. Also, the inputs are fixed as A in Layer 1, B in Layer 3 and C in Layer 2, and the output F is obtained at Layer 2, as in the 5th column. The circuit is synthesized in 3 Layer due to the use of M3J1 (which is in 3 Layer). It is shown in column 3 of the Table 5. Number of clock zones required, as evident from the expression tree, is 4 as shown in the 4th column of the Table 5. Thus it is evident that the 13 standard functions can also be synthesized using multilayer, using the proposed algorithm; but the issue of optimality (clock zone) is not considered in this case.

C A’ A

+1

layer 3 A’BC

layer 2

A M2J1

(AB)’ −1

ABC’

+1

M3J1

B’C’

M3J1

−1

AB

A’B

AB+A’B’C + Clock 3 A’B’C

AB

Fig. 12. Schematic diagram of multilayer synchronised QCA logic circuit.

Clock 2

A’B’

layer 1

layer 1

layer 2

−1

M3J1

B

M2J1

layer 3

F

A

B

Clock 1 C

Clock 0

Fig. 13. Multilayer synchronised standard benchmark function.

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Fig. 14. QCA implementation of different high level logic circuits with proposed 3-layer 2:1 MUX.

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B. Sen et al. / Journal of Computational Science xxx (2015) xxx–xxx Table 6 Comparison of recent 4:1 multiplexer designs. Design

Cell count

Matrix

Clock zones

Area (␮m2 )

In [33] In [39]

124 154

30 × 17 16 × 20

8 4

0.20 0.13

In [36] Proposed 3 layer 2:1 MUX

95 103

19 × 16 13 × 15

7 7

0.12 0.08

Proposed 4 layer 2:1 MUX

94

11 × 15

6

0.07

Table 7 Specifications of implemented high level logic circuits. Area (nm2 )

11

[43]. A five input majority logic is investigated for cost effective realization of multilayer structure in [14,41,18]. The fabrication issues related to the QCA realization in room temperature are discussed in [40]. At this point, designing QCA is an “in-principle” activity meant to explore what might be possible if and when the fabrication issues are overcome [44]. Hence, this work only focuses on the architectural issues associated with multilayer circuit without considering fabrication issues. So far as our current work is concerned, we propose a generic model around multilayer QCA which can be suitable for molecular QCA as well as semiconductor QCA [45] since proposed QCA model use columnar regions, where the phase difference of the clock signals for adjacent cells having different clock zone is 90o [46]. The experimental validation is made out in the framework of QCADesigner which mimics QCA feature that depends on local field coupling [47,48].

Circuit

Cell count

Matrix

Clock zones

4:1 Multiplexer (Fig. 14(a)) D Flip-Flop (Fig. 14(b)) XOR Logic (Fig. 14(c)) 1-bit Comparator (Fig. 14(b))

103

13 × 15

7

76,884

38

7×7

4

19,044

9. Conclusion

28

6×7

3

16,284

111

13 × 15

7

76,884

In this work a multilayer architecture of 2:1 multiplexer around QCA (Quantum-dot Cellular Automata) is introduced considering its primitives (majority voter). The resulting design takes only two clocking zones covering an area of 0.01 ␮m2 . The proposed work is one of the first attempts to design and evaluate feasible logic units on multilayer QCA nanotechnology. The fundamental issues related to multilayer architecture are addressed for all aspects of the design. Its robustness issue is further analysed for cell-displacement and variation of radius of effect with different layer spacing. To obtain the multi-layered synchronised QCA logic circuit an algorithm is also developed. The proposed hierarchical algorithm will help automate the process of design within the constraints imposed by multilayer in the QCA and a cost effective three layer structure of a given Boolean function is synthesized. The effectiveness of the proposed algorithm is further established by synthesizing 13 standard benchmark functions. The usefulness of the proposed design is further analysed with the implementation of efficient 4:1 MUX, D-Flip-Flop, XOR and 1-bit Comparator in QCA.

7. High level logic synthesis Design capability and flexibility of the proposed model is analysed with synthesizing high level logic circuits using the 3-layer 2:1 MUX. A 4:1 multiplexer is synthesized using 3 modules of the proposed 2:1 MUX as shown in Fig. 14(a) which enhance the modularity. A comparison of 4:1 multiplexer with existing designs is shown in Table 6. The robustness of the proposed model is further analysed by implementing D Flip-Flop (Fig. 14(b)), XOR (Fig. 14(c)) and 1-bit Comparator (Fig. 14(d)). Table 7 lists the design specifications of the implemented circuits. In the 4:1 Multiplexer, access to selection line 1 is inconvenient, but can be achieved from higher layers. The D Flip-Flop is implemented replacing the selection line of the multiplexer with Clock signal of a D Flip-Flop. The output is transferred to line B using a feedback loop, whereas the D input is fed to the design from line A. The constant cell (polarity −1.00) in Layer 2 has a much stronger signal than the feedback wire of the majority gate. Hence, it must be shifted down 0.2 nm or more from its original position. While implementing the XOR gate, the inputs to line A and B are fed from a single signal source A, whereas the selection line is replaced with ¯ + AB¯ can be achieved. The ComB such that the logic function AB parator is constructed using 3 modules of 2:1 MUX, evaluating <, > and = respectively. 8. Discussion Recent research suggests that magnetic QCA (MQCA) and molecular QCA can be operated at room temperature [11,40]. The technology for assembling room temperature EQCA operation is awaited. However, if the cell size is reduced to molecular scales, room temperature EQCA operation can be attained [40]. The issue is live both in mono-layer as well as multilayer QCA design. The QCA paradigm is flexible; the principle of local field coupling of identical cells of EQCA can be extended to arrays of coupled nanomagnets [20,40]. The same also can be translated to electrostatic QCA architecture using the concept of building blocks via radius of effect metric [40]. The investigation is on towards the design of multilayer architecture around QCA [14,41,18,19,40,20,42]. A model for synthesizing a multi-layer QCA majority logic is, however, reported in

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