Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers

Computers and Electrical Engineering 45 (2015) 42–54

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Computers and Electrical Engineering journal homepage: www.elsevier.com/locate/compeleceng

Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers q Bibhash Sen a,⇑, Mrinal Goswami a, Subhra Mazumdar a, Biplab K Sikdar b a b

CSE Department, NIT, Durgapur, India CST Department, IIEST, Shibpur, India

a r t i c l e

i n f o

Article history: Received 15 May 2014 Received in revised form 4 May 2015 Accepted 4 May 2015

Keywords: Quantum-dot Cellular Automata (QCA) QCA multiplexer Fault tolerant QCA circuit Configurable logic block (CLB)

a b s t r a c t With the rapid advancement in very large scale integration (VLSI) technology, it is the utmost necessity to achieve a reliable design with low power consumption. The Quantum dot Cellular Automata (QCA) can be such an architecture at nano-scale and thus emerges as a viable alternative for the current CMOS VLSI. This work targets design of logic module in QCA. It reports a modular design methodology to build the fault tolerant 2n :1 multiplexer with optimized wire-crossings, delay and power consumption. A 2:1 QCA multiplexer is proposed as the basic logic module that in turn is utilized to synthesize 4:1 and 8:1 multiplexers. It shows significant achievement in terms of clock speed (36%), wire-crossing (58%), fault tolerance (77.62%) and power consumption over the existing designs. The effectiveness of proposed multiplexer is further established through synthesis of configurable logic block (CLB) for field programmable gate arrays (FPGAs). Ó 2015 Elsevier Ltd. All rights reserved.

1. Introduction Downscaling of current CMOS devices beyond a certain limit is not feasible as it introduces an anomalous quantum behaviour in nano-scale level. Quantum-dot Cellular Automata (QCA), an emerging nanotechnology, is considered to be a potential alternative to the CMOS technology and provides solution to the fundamental limitation of CMOS. The primary advantage of QCA is the high device density and the computing speed at nano-scale era [1]. Most of the QCA designs, realized today, follow coplanar wire-crossing only. But the coplanar wire-crossing is highly susceptible to random external effects and cross-talk [2]. The multiplexer plays key role in recognizing boolean function and in circuit designs, such as carrying out of a field programmable gate array (FPGA), controlled logic block (CLB) and memory circuits designs. An evolutionary approach is investigated in [3] to realise a modular 2n to 1 multiplexer using the elementary building blocks like AND and OR-block. But the use of delay blocks and the extra interface circuits in that design add high circuit delays and complexity. Further cascading of two separate modules of lower order multiplexer can’t be utilized while synthesizing the higher order multiplexer. Moreover, the reliability issues related to fault tolerance and the optimization of a power consumption in a modular multiplexer are not addressed properly in the literature. The above factors demand trade-off between a modular design with less wire-crossing and its reliability associated with the fault tolerance as well as the power consumption. In this context, this work proposes a modular design approach for QCA q

Reviews processed and approved for publication by the Editor-in-Chief.

⇑ Corresponding author. Tel.: +91 3432754237.

E-mail addresses: [email protected] (S. Mazumdar), [email protected] (B.K Sikdar). http://dx.doi.org/10.1016/j.compeleceng.2015.05.001 0045-7906/Ó 2015 Elsevier Ltd. All rights reserved.

(B.

Sen),

[email protected]

(M.

Goswami),

[email protected]

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

logic block (CLB). It is designed around the modular multiplexer, in produced in this work, that can be used for realizing the basic boolean functions. The reliability of proposed designs are established the power estimation model. The salient feature of this work is as follows:  A modular QCA multiplexer module is designed and its effectiveness in realising higher order 2n :1 multiplexers ðn P 2Þ, just by cascading, is explored.  Performance analysis of the proposed are design in terms of wire-crossings, delay and area are reported.  Reliability of a QCA design is evaluated following the power estimation model and the fault tolerance capability.  A control logic block (CLB), based on the proposed 2:1 multiplexer, is designed that can be used to realize various boolean logic functions. The rest of the paper is organized as follows: Section 2 introduces the QCA. In Section 3, a brief review on the work related to modular multiplexer is reported. T design of proposed modular multiplexer is detailed are in Section 4. Power consumption and fault tolerant capability of the multiplexer are estimated in Sections 5 and 6 respectively. In Section 7, a CLB is synthesized around the proposed modular multiplexer. Section 9 concludes the paper. 2. Preliminaries A square shaped QCA cell consists of four quantum dots (Fig. 1(a)) at its four corners. In the dots, electrons are quantum– mechanically confined [1] and in standard fault-free QCA cell, there are two electrons. The electrons occupy opposite corners of the cell due to coulombic repulsions, and as such give rise to two stable configurations with polarization P ¼ 1 (logic ‘0’) and P ¼ þ1 (logic ‘1’), Fig. 1(b) [1]. A QCA cell, when flipped from logic state 1 to 0, there is no actual discharging of the capacitor as in conventional CMOS since the states 1 and 0 are determined by the position of electrons in the QCA cell. Further, the propagation of polarization along the cells is due to interaction of the electrons in adjacent QCA cells. Four distinct and cascaded clock phases are used to synchronise the QCA cells [1], as shown in Fig. 1(f), for the propagation of information (polarization). Clocking not only controls the information propagation but also provides the required power in a QCA circuit. The basic QCA structure is the majority voter which can be described by the function MV(A, B, C) = Maj(A, B, C) = AB + BC + CA (Fig. 1(c)). If required, And/Or gates can be derived from the majority voter by setting one of its inputs to a constant (1)/(+1). Inverters in QCA can be realised in two different ways as shown in Fig. 1(d). Furthermore, a wire-crossing can be realised either as coplanar or as multilayer. Coplanar wire-crossing requires 45 (+-cell) rotated cells with 90 (-cell) cells shown in Fig. 1(e). A very few attempts are made to realize multilayer wire-crossing due to its fabrication constraints. 3. Related work

Quantum well

Junction Tunnel

Binary ’0’ P = −1 Localised Electron Binary ’1’ P = +1

(a)

45 degree orientation

Tunnelling Potential

90−degree orientation

Several attempts have already been made to design efficient logic circuits around QCA multiplexers. A modular design methodology is first proposed in [3] to construct the 2n :1 multiplexers. In such a design, AND, OR, and delay (modular)

A A B F C

B

Maj

F = AB + BC + CA C

(b)

(c)

B

Hold

Switch

Relese

’X’ Cell

Input A

Output A A’

F

Relax

A T/4

’+’ Cell

T/2

3T/4

T

A’ A

Output

Input B

(d)

(e)

(f)

Fig. 1. QCA basics: (a) Quantum cell. (b) Quantum-dot cell with two different polarizations. (c) Majority logic gate. (d) Inverters. (e) Wire-crossing. (f) Clocking.

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

blocks have been used. However, due to a lot of delay blocks and additional interface logic, the circuit delay and complexity become unacceptable. The number of delay blocks and additional interface, including the costly wire-crossings, are increased with the increase in order of multiplexer. A novel attempt to design multiplexer in QCA is made in [4] to overcome the inevitable problem of coplanar wire-crossing in QCA. It uses the single distribution network. The separation of signal distribution network from the combinational logic gates improves the system performance at the cost of clock cycles as well as complex design layout with huge wire-crossings. However, the reliability issue in all such attempts fails to desire the high fault tolerant as well as energy efficient logic circuit. 4. The proposed architecture of multiplexers An initial attempt to design an efficient multiplexer is reported in [5]. It assumes three clock zones. In order to make it more efficient with less delay, we propose a design involving only two clock zones (Fig. 3(a)). The logic function of the proposed 2:1 QCA multiplexer is

OUT ¼ I1:S þ I0:S where, I0 and I1 are the two data inputs and S is the select line. That is,

OUT ¼ MajðMajðS; I0; 0Þ; MajðS; I1; 0Þ; 1Þ ¼ MajðS:I0; S:I1; 1Þ ¼ S:I0 þ S:I1 It can be inferred from the above derivation that a 2:1 multiplexer requires 3 majority gates and 1 inverter as shown in Fig. 2. All logic elements int the schematic diagram of Fig. 3(a) are coloured to indicate the different clock zones. All the inputs (I0, I1 and S) are placed in one clock zone and the output is placed in another clock zone. This enables the clocking phases to traverse in the proper order (0, 1, 2, 0, 1, 2, . . .) and the required clock phases are always adjacent to each other to allow

S I0

M1 −1

1

M3

Out

M2

I1

Fig. 2. Schematic diagram of 2:1 multiplexer.

I0

max: 1.00e+00 S min: -1.00e+00

-1.00

max: 1.00e+00 I1 min: -1.00e+00

S

max: 1.00e+00 I0 min: -1.00e+00

I1

OUT

max: 9.54e-01 OUT min: -9.55e-01 max: 9.80e-22 CLOCK 0 min: 3.80e-23 max: 9.80e-22 CLOCK 1

-1.00

1.00

(a)

min: 3.80e-23

(b)

Fig. 3. QCA implementation of (a) proposed 2:1 multiplexer and (b) its simulation result.

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

correct signal propagation. The cell structure shown in Fig. 3(a) is the QCA realization of proposed multiplexer with the target objective of high device density, low area of layout and high computation speed. The simulation result for the multiplexer is shown in Fig. 3(b). In bistable approximation, the 2:1 multiplexer is simulated and verified using QCADesigner version 2.0.1 with default parameters. The performance of proposed QCA 2:1 multiplexer is compared with that of existing designs in terms of area, clock zones and cell complexity in Table 1. Column 1 denotes the scheme. The other 3 columns report the number of QCA cells required for the design, the area overhead and the number of clock zones. It can be established from the figures of Table 1 that the 2:1 multiplexer proposed in this section is having lesser numbers of cells, area and clock zones. 4.1. The 4:1 multiplexer The logic function of 4:1 QCA multiplexer is,

OUT ¼ I3:S0:S1 þ I2:S0:S1 þ I1:S0:S1 þ I0:S0:S1 where I0, I1, I2, I3 are the data input lines and S0, S1 are the two select lines. The proposed design is based on the module used for the 2:1 multiplexer. The schematic diagram and its QCA layout is shown in Fig. 4(a). The simulation result is shown in Fig. 4(b). In bistable approximation, the 4:1 multiplexer is simulated and verified setting the following parameters in QCADesigner version 2.0.1: number of samples = 450,001, radius-of-effect = 45 nm, maximum iterations per sample = 1000. The other parameters are set as default. 4.2. The 8:1 multiplexer The 8:1 multiplexer consists of two 4:1 multiplexers and one 2:1 multiplexer. All the inputs (I0–I7) are placed at the same clock zone and that is why all the AND gates, consisting of all the eight inputs, are in the same clock zone. The two select lines S0 and S1 controls the two 4:1 multiplexers and the select line S2 controls 2:1 multiplexer. The QCA realization of 8:1 multiplexer is shown in Fig. 5. The simulation result of 8:1 multiplexer is shown in Fig. 6. The relative performance analysis of 4:1 and 8:1 multiplexers is shown in Table 2 in terms of area, clock zones and cell complexity. In bistable approximation, the 8:1 multiplexer is simulated and verified. The parameters in QCADesigner version 2.0.1: number of samples = 1,400,000, radius of effect = 41 nm, Convergence Tolerance = 0.000000100, maximum iteration per sample = 1000 and other parameters are set as default. 5. Power estimation of proposed multiplexers The QCA computational paradigm introduces highly pipelined architectures with extremely high speed (in the order of THz). The molecular QCA can be faster than 2.5 THz. Theoretically, processing speed may reach 25 THz [1]. The kink energy plays a major function in power estimation as it delivers a direct and inverse relation with power dissipation and steady state polarisation error. Therefore, an optimal value of kink energy is desired to obtain a trade off between error and power dissipation. In this context, temperature factor is kept constant and the variation of kink energy is observed again to the change in dimension of the QCA cell as well as the spacing between the adjacent cells. In [9], a model is provided to calculate the power loss in a QCA circuit with sharp clock transitions. It results in non-adiabatic operations and yields the upper bound of power consumption. Examining the effect of kink energy on output error and power dissipation in QCA circuit, an attempt has been made to obtain a trade off between these two in [9,10]. The aim of this report is to reckon the result of power dissipation in the multiplexer circuit based on the model mentioned above [9]. Fig. 7 shows the thermal layout for average power dissipation at each cell in the 8:1 multiplexer. The worst thermal hot spots in the design are marked as black. It can be observed that the logic cell of the majority voters, including few L-shape wires, in the multiplexer are the weak spots. These hot spots dissipate maximum power (averaged over all input combinations) and, therefore, to form a thermally stable/tolerant design. 5.1. Estimation of power dissipation in multiplexer The effect of varying kink energy on the power dissipation during a switching event from one clock zone to other, in a multiplexer circuit, has been analysed and the results are shown in Table 4. It can be found that the kink energy in a circuit Table 1 Comparison of 2:1 multiplexers. Design #

Cells

Area (lm2 )

Clock zones

In [6] In [3] In [7] In [8] Proposed

41 56 36 27 23

0.08 0.07 0.06 0.03 0.02

4 4 3 3 2

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54 -1.00

1.00

I1

-1.00

I2

-1.00

S0 I1 2:1 I3

MUX

1.00

-1.00

OUT

I2 2:1 -1.00

OUT

S0

MUX

I3

I0

2:1 MUX

S1

I0 -1.00

1.00

S1

S0

(a) Schematic diagram and QCA layout max: 1.00e+000

S0 min: −1.00e+000 max: 1.00e+000

S1 min: −1.00e+000 max: 1.00e+000

I1 min: −1.00e+000 max: 1.00e+000

I0 min: −1.00e+000 max: 1.00e+000

I2 min: −1.00e+000 max: 1.00e+000

I3 min: −1.00e+000 max:9.54e−001

I3

I1

I0

I2

OUT min:−9.54e−001

(b) Simulation result Fig. 4. Implementation of proposed 4:1 multiplexer.

has the direct relation to the overall average power dissipation. The output node polarization error improves, but the power dissipation deteriorates when the kink energy is increased. 5.2. Output node polarization error for multiplexer It is already noted that with an increase in temperature both the polarisation error and the rate of power dissipation are increased. For the present analysis, maintaining the constant temperature, the decrease of node polarisation error is observed with the increase in kink energy in (Table 3). So, we can conclude that increase in maximum kink energy Ek has

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

-1.00

1.00

I0

-1.00

I1

S2

-1.00

I2

-1.00

-1.00

I3 1.00

S0

1.00

-1.00

L

-1.00

1.00

-1.00

1.00

-1.00

OUT 1.00

1.00 I4 -1.00

-1.00 I5

I6

-1.00

-1.00

1.00

S1

I7

-1.00

1.00 Fig. 5. QCA implementation of proposed 8:1 multiplexer.

a positive effect on the gain of node polarisation. This effect becomes more and more prominent with the increase in the number of cells in a design. That is, two different designs, performing a similar logic function but having an inadequate number of cells, can exhibit different polarizations at the output nodes. The details are reported in Table 3. Therefore, the increase in Ek refers to decrease in QCA cell size and grid spacing and that lead to a more compact construction. Table 3 establishes that our proposed multiplexer achieves similar output node polarisation as in [4] and it is a significant improvement over the design defined in [3]. On the other hand, comparatively low power dissipation is observed than the design reported in [4] (Table 4). Therefore, it can be concluded that the design proposed in this work not only suggests a modular approach for designing higher order multiplexer but it is also quite robust in terms of energy efficiency.

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

Select

0

1

I6

I2

2

3

4

5

6

7

I0

I7

I3

I5

I1

0

max: 1.00e+00

I0 min: −1.00e+00 max: 1.00e+00

I1 min: −1.00e+00 max: 1.00e+00

I2 min: −1.00e+00 max: 1.00e+00

I3 min: −1.00e+00 max: 1.00e+00

I4 min: −1.00e+00 max: 1.00e+00

I5 min: −1.00e+00 max: 1.00e+00

I6 min: −1.00e+00 max: 1.00e+00

I7 min: −1.00e+00

I4

I6

max: 9.54e−01

OUT min: −9.54e−01

Fig. 6. Simulation result of proposed 8:1 multiplexer.

Table 2 Performance comparison of different 4:1 and 8:1 multiplexers.

⁄

Design

Cells

Area (lm2 )

Clock zones

Wire crossing

4:1 multiplexer In [4] In [3] Proposed

271 215 155

0.37 0.25 0.24

19 6 5

6 8 3

Improvement(%)

27.9

4

16.6

62.5

8:1 multiplexer In [4] In [3] Proposed

1312 633 462

1.83 0.67 0.87

42 11 7

38 24 10

Improvement (%)

27

29⁄

36

58

Mitigated by less wire-crossing and less delay.

6. Fault-tolerant behaviour of proposed multiplexers One of the most vital characteristics of nano-scale electronics is the expected high defect density compared to VLSI. This is caused due to nano-scale operations (such as a bottom up self assembly) that are utilised to replace conventional lithography-based technique. Synthesis and deposition phases in QCA manufacturing are the main contributors of defect. As cell deposition is very sensitive to variation in process parameters [11], researchers have shown that the QCA circuits are more susceptible to missing and additional cell defects and have the substantial effect on its functionality. In this proposed work, using the HDLQ Verilog library [12], the QCA layout of a multiplexer is converted to its equivalent hardware description language notations. Verilog library of MV, INV, FO, L-shape wire with fault injection capability are available in the HDLQ design tool. The equivalent HDLQ model of the 2:1 multiplexer gate is shown in Fig. 8(a). Presence

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

Fig. 7. Thermal layout of proposed 8:1 multiplexer.

Table 3 Comparative analysis of output node polarization under different kink energies. Input

000 001 010 011 100 101 110 111

Node polarization of 2:1 multiplexer Ek ¼ 0:5 (meV)

Ek ¼ 1:0 (meV)

104

104

Ek ¼ 1:5 (meV) 104

In [4]

In [3]

Proposed

In [4]

In [3]

Proposed

In [4]

In [3]

proposed

4.10 4.10 4.10 4.10 4.10 4.10 4.10 4.10

6.04 6.04 6.04 6.04 6.04 6.04 6.04 6.04

4.10 4.10 4.10 4.10 4.10 4.10 4.10 4.10

11.83 11.83 11.83 11.83 11.83 11.83 11.83 11.83

17.42 17.42 17.42 17.42 17.42 17.42 17.42 17.42

11.83 11.83 11.83 11.83 11.83 11.83 11.83 11.83

19.85 19.85 19.85 19.85 19.85 19.85 19.85 19.85

29.22 29.22 29.22 29.22 29.22 29.22 29.22 29.22

19.85 19.85 19.85 19.85 19.85 19.85 19.85 19.85

Table 4 Comparative analysis of power dissipation at different multiplexers. Parameter

Ek ¼ 0:5 (meV) 102 In [4]

Proposed

Ek ¼ 1:5 (meV) 102

In [4]

In [3]

Proposed

In [4]

In [3]

Proposed

Max Energy Diss of Circuit Avg Energy Diss of Circuit Min Energy Diss of Circuit Avg Leakage Energy Diss Avg Switching Energy Diss

Power dissipation of 2:1 multiplexer 9.75 23.69 5.57 4.20 13.15 3.03 0.53 3.29 0.62 0.67 3.40 0.66 3.52 9.74 2.37

9.88 5.15 1.79 2.11 3.03

26.17 17.46 9.15 9.36 8.10

6.11 4.00 1.90 1.99 2.01

10.46 6.41 3.40 3.82 2.58

29.87 22.69 15.75 16.00 6.68

6.97 5.20 3.40 3.52 1.68

Max Energy Diss of Circuit Avg Energy Diss of Circuit Min Energy Diss of Circuit Avg Leakage Energy Diss Avg Switching Energy Diss

Power dissipation of 8:1 multiplexer 4.93 1.98 1.17 2.59 1.11 0.70 0.38 0.36 0.24 0.39 0.37 0.25 2.20 0.74 0.45

5.11 3.11 1.23 1.25 1.86

2.34 1.61 0.99 1.00 0.61

1.46 1.07 0.69 0.70 0.37

2.81 2.21 1.69 1.70 0.50

1.84 1.51 1.19 1.20 0.31

‘–’=Unable to estimate.

In [3]

Ek ¼ 1:0 (meV) 102

– – – – –

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B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

Fig. 8. HDLQ modelling of (a) Proposed 2:1 multiplexer. (b) Proposed 8:1 multiplexer.

of all possible single missing/additional cell defects in the majority voters (MAJs), FOs, INVs and CWs is detected by testing the HDLQ model with eight input vectors. It generates 6 unique fault patterns at the output as shown in Table 5. The 5, decimal value in three piece pattern is exemplified as a. For example, a0 represents 000 (decimal 0) and a7 represents 111

51

B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54 Table 5 Fault pattern of proposed 2:1 multiplexer. IV S I0 I1

Fault free output

a0 a1 a2 a3 a4 a5 a6 a7

Fault pattern

a0 a0 a1 a1 a0 a1 a0 a1

Fault tolerance %

1

2

3

4

5

6

a0 a0 a0 a0 a0 a1 a1 a1

a0 a0 a1 a1 a1 a1 a1 a1

a0 a0 a1 a1 a0 a1 a1 a1

a1 a1 a1 a1 a0 a1 a0 a1

a0 a1 a1 a1 a0 a1 a0 a1

a0 a0 a1 a1 a0 a0 a0 a0

Average=

84 67 84 84 84 84 50 84 77.62

LUT

MUX

Input

IV: input vector and a0 : means 000.

D Flip−flop Clock

Output

Control

Fig. 9. Schematic diagram of CLB unit.

A

B C

D

0 1 A

B

C

D

F= A xor B xor C xor D

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1

0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

0

1 0 1 0 1

1 0 1 0 0 1

F

1 0 0 D Flip Flop

1 0 1

Control

2:1 MUX

1 0

Clock

Fig. 10. MUX based implementation of CLB unit.

(decimal 7). From Table 5, it can be understood that the proposed design produces an average of 77.62% correct outputs even when design is faulty. The fault tolerance capability of 2:1 multiplexer reported in [3] is 65.62%. That is, the proposed 2:1 multiplexer achieves 15.58% better tolerance than that is reported in [3]. The HDLQ model of proposed 8:1 multiplexer is shown in Fig. 8(b). An exhaustive testing of this model with 211 (considering 8 inputs and 3 selection lines) input vectors shows 24 unique fault patterns at the output in presence of all possible single missing/additional cell defects in the majority voters (MAJs), FOs, INVs and CWs. In average, its fault tolerance is 75.29% (tabular representation is not included for its large volume of data). 7. Application of proposed multiplexer In [13], an architecture of Configurable Logic Block (CLB) in FPGA is formulated. It facilitates general purpose multiplexing and consists of a look up table (LUT), a flip-flop, and multiplexer as shown in Fig. 9. For realization, it is first broken down into smaller sub-circuits such that each of the sub-circuits can be implemented utilizing a single CLB. A wide range of functions

52

B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54 A B LOAD ENABLE

C -1 -1 1

-1

-1

1 1 -1 -1

-1

-1

-1

1

1 1

-1

-1

-1

1

1 -1

-1

-1

-1

-1

1 -1

1

-1

-1

-1 -1

1

-1

1

1 -1

D

F

Q

1

1 1 -1

-1

-1

-1

1 -1 -1 -1

1

-1

-1

1

1 -1

-1

-1

1

CLK

1

-1

-1

1 1 -1 -1

-1

-1

1

1

Fig. 11. QCA implementation of CLB unit.

can be implemented utilizing a logic block and, therefore is configured to perform combinational functions, or just simple logic gates like AND and XOR. An LUT in CLB can be implemented with decoder and memory cell or with the multiplexer having masked constants as input (Fig. 10). In the present work, the CLB unit (Fig. 10) is designed in QCA technology (Fig. 11) with the proposed 2:1 multiplexer. The simulation result is shown in Fig. 12.

8. Discussion Coplanar wire-crossings introduce the possibility of crosstalk and chances of increased output node polarisation error. One room to eliminate crossings in a given circuit is to duplicate logic gates such that the crossed connections can be taken away. From a physical implementation standpoint, gate duplication may unavoidably lead to area overhead. Furthermore, removing wire-crossings with gate duplication essentially pre-pones all wire-crossings by pushing them to the inputs of the circuit. That effectively increases the input size and in turn adds to area overhead. In Table 2, it is shown that our 8:1 multiplexer design the area overhead is 29% more than the design reported in [3] but in comparison to that of [4] the improvement is significant. However, significant improvement is achieved in wire-crossing (58% improvement) as well as in clock zones (36% improvement). The most important aspect in a QCA structure is the radius of effect. Radius of effect determines how tightly the cells are interacting among each other within its induced zone. As the distance between the cells increases, the influence of

B. Sen et al. / Computers and Electrical Engineering 45 (2015) 42–54

53

Fig. 12. Simulation result of QCA CLB unit.

neighbouring cells on polarization of a cell decreases. If the center-to-center distance between the cells exceeds a certain limit, the radius of effect becomes nil. That is, there is, no influence of neighbours on polarization of a cell. The minimum radius of effect within which our proposed design functions correctly are 28.29 nm (in 2:1 multiplexer), 40.01 nm (in 4:1 multiplexer), 40.01 nm (in 8:1 multiplexer) and the maximum does not have any point of accumulation.

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9. Conclusion An efficient methodology for designing reliable modular multiplexer using QCA technology is established which is better in terms of number of cells, clock zones and wire-crossings (58% improvement) than the existing modular multiplexer has been proposed. A modular approach in designing the higher order multiplexer by cascading lower order multiplexers is explored. It ensures a low power modular design by minimizing the rate of power dissipation and output node polarization error. Similarly, an enhancement of 18.25% in fault tolerant capability of the circuit is observed. An application of the same multiplexer to design configurable logic block (CLB) is also designed and simulated. References [1] Lent CS, Tougaw PD, Porod W, Bernstein GH. Quantum cellular automata. Nanotechnology 1993;4:49–57. [2] Chaudhary A, Chen DZ, Hu XS, Niemier MT, Ravichandran R, Whitton K. Fabricatable interconnect and molecular QCA circuits. IEEE Trans CAD Integr Circ Syst 2007;26:1978–91. [3] Mardiris VA, Karafyllidis IG. Design and simulation of modular 2n–1 QCA multiplexer. Intl J Circ Theory Appl 2010;38:771–85. [4] Sabbaghi-Nadooshan R, Kianpour M. A novel QCA implementation of MUX-based universal shift register. J Comput Electr 2013:1–13. [5] Sen B, Dutta M, Saran D, Sikdar B. An efficient multiplexer in quantum-dot cellular automata. In: Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol. 7373. Berlin Heidelberg: Springer; 2012. p. 350–1. http://dx.doi.org/10.1007/978-3-642-31494-0_40. [6] Kim K, Wu K, Karri R. The robust QCA adder designs using composable QCA building blocks. IEEE Trans Comput-Aid Des Integr Circ Syst 2007;26:176–83. [7] Hashemi S, Azghadi M, Zakerolhosseini A. A novel QCA multiplexer design. In: Telecommunications, 2008. International Symposium on, 2008. p. 692– 6. http://dx.doi.org/10.1109/ISTEL.2008.4651389. [8] Roohi A, Khademolhosseini H, Sayedsalehi S, Navi K. A novel architecture for quantum-dot cellular automata multiplexer. IJCSI 2011;8:55–60. [9] Srivastava S, Sarkar S, Bhanja S. Estimation of upper bound of power dissipation in QCA circuits. IEEE Trans Nanotechnol 2009;8:116–27. [10] Ma X, Huang J, Lombardi F. A model for computing and energy dissipation of molecular QCA devices and circuits. J Emerg Technol Comput Syst 2008;3:3:1–3:30. [11] Tahoori MB, Huang J, Momenzadeh M, Lombardi F. Testing of quantum cellular automata. IEEE Trans Nanotechnol 2004;3:432–42. [12] Ottavi M, Schiano L, Lombardi F, Lombardi F. HDLQ: a HDL environment for QCA design. ACM J Emerg Technol 2006;2:243261. [13] New BJ. Multiplexer enhanced configurable logic block, 2000. Bibhash Sen received his B.Tech degree in CSE from NERIST, Nirjuli, India in 2002 and the M.E. in CSE from the IIEST, Shibpur in 2007. He has submitted his PhD thesis in 2014. Currently, He is an assistant professor of CSE department, NIT Durgapur. His research interests include Quantum-dot Cellular Automata, Reversible logic, Fault tolerant architectures for emerging nano-devices. Mrinal Goswami received his B.Tech degree from NERIST, Nirjuli (India) in 2012. He received his M.Tech in CSE from NIT, Durgapur (India) in 2014. He is currently working as Assistant Professor in NERIST (India). His research interests include in design and testing of Quantum-dot Cellular Automata and Reversible logic. Subhra Mazumdar completed her B.Tech in CSE from NIT Durgapur in 2014. Her research interests include Cryptography, Algorithms and DNA Computing. Currently she is working at TCS Innovation Labs, Kolkata on Graph based Analytic for Cognitive Diagnostics and Planning. Biplab K Sikdar received his B. Sc. (Hons) in physics, B. Tech and M.Tech in CSE from Calcutta University, India, in 1985, 1988 and 1990, respectively, and the PhD from BEC, Shibpur in 2003. Presently, he is a professor in the CST department, IIEST, Shibpur, India. His research interests include digital system design and test, Cellular Automata theory.