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A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA
Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
1 Contents lists available at ScienceDirect 2 3 4 5 6 journal homepage: www.elsevier.com/locate/dib 7 8 9 Data Article 10 11 12 Q1 13 14 15 16 17 Peer Zahoor Ahmad a,n, S.M.K. Quadri b, Firdous Ahmad c,n, 18 Ali Newaz Bahar d, Ghulam Mohammad Wani e, 19 Shafiq Maqbool Tantary f 20 21 Q2 a Department of Computer Science, University of Kashmir, Srinager, Jammu and Kashmir, India b Department of Computer Science, Jamia Millia Islamia, New Delhi, India 22 c Department of Electronics & IT, University of Kashmir, Srinager, Jammu and Kashmir, India 23 d Department of Information & Communication Technology, Mawlana Bhashani Science and Technology 24 University, Tangail, Bangladesh e 25 Department of Physics, Sri Pratap College, Srinagar, Jammu and Kashmir, India f Department of Physics, Govt Degree College Patan, Jammu and Kashmir, India 26 27 28 a r t i c l e i n f o abstract 29 30 Article history: Quantum-dot cellular automata, is an extremely small size and a 31 Received 11 January 2017 powerless nanotechnology. It is the possible alternative to current 32 Received in revised form CMOS technology. Reversible QCA logic is the most important issue at 33 29 April 2017 present time to reduce power losses. This paper presents a novel 34 Accepted 4 October 2017 reversible logic gate called the F-Gate. It is simplest in design and a 35 powerful technique to implement reversible logic. A systematic 36 Keywords: approach has been used to implement a novel single layer reversible 37 QCA Full-Adder, Full-Subtractor and a Full Adder–Subtractor using the F-Gate 38 F-Gate. The proposed Full Adder–Subtractor has achieved significant Adder 39 improvements in terms of overall circuit parameters among the most Subtractor 40 previously cost-efficient designs that exploit the inevitable nano-level Adder–subtractor issues to perform arithmetic computing. The proposed designs have 41 QCADesigner been authenticated and simulated using QCADesigner tool ver. 2.0.3. 42 & 2017 Published by Elsevier Inc. This is an open access article under 43 the CC BY license (http://creativecommons.org/licenses/by/4.0/). 44 45 46 47 48 49 n Corresponding authors. 50 E-mail addresses: [email protected] (P.Z. Ahmad), fi[email protected] (F. Ahmad). 51 52 http://dx.doi.org/10.1016/j.dib.2017.10.011 53 2352-3409/& 2017 Published by Elsevier Inc. This is an open access article under the CC BY license 54 (http://creativecommons.org/licenses/by/4.0/).
Data in Brief
A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
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Specifications Table Subject area More specific subject area Type of data How data was acquired Data format Experimental factors Experimental features Data accessibility
Nanoelectronics Nanotechnology QCA reversible logic design Table, figure QCADesigner software Bistable engine and Analysis process have been applied to attain the data results Analyzed Reversible F-Gate has been proposed. It has been testified to determine various arithmetic logic circuits Computational Simulation study has been used to determine results Data is available within this article
Value of the data
Gates are the basic building block to design logic in digital systems. A new reversible F-Gate has been proposed to enhance the performance of digital systems.
Adder circuits are widely investigated since their performance can directly affect the whole digital
system performance. We have proposed an optimal reversible Arithmetic circuits including Adder, Subtractor and Adder-Subtractor using the proposed F-Gate. The presented circuit designs and data analysis can support the researchers to reduce the circuit complexity and implement high robust Arithmetic logic designs. The proposed QCA reversible designs can be used to reduce hardware cost and design energy lossless arithmetic logic unit (ALU) in quantum computers.
1. Data In this paper, a new high speed and a low power reversible gate called the F-Gate has been proposed. The logic symbol, QCA layout, and its simulation results are shown in Fig. 1. The proposed gate has been used in a systematic manner to implement single layer arithmetic logic functions such as reversible Full Adder (RFA), reversible Full Subtractor (RFS) and reversible Full Adder-Subtractor (RFAS). The logic symbol, QCA layout, and simulation results of the proposed Arithmetic circuits are shown in Figs. 2–4, respectively. A detailed report on the hardware costs achieved from the proposed QCA implementations in terms of area, cell counts and clock delays are provided in Table 1. However, the structural evaluation of the proposed RFAS circuit has been compared with their conventional counterparts [1–5]. The detailed comparison results of RFAS are shown in Table 2.
2. Experimental design, materials and methods QCADesigner tool ver. 2.0.3 [6] with default parameters have been verified the functioning of the proposed QCA-circuits. The default parameters are listed as: QCA cell size ¼ 18 nm, diameter of quantum dots ¼ 5 nm, number of samples ¼ 50,000, convergence tolerance ¼ 0.001, radius of effect ¼ 65 nm relative permittivity ¼ 12.9, clock low ¼ 3.8e−23 J, clock high ¼ 9.8e−22 J, clock amplitude factor ¼ 2.000, layer separation ¼ 11.5 nm and maximum iterations per sample ¼ 100. The simu-
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
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Fig. 1. (a) Logic symbol (b) QCA Layout (c) Simulation results.
lation result, shown in Figs. 1–4, validates the functionality of the proposed circuits, which has used the proposed F-Gate as its main functional block. The construction of the F-Gate is simple in design. It consists of three inputs (A, B, & C) and three outputs “P, Q, & R”. The main processing part of the F-Gate is a three-input XOR (TIEO) [8]. The Q ¼ (A ⊕ B ⊕ C) is carried out from the main part of the F-Gate. The logic expression of inputs & outputs are expressed as: P¼A
ð1Þ
Q ¼ ðA⊕B⊕CÞ
ð2Þ
R¼B
ð3Þ
To testify the functionality of the F-Gate it has been used as a main component to compute Sum bits of the reversible Full-Adder (RFA), Difference of the reversible Full-Subtractor (RFS) and Sum/ Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
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P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Fig. 2. (a) Logic diagram (b) QCA Layout (c) Simulation results.
Difference of the reversible Full Adder-Subtractor (RFAS). Table 2 includes a comparison between our proposed Full Adder-Subtractor with their conventional counterparts. An extensive structural analysis have been developed in different aspects of Area, Circuit complexity and cost of the proposed Full Adder-Subtractor and previously published works [1–5]. The proposed RFAS produce one garbage outputs. However, clock zones for wire crossing signal synchronization makes the latency (number of clock cycles), a little head greater than conventional designs. But the RFAS have achieved a significant improvements in terms of Cost ¼ Area × Delay × Power [7] than existing one. It performs both addition and subtraction operations. The main outputs of the RFAS circuit are, P ¼ A ⊕ B ⊕ C, pro-
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
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Fig. 3. (a) Logic diagram (b) QCA Layout (c) Simulation results.
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
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P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Fig. 4. (a) Logic diagram (b) QCA Layout (c) Simulation results.
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
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325 Table 1 QCA design characteristics. 326 327 Proposed structures ConstantGarbage Area Circuit complexity Latency (Clock Cost ¼ Area × Delay 328 inputs outputs (μm2) (Cell-Counts) delays) × Power 329 F-Gate 0 1 0.02 18 3-clock phases 0.27 330 ¼ (0.75) 331 Proposed Full Adder 0 1 0.03 45 3-clock phases 1.0125 332 (RFA) ¼ (0.75) 333 Proposed Full Sub0 1 0.04 47 3-clock phases 1.35 tractor (RFS) ¼ (0.75) 334 335 336 337 338 Table 2 Comparisons of reversible Full Adder-Subtractor circuits. 339 340 Full Adder–SubConstantGarbage Area Circuit complexity Latency (Clock Cost ¼ Area× Delay 341 tractor designs inputs outputs (μm2) (Cell-counts) delays) × Power 342 Ref. [1] 0 3 0.46 343 6-clock phases 236.67 343 ¼ (1.50) 344 Ref. [1] 0 3 0.47 356 6-clock phases 250.98 345 ¼ (1.50) 346 Ref. [2] 1 2 0.78 517 13-clock phases 1310.595 ¼ (3.25) 347 Ref. [3] 3 3 0.96 612 16-clock phase 2350.08 348 ¼ (4.0) 349 210.6 Ref. [4] 0 3 0.40 351 6-clock phase 350 ¼ (1.50) 351 Ref. [5] 1 1 0.28 228 7-clock phase 111.72 ¼ (1.75) 352 Proposed Full Adder- 0 1 0.11 109 7-clock phase 20.9825 353 Subtractor ¼ (1.75) 354 355 356 duces Sum/Difference. The Sum/Difference is the Sum and Difference of the three inputs (A, B, C) and 357 Q ¼ MV (A′, B, C) & R ¼ MV (A, B, C) are the outputs of Borrow and Carry, respectively. 358 359 360 Acknowledgements 361 362 Authors have declared that no competing interests exist regarding the publication of this 363 manuscript. 364 365 366 367 368 Q3 Transparency document. Supplementary material 369 Transparency document associated with this article can be found in the online version at http://dx. 370 doi.org/10.1016/j.dib.2017.10.011. 371 372 373 374 Appendix A. Supplementary material 375 376 Supplementary data associated with this article can be found in the online version at http://dx.doi. 377 378 org/10.1016/j.dib.2017.10.011. Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
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References [1] X. Ma, J. Huang, C. Metra, F. Lombardi, Reversible and testable circuits for molecular QCA design, in: M. Tehranipoor (Ed.), Emerging Nanotechnologies, Springer, US, 2008. [2] B. Sen, M. Dutta, S. Some, B.K. Sikdar, Realizing reversible computing in QCA framework resulting in efficient design of testable ALU, ACM J. Emerg. Technol. Comput. Syst. 11 (2014) 8–22 (30). [3] B. Sen, M. Dutta, M. Goswami, B.K. Sikdar, Modular design of testable reversible ALU by QCA multiplexer with increase in programmability, Microelectron. J. 45 (2014) 1522–1532. [4] Z. Mohammadi, M. Mohammadi, Implementing a one-bit reversible full adder using quantum- dot cellular automata, Quantum Inf. Process. 13 (2014) 2127–2147. [5] M. Moaiyeri, E. Taherkhani, S. Angizi, A Novel Efficient Reversible Full Adder-Subtractor in QCA Nanotechnology, CS, arXiv1610.09473, 2016. [6] K. Walus, T.J. Dysart, G.A. Jullien, R.A. Budiman, QCADesigner: a rapid design and simulation tool or quantum-dot cellular automata, IEEE Trans. Nanotechnol. 3 (2004). [7] V.G. Oklobdzija (Ed.), The Computer, Engineering Handbook, CRC Press, Boca Raton, FL, 2002, pp. 81–86. [8] F. Ahmad, Gh. Mohiuddin Bhat, H. Khademolhosseini, S. Azimi, S. Angizi, K. Navi, Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells, J. Comput. Sci. 16 (2016) 8–15.
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
1 Contents lists available at ScienceDirect 2 3 4 5 6 journal homepage: www.elsevier.com/locate/dib 7 8 9 Data Article 10 11 12 Q1 13 14 15 16 17 Peer Zahoor Ahmad a,n, S.M.K. Quadri b, Firdous Ahmad c,n, 18 Ali Newaz Bahar d, Ghulam Mohammad Wani e, 19 Shafiq Maqbool Tantary f 20 21 Q2 a Department of Computer Science, University of Kashmir, Srinager, Jammu and Kashmir, India b Department of Computer Science, Jamia Millia Islamia, New Delhi, India 22 c Department of Electronics & IT, University of Kashmir, Srinager, Jammu and Kashmir, India 23 d Department of Information & Communication Technology, Mawlana Bhashani Science and Technology 24 University, Tangail, Bangladesh e 25 Department of Physics, Sri Pratap College, Srinagar, Jammu and Kashmir, India f Department of Physics, Govt Degree College Patan, Jammu and Kashmir, India 26 27 28 a r t i c l e i n f o abstract 29 30 Article history: Quantum-dot cellular automata, is an extremely small size and a 31 Received 11 January 2017 powerless nanotechnology. It is the possible alternative to current 32 Received in revised form CMOS technology. Reversible QCA logic is the most important issue at 33 29 April 2017 present time to reduce power losses. This paper presents a novel 34 Accepted 4 October 2017 reversible logic gate called the F-Gate. It is simplest in design and a 35 powerful technique to implement reversible logic. A systematic 36 Keywords: approach has been used to implement a novel single layer reversible 37 QCA Full-Adder, Full-Subtractor and a Full Adder–Subtractor using the F-Gate 38 F-Gate. The proposed Full Adder–Subtractor has achieved significant Adder 39 improvements in terms of overall circuit parameters among the most Subtractor 40 previously cost-efficient designs that exploit the inevitable nano-level Adder–subtractor issues to perform arithmetic computing. The proposed designs have 41 QCADesigner been authenticated and simulated using QCADesigner tool ver. 2.0.3. 42 & 2017 Published by Elsevier Inc. This is an open access article under 43 the CC BY license (http://creativecommons.org/licenses/by/4.0/). 44 45 46 47 48 49 n Corresponding authors. 50 E-mail addresses: [email protected] (P.Z. Ahmad), fi[email protected] (F. Ahmad). 51 52 http://dx.doi.org/10.1016/j.dib.2017.10.011 53 2352-3409/& 2017 Published by Elsevier Inc. This is an open access article under the CC BY license 54 (http://creativecommons.org/licenses/by/4.0/).
Data in Brief
A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
2
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108
Specifications Table Subject area More specific subject area Type of data How data was acquired Data format Experimental factors Experimental features Data accessibility
Nanoelectronics Nanotechnology QCA reversible logic design Table, figure QCADesigner software Bistable engine and Analysis process have been applied to attain the data results Analyzed Reversible F-Gate has been proposed. It has been testified to determine various arithmetic logic circuits Computational Simulation study has been used to determine results Data is available within this article
Value of the data
Gates are the basic building block to design logic in digital systems. A new reversible F-Gate has been proposed to enhance the performance of digital systems.
Adder circuits are widely investigated since their performance can directly affect the whole digital
system performance. We have proposed an optimal reversible Arithmetic circuits including Adder, Subtractor and Adder-Subtractor using the proposed F-Gate. The presented circuit designs and data analysis can support the researchers to reduce the circuit complexity and implement high robust Arithmetic logic designs. The proposed QCA reversible designs can be used to reduce hardware cost and design energy lossless arithmetic logic unit (ALU) in quantum computers.
1. Data In this paper, a new high speed and a low power reversible gate called the F-Gate has been proposed. The logic symbol, QCA layout, and its simulation results are shown in Fig. 1. The proposed gate has been used in a systematic manner to implement single layer arithmetic logic functions such as reversible Full Adder (RFA), reversible Full Subtractor (RFS) and reversible Full Adder-Subtractor (RFAS). The logic symbol, QCA layout, and simulation results of the proposed Arithmetic circuits are shown in Figs. 2–4, respectively. A detailed report on the hardware costs achieved from the proposed QCA implementations in terms of area, cell counts and clock delays are provided in Table 1. However, the structural evaluation of the proposed RFAS circuit has been compared with their conventional counterparts [1–5]. The detailed comparison results of RFAS are shown in Table 2.
2. Experimental design, materials and methods QCADesigner tool ver. 2.0.3 [6] with default parameters have been verified the functioning of the proposed QCA-circuits. The default parameters are listed as: QCA cell size ¼ 18 nm, diameter of quantum dots ¼ 5 nm, number of samples ¼ 50,000, convergence tolerance ¼ 0.001, radius of effect ¼ 65 nm relative permittivity ¼ 12.9, clock low ¼ 3.8e−23 J, clock high ¼ 9.8e−22 J, clock amplitude factor ¼ 2.000, layer separation ¼ 11.5 nm and maximum iterations per sample ¼ 100. The simu-
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162
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Fig. 1. (a) Logic symbol (b) QCA Layout (c) Simulation results.
lation result, shown in Figs. 1–4, validates the functionality of the proposed circuits, which has used the proposed F-Gate as its main functional block. The construction of the F-Gate is simple in design. It consists of three inputs (A, B, & C) and three outputs “P, Q, & R”. The main processing part of the F-Gate is a three-input XOR (TIEO) [8]. The Q ¼ (A ⊕ B ⊕ C) is carried out from the main part of the F-Gate. The logic expression of inputs & outputs are expressed as: P¼A
ð1Þ
Q ¼ ðA⊕B⊕CÞ
ð2Þ
R¼B
ð3Þ
To testify the functionality of the F-Gate it has been used as a main component to compute Sum bits of the reversible Full-Adder (RFA), Difference of the reversible Full-Subtractor (RFS) and Sum/ Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
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P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Fig. 2. (a) Logic diagram (b) QCA Layout (c) Simulation results.
Difference of the reversible Full Adder-Subtractor (RFAS). Table 2 includes a comparison between our proposed Full Adder-Subtractor with their conventional counterparts. An extensive structural analysis have been developed in different aspects of Area, Circuit complexity and cost of the proposed Full Adder-Subtractor and previously published works [1–5]. The proposed RFAS produce one garbage outputs. However, clock zones for wire crossing signal synchronization makes the latency (number of clock cycles), a little head greater than conventional designs. But the RFAS have achieved a significant improvements in terms of Cost ¼ Area × Delay × Power [7] than existing one. It performs both addition and subtraction operations. The main outputs of the RFAS circuit are, P ¼ A ⊕ B ⊕ C, pro-
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270
Fig. 3. (a) Logic diagram (b) QCA Layout (c) Simulation results.
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
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P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
Fig. 4. (a) Logic diagram (b) QCA Layout (c) Simulation results.
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
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325 Table 1 QCA design characteristics. 326 327 Proposed structures ConstantGarbage Area Circuit complexity Latency (Clock Cost ¼ Area × Delay 328 inputs outputs (μm2) (Cell-Counts) delays) × Power 329 F-Gate 0 1 0.02 18 3-clock phases 0.27 330 ¼ (0.75) 331 Proposed Full Adder 0 1 0.03 45 3-clock phases 1.0125 332 (RFA) ¼ (0.75) 333 Proposed Full Sub0 1 0.04 47 3-clock phases 1.35 tractor (RFS) ¼ (0.75) 334 335 336 337 338 Table 2 Comparisons of reversible Full Adder-Subtractor circuits. 339 340 Full Adder–SubConstantGarbage Area Circuit complexity Latency (Clock Cost ¼ Area× Delay 341 tractor designs inputs outputs (μm2) (Cell-counts) delays) × Power 342 Ref. [1] 0 3 0.46 343 6-clock phases 236.67 343 ¼ (1.50) 344 Ref. [1] 0 3 0.47 356 6-clock phases 250.98 345 ¼ (1.50) 346 Ref. [2] 1 2 0.78 517 13-clock phases 1310.595 ¼ (3.25) 347 Ref. [3] 3 3 0.96 612 16-clock phase 2350.08 348 ¼ (4.0) 349 210.6 Ref. [4] 0 3 0.40 351 6-clock phase 350 ¼ (1.50) 351 Ref. [5] 1 1 0.28 228 7-clock phase 111.72 ¼ (1.75) 352 Proposed Full Adder- 0 1 0.11 109 7-clock phase 20.9825 353 Subtractor ¼ (1.75) 354 355 356 duces Sum/Difference. The Sum/Difference is the Sum and Difference of the three inputs (A, B, C) and 357 Q ¼ MV (A′, B, C) & R ¼ MV (A, B, C) are the outputs of Borrow and Carry, respectively. 358 359 360 Acknowledgements 361 362 Authors have declared that no competing interests exist regarding the publication of this 363 manuscript. 364 365 366 367 368 Q3 Transparency document. Supplementary material 369 Transparency document associated with this article can be found in the online version at http://dx. 370 doi.org/10.1016/j.dib.2017.10.011. 371 372 373 374 Appendix A. Supplementary material 375 376 Supplementary data associated with this article can be found in the online version at http://dx.doi. 377 378 org/10.1016/j.dib.2017.10.011. Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i
P.Z. Ahmad et al. / Data in Brief ∎ (∎∎∎∎) ∎∎∎–∎∎∎
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References [1] X. Ma, J. Huang, C. Metra, F. Lombardi, Reversible and testable circuits for molecular QCA design, in: M. Tehranipoor (Ed.), Emerging Nanotechnologies, Springer, US, 2008. [2] B. Sen, M. Dutta, S. Some, B.K. Sikdar, Realizing reversible computing in QCA framework resulting in efficient design of testable ALU, ACM J. Emerg. Technol. Comput. Syst. 11 (2014) 8–22 (30). [3] B. Sen, M. Dutta, M. Goswami, B.K. Sikdar, Modular design of testable reversible ALU by QCA multiplexer with increase in programmability, Microelectron. J. 45 (2014) 1522–1532. [4] Z. Mohammadi, M. Mohammadi, Implementing a one-bit reversible full adder using quantum- dot cellular automata, Quantum Inf. Process. 13 (2014) 2127–2147. [5] M. Moaiyeri, E. Taherkhani, S. Angizi, A Novel Efficient Reversible Full Adder-Subtractor in QCA Nanotechnology, CS, arXiv1610.09473, 2016. [6] K. Walus, T.J. Dysart, G.A. Jullien, R.A. Budiman, QCADesigner: a rapid design and simulation tool or quantum-dot cellular automata, IEEE Trans. Nanotechnol. 3 (2004). [7] V.G. Oklobdzija (Ed.), The Computer, Engineering Handbook, CRC Press, Boca Raton, FL, 2002, pp. 81–86. [8] F. Ahmad, Gh. Mohiuddin Bhat, H. Khademolhosseini, S. Azimi, S. Angizi, K. Navi, Towards single layer quantum-dot cellular automata adders based on explicit interaction of cells, J. Comput. Sci. 16 (2016) 8–15.
Please cite this article as: P.Z. Ahmad, et al., A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA, Data in Brief (2017), http: //dx.doi.org/10.1016/j.dib.2017.10.011i