CMOS regenerative logic circuits

0026-269218311405-0021$5.00/0

CMOS regenerative logic circuits by Branko L. Doki~ Faculty of Electric Engineering,

University of Banjaluka, Yugoslavia

New solutions of inverter, NAND and NOR logic circuits with hysteresis transfer characteristic (Schmitt triggers} consisting of three standard CMOS logic circuits and one resistor are described in this paper. The input circuit determines the logic function of a Schmitt trigger and the other two are connected in an inverter configuration. Through resistor R and the inverters, the positive feedback loop is closed during the change of output state. Besides the theoretical analysis of transfer function and conditions of existence of hysteresis, experimental results are given in the paper.

1. Introduction Logic circuits with positive feedback (regenerative circuits) and hysteresis in the transfer characteristic, frequently called Sehmitt triggers, have very high noise immunity and almost ideal transfer characteristics. In monolithic CMOS integrated circuits, besides Schmitt trigger inverters (MC 14584C, CD 40106B or MM 74C14) there are two - input NAND Schmitt triggers (CD 4093, MC 14093). There are two types of Schmitt trigger - inverters (Fig. 1) used in standard CMOS logic circuits, la Voltage hysteresis of the circuit in Fig. l(a) is equal to the product of supply voltage VDD and the resistance ratio R2/Rz, and the input resistance is RI + R2. The asynchronous D-type flip-flop (Fig. l(b) and l(c)) will have static transfer characteristics with hysteresis if the threshold voltage of circuit A is higher than the threshold voltage of circuit B i.e. VXA > V s . It can be shown that the threshold voltage of CMOS N A N D and N O R logic circuits depends on the number and combination of active inputs. 3 In the general case when A and B are m-input logic circuits, using eqns (17) and (18) of reference 3 and the condition VrA > V-m, the condition for existence of hysteresis of the circuit in Fig. l(b) and Fig. l(c) is obtained as: kA <

an

kB + (m+ 1) (1--nB/nA)

nA

where: m - no. of inputs, n - no. of active inputs, k-first active input position (indices A and B relate respectively to logic circuit A and B). The circuits in Fig. 1 are impractical for multiple input N A N D or N O R logic functions to be realised. MICROELECTRON1CS JOURNAL Vo114 No 5 9 1983 Benn Electronics Publications Ltd, Luton

21

CMOS regenerative logic circuits continued from page 21 I

Vin c

;

;

l

-

R1

I

R2 .

~ j ~ - ~ L j ~ ~

ut

Q)

Vin

iVooir i,o, b)

(GND or Vin)

Won i

_ Vooot

c) Fig. 1 Standardperformanceof Schmitt triggerswith CMOScircuits.

Simple solutions for inverters, NAND and N O R Schmitt triggers as used in standard CMOS logic circuits are proposed in tlJis paper. In contrast to the solutions known up to now, N A N D and N O R logic operations can be simply realised, as well as the inverter function. Transfer function and threshold voltages as well as hysteresis conditions will be analysed in detail. 2.

Inverter

A Schmitt trigger scheme with one input is shown in Hg. 2. Instead of resistor R t in Fig. 1 (a), a CMOS inverter with transistors 'IN and Tp is used. The positive feedback loop is closed through resistor R and inverters I2 and I3 during the change of state at the output. As in static conditions V',t = Vo,t the current through resistor R is then equal to zero, so that the static power consumption of the circuit in Fig. 2 is negligible. Resistor R reduces the voltage gain of inverter It in the transient region before the beginning of the regenerative process. It is specially emphasised that when both transistors "IN and rip are in the saturated region, the voltage gain of inverter It without resistor R (R ~ =) would be very high (higher than 1000) and with resistor R can be lower than 1. 22

+VDD

TP I

R

T

Fig. 2 Logic scheme of regenerative inverter.

Therefore, the transfer characteristic Vo',,(V~,) is moved to the right when V~, increases and to the left when Vi, decreases in relation to the inverter characteristic when there is no resistor R. Due to the regenerative process and as the change of state at the outpui occurs when V'u, is equal to the threshold voltage VT2 of inverter I2, the transfer characteristic will show hysteresis. 2.1 Circuit analysis Transfer functions V~utWin) and Vout(Vi.) are shown in Fig. 3(a) and Fig. 3(b) respectively. As the threshold voltages V~- and Vu depend on V;~t(Vi.) this function will be analysed in more detail. Threshold voltages and constants/3 of NMOS and PMOS transistors will be designated VaN, flr~ and Vav,/3p. For 0' --< Vi, < V ~ , Tr~ is OFF, and Tp is ON and in the nonsaturated region so that Vo'~t= Volt = VOD. When V ~ < Vi. < V'~t -[Vrp[ both transistors are ON, with Tp being in the nonsaturated region and T. saturated between points A and B in Fig. 3(a). Then we have:

/3N(V~--VTN)2 =/3p[2(VDD+V'n,--V~) (VDD-V'.t) -- (VDD--V:~,)2] -t

VDD--Vgut R

. (1)

Through solution of eqn. (1) we obtain:

1 #( v'u, = v~. - v~, 2/3p~ +

1 _)2 __VDD+V~--V"+2/3p~

_ f i n (Vi.-VT~)2 9 (2) /JN

Between the points B and C, (Vo'~t-lVTpl< Vi. < V~-) i.e. for V'~t--lVTPl< Vi. < V'= + VaN both transistors are in the saturated region so that /3N(Vin--VTN) 2 = /3p(VDD4"VTp--Vin) 2 q'

VDD--V'u, R

......................

(3)

The voltage Votut = V D D - / 3 pR [ ~_N Win--VTN)2 -- (VDD"[-VTp--Via)2 / . . . . . . . . . . . . .

L~

(4)

J 23

CMOS

regenerative logic circuits continued from page 23

is a quadratic function of the input voltage, the voltage gain of inverter 11 in this region is directly proportional to the resistance R. In the case when fiN/fie = 1, it is seen from eqn. (4) that V'=t = VDD(I+/3pAVR) - 2/3pAVRV, . . . . . . . . . . . . . . . . . . . . . . (5) i.e. V'., is a linear function of Vi.. In eqn. (5) AV = V o r , - I V ~ I - V ~ . -0 >

Voo

A

~."

Z'"'~. \ ~

\-,,~ ,,0 /

l

"x/~

!

,..\i"\ ',7/ ", ,N

'i,

,'"

i

v~o,2 __ 4,-~/4~ I\~ - 49 - : ~ 4/ ..'g\~ ', , " , ; ' / -~o'~"~/

\

,,~'~

~-

;49 "

I

'I

-

, ,, ,

~ \1\\, , i'~ .'b,,, !~..

v;.

/

1- - 4 "

JV,~

, ~-,s >"

~',~

\ \ ,. /~",,}..-" § \",'~ r

' '" \ ~'F\, \ ~ IN." .<,.'>" , ' s ' ~ \ .

.

IVTpI'

0"-

I

l

v00,~

LI~,~

w,,

a )l 0

>

%o ....

I I I I I I

I I I

t I I I I

I I I I

I I I

I I

I

k

I I 1

T ~

Vf b) 24

_-E ,,Vop

V,~

V0D A w

lt_

Vin

Hg. 3 Transfer characteristics Vgut(Vin)and Vout(Vin) for various values of resistance R.

Equations (4) and (5) are valid for V'u, < V-n. When V'u, becomes equal to the threshold voltage of inverter I2 the regenerative process occurs, so that voltages V',, and Vow,rapidly decrease due to the very high voltage gain in the feedback loop. The input voltage, at which these changes occur, is the high threshold V~ of the Schmitt trigger. From the condition V'~t(W~-) = Va~ and eqn. (4) it is shown that:

VDD-]-Vw- VTNflN/]~P BN/~P- 1

[

'~

+ ~s/flp-1)

(VDD']-VTp)2 "~-(VDD--V-[2)[ (/3pR)-V~,flr~/~p 1' (6) (VDD"t-VTp-- VTNBN/Bp)2

where Vr2 = V-rs Jr

VDD+VrrV~ I +X///s//3p

..........................

(7)

The regenerative process finishes when Vout = 0. As then "Is is in the nonsaturated region and Tp is in saturation, it is, for V~- < Vin < VDD + Vw, V'u,(V~,), a quadratic function given by eqn. (8). When the input voltage decreases and at Vi. = VDD+Vw, Tp starts t_urning ON. Between points E and F (Fig. 3(a)), i.e. for V',t + VaN < V~n< VDr, + Vw, Tp is in the saturated region and "Is is nonsaturated so that

vo,:rv

voo+v.v

\

2flsR/

V

/3s

Vi,-V~+l/(2flsR)

):]

(8)

For V~ut+W-rp
g~ut = BpR [(VDD-'}'V.rp--Via)2 -- -~-pS(Vin--VTN)2]

...................

(9)

and in the special case of/3s =/3p, by vg., = flp(VDD+V~--V~)R (V~D-2V~,)

....................

(10)

when V',t = V~, the regenerative process starts and change of state at the output occurs. Therefore, from condition Vo'u,(Vu = V~ and eqn. (9), it is seen that the low threshold of the Schmitt trigger is

VDD+ VTp--VTN~N/~p fls//3p- 1

['~I+

(fls/flp- 1)

(VDD--V'rp)2 + VTZ/ (flpR)-V~fls/flp (VDD"I-VTp-- VTN/~ N//3p)2

- ~ , (11)

where V ~ is determined by eqn. (7).

25

CMOS regenerative logic circuits continued from page 25

Voltage hysteresis VH is equal to the difference of high and low threshold voltages, and is given by Vn-

VDD+VTp--V~/3N//3p BN//3P- 1 _1~ (Vt)D+Vav)2+(VDD-Vx2) / (flpR)-V-~/3~//3p (VDD "It"VT P -- VTN/3 N//3 p)

7

_ 1) (VDD+Vav)2-Vx2 / (/3PR)-V~2/3r4/3P ]

v

\~p

W D D -I-V.rp--VTN/3 N//3p)2

.]"

(12)

With constants/3 and thresholds of all transistors being equal, then V~ = VDb/2 and on the basis of eqns (5) and (10), the thresholds of the Schmitt trigger are given as Vr V~=

VDD VDD 2 +4/3(VDD+Vav-V~)R . . . . . . . . . . . . . . . . . . . . . VDD VDD + 2 4j~(VDD+VTp--VTN)R

(13) ....................

(14)

.... ................

(15)

In that case voltage hystresis is given by

V~,D

V,,-

2/3(VDD+VTe--VTN)R Expressions for thresholds V + and Vu arc derived on the assumption that at vgut = VT2 both "In and Tp arc in the saturated region. But, at low values of resistance R when Vo',,= VT2, one of the transistors Crn when V ~ increases and 'Iv when Vt~ decreases) can go out of the saturated region into a nonsaturatcd one. In that case the transfer characteristics are drawn with broken lines (Fig. 3). This will happen ifV~ - VTS > VT2 and/or Vu + IVvpl < VT2 i.e. from cqns (13) and (14) if

R <

VDD 4fl(VD D "{"VTp --VTI~)V'I~

....................

(16)

A n equation for determination of V~-, for example, would bc then obtained by equating the drain current of transistorTN in the nonsaturatcd region to the sum of the current through R and the drain current of transistor'Iv in the saturated region. However, as the transition from a saturated region into a nonsaturatcd one isgradual, derived expressions (6) and (13) i.e.(11) and (14) for thresholds V-~ and Vu will bc valid with small error cvcn when Condition (16) is fulfilled. The output resistance of inverter I3 which can bc several hundred ohms, has bccn neglected in the analysis up to now. The expressions can be simply corrected when that resistance is added to resistance R. W h e n the output is high, the P M O S transistor of inverter 13 is in a nonsaturated region and itsresistance is approximately

Rp =

1

2•p (VDD'{-V-rl,)

and when Vout = 0, the N M O S approximately

Rn= 26

1

2~ N (VDD--V'I'p)

,

....................

(17)

transistor can bc replaced by a resistor whose resistance is

. ...................

(18)

Therefore, correct expressions for thresholds V~ and Vu will be obtained when R in eqns (6) and (13) is replaced by R + R p and in eqns (11) and (14) by R+RN. Due to resistance Rp and R m the output voltage is changed by AVop i.e. AVoN (Fig. 3(b)) up to the beginning of the regenerative process. These changes increase when R decreases. If it is taken that V n = VI~D/2it is seen that AVop =

AVoN =

VDD 2[I+2/3p(VDD+V~)R]

VDD 211+23N(VDD--V~)R]

. ...................

(19)

....................

(2o)

2.2 Experimental results A Schmitt trigger is made of CMOS circuit type CD4007A. Oscillograms of transfer functions Vo',t(Vi,) and Vout(V~, at various values of resistance R and supply voltage Vt)D = 10V are shown in Figs 4(a) and 4(b). Voltage hysteresis increases when R decreases. For example, 10

9

-...

2

0

,

2

! 3

i t,

l 5

~

7

8

- - - - vin[v] o - R = %5 k f L

c - R=100.fI.

b - R= 360.1"1.

d -R=

oo

10

I I i I

,._=.I C

9

I'

--d

b

I

I

I

I

2

3

t,

I 5

6

7

- Vin [v] Fig. 4

Oscillograms of transfer characteristics of inverter as a function of resistance R at VI)D = 10V w h e n C M O S transistors are of type CD4007.

27

CMOS regenerative logic circuits continued from page 27

for R = 1.5 klq, V . = 1.3V and for R = 1001], V~t = 6.6V. Results of threshold measurements V~- and Vu as a function of resistance R at supply voltages VDo = 5V, VDD = 10V and VDD = 15V are shown in Fig. 5. The thresholds are symmetrical around the threshold voltage of inverter 12 (the CMOS circuit used had a threshold somewhat higher than VDD/2). If R > 4kl], the voltage hysteresis is lower than 1V regardless of the supply voltage value. . . . . . . .

\

VDD=I5V

*I DD

VDD:IO V

lt..~

R

--'CZ~]'~I

"~.,.,, 9

==

I/, I 0,5

I

1,5

2

2, 5

3

3~5 =

/.

/. 5

5

R [ks

Fig. 5 High V-~ and low V-~ threshold as a function of resistance R with supply voltage as parameter (experimental results).

3. NAND and NOR circuits N A N D and N O R regenerative logic circuits are obtained if, instead of inverter 11, unbuffered N A N D or N O R standard logic circuits (Fig. 6(a) and 6(b)) are used. As the transfer characteristic of N A N D and N O R circuits depends on the number and combination of active inputs, 3 the thresholds of the Schmitt triggers in Fig. 6 will also be a function of these

-

Xl "x2"-.xm

o) !

I

R xm;

-12_

b)

Hg. 6 Logic schemes NAND (a) and NOR Schmitt triggers (b). 28

parameters. Expressions V§ and Vu are obtained when constants i y and iP in eqns (6) - (11) are replaced by equivalent constants tsc and ice. Thus, for NAND circuits, as has been shown, 3 (correction factors a s and ap have been neglected), ir~e = f l N / ( m - k + l ) ,

tP~ = nile

and for N O R circuits fine = nflN,

flPe = f l P / ( m - k + l ) ,

where fin and tip are constants of one NMOS and one PMOS transistor respectively. Oscillograms of the transfer functions of a two-input NAND (a) and a three-input N O R Schmitt trigger (b) for combinations of active inputs at VDD = 10V and R = 750iq are shown in Fig. 7. It should be emphasised that buffered N O R and NAND logic circuits cannot be used for the circuit Fig. 6 due to their almost ideal transfer characteristic. W h e n the N A N D and N O R circuits are of same types for low resistance R the Schmitt

75O13.

7501"1. 1

1,011A 1/3CD/,069

t

113CD4025A

1/3CD4069

I(

2 "3

irl

E

t

f

2 0 2

3

t.

5

6

2

7

3

5

Vin [ v .]

6

?

--- V i n [ v ]

(a)

(b)

Fig. 7 0 s c i l l o g r a m s of transfer functions ofNAND (a) and NOR (b) circuits at VDD -----I0V for some combinations of active inputs.

trigger output may be permanently low or high regardless of the input voltage value. So, for example, if V',, < VT at V~, = 0, the output will be low (Volt = 0). Then the PMOS transistor (or transistors) of the input logic circuit and the NMOS transistor of the output inverter are ON and in the nonsaturated region. It is seen from condition V',,(Vi. = 0) > V~ VDD/2 that the condition (21) has to be fulfilled for normal circuit operation.

R > 2/3s3(VDD--VvN) 3flp~(Vt~D+4Vw/3)

- 1

= 2/3m(V~D--Vw)

Obviously, the minimum value of resistance R depends on the ratio constants are equal, R can be < 100 fl.

iP'--~

"

tmlflr~. When these 29

CMOS regene .rative logic circuits continued from page 29

4. Conclusion All circuits described can be realised with standard CMOS logic circuits. In that regard there is only one limitation on N A N D and N O R Schmitt triggers (Fig. 6), namely, that buffered N A N D and N O R logic circuits cannot be used. The input resistance and static power consumption are like standard CMOS circuits. The transfer characteristic of N O R and N A N D circuits depends on the number and combination of active inputs so that, unlike the inverter, it is not symmetrical around Vt, = VDD/2. Resistance R can have a value of hundreds of ohms to tens of ktq. But, increase of resistance R above 5klq causes a very small threshold change. Voltage hysteresis depends on supply voltage, as well as on resistance R, and can be regulated within several hundreds of mV to several V. So, for example, when CMOS transistors of type CD4007, for R = 250 II at VDD = 5V, voltage hysteresis is V~! = 4V, and at VDD = 15V it is Vn = 5V. When R = 6 k f / a n d VDo = 15 V then Vn = 0.4V. Such regenerative logic circuits with standard CMOS technology can be realised in the form of monolithic integrated circuits. Resistor R should then be replaced by an MOS transistor. 5.

References

[1] Schamis, Robert S., "Reduce system noise with CMOS circuits", Electronic Design, 25, 112-115 (1973). [2] Morris, R. L., "C-MOS Schmitt trigger can be more than an interface", Electronics, 16, 124-125 (1974). [3] D oki6, Branko L., "Influence of series and parallel transistors on DC characteristics of CMOS logic circuits", MicroelectronicsJournal, 13, 25-30 (1982). [4] Blandford, D. J., "A COS/MOS Schmitt trigger circuit", New Electron (GB), 8, 50-54 (1975). [5] Doki6, Branko L., "Contribution to theory and application of complementary MOS integrated circuits", Doctoral dissertation, Novi Sad 1982.. (Serbo-Croatien). [6] Nagaraj, K. and Satyam, M., "Novel CMOS Schmitt trigger", Electronics Letters, 17, 693-694 (1981).

30