Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology

Microelectronics Journal 72 (2018) 86–99

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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Quantification of the likelihood of single event multiple transients in logic circuits in bulk CMOS technology Nanditha P. Rao * , Madhav P. Desai Indian Institute of Technology Bombay, Mumbai, 400076, India

A R T I C L E

I N F O

A B S T R A C T

Keywords: Multiple transients Critical area fraction Quantification Soft error

It is well known that high-energy particle strikes on an integrated circuit can cause circuit errors. We quantify the fraction of a layout which is susceptible to multiple transients, through the notion of critical area fraction (CAF). We perform a 2D-study on a layout of 65 nm planar transistors to evaluate maximum values of CAF. We find that CAF can be as high as 1, that is, 100% of the layout area is vulnerable. Potentials of adjacent source/drain regions play a significant role in increasing the CAF and simple layout techniques do not reduce the CAF substantially. We confirm these observations through 3D simulations of inverter layouts. A key observation is that, CAF is high in the region of the layout which contains small gates. At the circuit-level, multiple transients not only cause multiple errors, they also merge to create wider transient increasing its capture probability. A circuit-aware placement of vulnerable gates and alternate latch designs may be required to alleviate the problem.

1. Introduction

of simple layout-based solutions to reduce the probability of multiple transients. Further, we discuss the circuit level implications of multiple SETs and propose possible circuit level approaches to reduce their likelihood. Critical charge is defined as the minimum charge collected by a logic gate to cause an observable difference in the output (greater than the threshold voltage). CAF is that fraction of the layout where a particle strike causes multiple logic gates to collect a charge greater than the critical charge. We evaluate the CAF by performing a device simulation based characterization study of the impact of a particle strike on representative layouts of 65 nm planar transistors under different operating conditions, particle LETs and device separations. We also try out simple layout techniques to see if it helps to reduce the CAF. This study is carried out on 2D and 3D layouts of 65 nm planar transistors. We first perform particle strike simulations on a 2D layout of 65 nm planar transistors which spans a distance of 30 λ (2 λ = 65 nm), and measure the charge collected in the source/drain regions under different operating conditions. We find that potentials of source/drain regions of adjacent transistors in the neighborhood of the strike play a significant role in multiple node charge collection. CAF values were as high as 1 at worst case voltages (source/drain of adjacent transistors biased high) and nearly 0.4 at best case voltage conditions (source/drain of adjacent transistors biased low). This means that, in the worst case, 100% of our layout is

When high energy particles such as alpha particles or neutrons strike a semiconductor device, they generate charge at the region of strike. This charge gets collected in the source/drain regions [1,2], resulting in a transient current known as single event transient (SET). The SET can propagate to flip-flops and flip the stored value resulting in bit-flips, known as soft errors. The architectural level model for soft errors is a probabilistic single bit-flip fault model [3–6]. Similarly, at the circuit level, an SET is modeled as a current injection into the drain of a single transistor [7,8]. If multiple transients or multiple bit-flips are to occur, these models will result in optimistic reliability estimates. Thus, it is important to quantify the extent to which a circuit/layout is susceptible to multiple transients. The phenomenon of a radiation-induced strike affecting multiple transistors has been studied in the past [9–12]. Studies carried out in 130 nm and 90 nm technologies by other authors [13,14], reveal that charge collection depends on particle energy, direction and device separation. Layout methods such as increased device separation, guardrings and a technique called Layout Design through Error-Aware Transistor Positioning (LEAP) are known to reduce charge collection [10,15,16]. In this paper, we quantify the fraction of a device layout which is susceptible to multiple SETs, by introducing the notion of a critical charge and critical area fraction (CAF). We study the effectiveness

* Corresponding author. E-mail addresses: [email protected] (N.P. Rao), [email protected] (M.P. Desai). https://doi.org/10.1016/j.mejo.2017.12.009 Received 8 April 2017; Received in revised form 3 December 2017; Accepted 12 December 2017 Available online XXX 0026-2692/© 2017 Elsevier Ltd. All rights reserved.

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Microelectronics Journal 72 (2018) 86–99

Fig. 1. (a) Simulated 65 nm NMOS device layout (zoomed in to show the 2 transistors). The arrows indicate particle strike locations assumed in our simulations. (b) Device 1 is shown with the mesh.

found to be vulnerable, that is, multiple transistors are surely affected. The implications of multiple SETs on a logic circuit can be quite serious. The SETs can propagate and consequently get captured in flip-flops causing multiple bit flip errors in a circuit. A key observation is that, CAF is high at small critical charge values. This implies that, multiple gates are more likely to be affected in the region of a layout which has small gates in close proximity. Simple layout techniques such as controlling the potentials of adjacent signal rails and adding guard-regions do not help reduce charge collection in multiple logic gates substantially. Similar observations with guardrings have been reported in the past [13,15] for 130 nm and 90 nm technologies.

To confirm the impact of layout techniques, we perform particle strike simulations on a 3D layout of two adjacent inverters in 65 nm technology. The layout methods chosen are similar to those in the 2D analysis: inverter layouts with different cell orientations to modify the potentials of adjacent signal rails, different positions of body contacts and layout with guard-regions are simulated. Our observations are similar to those in the 2D case; the reduction in charge collection due to these layout methods is not substantial. This implies that the problem cannot be entirely tackled at the local layout level and may need to be addressed using careful circuit-aware placement of vulnerable gates. For instance, approaches such as placing small gates in the same logic cone (to prevent multiple flip-flops from being affected) or placing a 87

N.P. Rao and M.P. Desai

Microelectronics Journal 72 (2018) 86–99 Table 2 Simulation parameters. Variable

Number of levels for the variable

Values taken by the variable

Voltage

2

Strike locations

15

Secondary particle LET Separation (between the edge of B1 and A2) Particle direction

6

Gate, source and drain voltage: 0 or Vdd x location: −0.1 μm, −0.05 μm, 0 μm …. 0.75 μm, 0.8 μm (1,3,5,7,9,11) MeV cm2 /mg

3

0.22 μm, 0.3 μm, 0.5 μm

5

2, 30, 45, 60, 90◦

simulation results with 2D and 3D experiments in 65 nm. Circuit level implications of multiple SETs are discussed in Section 7. We summarize and conclude the paper in Section 8. 2. Charge generation and experimental setup When a neutron strikes the silicon substrate, several nuclear reactions occur which result in secondary ions such as, 28 Al and 25 Mg [2,14]. The energy of these ions is typically expressed in terms of linear energy transfer or LET (MeV-sq.cm/mg) and is defined as the energy that a particle transfers per unit length. Nuclear libraries such as: LA150 library, JENDL-4.0, ENDF-B6, HETC, model these reactions and calculate the secondary ion distribution. We use the ENDF/B-VI (Evaluated Nuclear Data File) library and the JANIS tool (Java-based Nuclear Information Software) [17] to determine the energy distributions of secondary ions for a given neutron energy. The LET of secondary ions is typically known to range from 1 to 10 MeV-sq. cm/mg [14].

Fig. 2. 65 nm NMOS device plots: (a) log (Drain current) (A/μm) versus Gate source voltage (Vgs ) plot for Drain source voltage (Vds ) of 1.2 V. The plots obtained from our simulation (Sim) are shown along with the specifications (Spec) [18]. (b) The same plots are shown for a drain source voltage (Vds ) of 0.1 V.

small gate adjacent to a large gate may reduce the probability of multiple SETs getting generated. It must be noted that even if the gates are placed in the same logic cone, multiple SETs might merge and produce an SET of larger width, thus increasing its possibility of getting captured. So, existing error tolerant latch designs may need to be revisited to handle such scenarios. The rest of this paper is organized as follows. We explain the overall experimental methodology in Section 2. In Section 3–6 we present the

Table 1 NMOS device structure details and doping concentrations calibrated to meet STM 65 nm specifications. Device parameter

Value

Gate length Effective oxide thickness- SiON Polysilicon gate height Spacer width Gate pitch STI depth Source/drain extensions depth Source/drain region depth Halo doping (Boron) Source/drain extension doping (Arsenic) Source/drain doping (Arsenic)

60 nm [18] 1.2 nm [21] 110 nm 45 nm 220 nm 350 μm [21] 25 nm 43 nm 2e18 cm−3 8e18 cm−3 1e20 cm−3

Fig. 3. Collected charge in the source/drain regions (B1 and A2) of the two adjacent devices, for a particle strike in between B1 and A2 at different voltage conditions.

Table 3 Critical charge values of a STM 65 nm Inverter standard cell (INVX2) and NAND standard cell (NANDX2).

88

Wp ∕Wn

Qcrit of INVX2

Qcrit of NANDX2

6λ∕3λ 10λ∕5λ 12λ∕6λ 20λ∕10λ 30λ∕15λ

5 fC 6 fC 8 fC 15 fC 25 fC

12 15 18 35 45

fC fC fC fC fC

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Microelectronics Journal 72 (2018) 86–99

array of N-type Metal Oxide Semiconductor (NMOS) transistors in 65 nm technology, which represent the transistors situated on the boundary of adjacent standard cells. We perform particle strike simulations and measure the charge collected in the transistors. We study the role of different device and particle parameters on multiple node charge collection. We also quantify the part of the layout which is susceptible to multiple transients and study the impact of simple layout techniques on reducing multiple node charge collection.

Fig. 4. Output of the inverter showing the change in the voltage for different charge injections. (Pink- 2 fC charge injection, Black- 4 fC charge injection, Blue- 6 fC charge injection). (For interpretation of the references to colour in this figure legend, the reader is referred to the Web version of this article.)

Fig. 7. Critical area fraction for different critical charge values and voltage conditions for a particle strike of LET = 11 MeV-sq. cm/mg. Incident angle is 90◦ to the substrate.

Fig. 5. Example device layout to define critical area fraction.

Fig. 8. Critical area fraction for different critical charge values and voltage conditions for a particle strike of LET = 5 MeV-sq. cm/mg. Incident angle is 90◦ to the substrate.

Fig. 6. Critical area fraction for the worst case voltage condition for different particle LETs and separation.

In Silicon, every 3.6 eV of energy lost by the secondary ion results in the creation of one electron hole pair (LET of 1 MeV cm2 /mg = 0.01 pC/μm). In other words, it creates a charge track in Silicon. After obtaining the LET of the secondary ion, we calculate the length and radius of the charge track using a tool called TRIM (Transport Ions in Matter). We simulate the impact of this charge track on the device layout using Sentaurus Device and measure the transient current (and charge) collected at the source/drain regions. 3. Impact on multiple transistors at 65 nm: 2D analysis In this section, we discuss the impact of a neutron induced strike on 2D layouts constructed in the 65 nm planar technology. We choose an

Fig. 9. 2D analysis: Critical area fraction for different incident angles and particle LETs.

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source voltage (Vds ) of 1.2 V and 0.1 V (these are the maximum and minimum voltage values for the technology). Geometry and the doping concentrations of the device after calibration, are shown in Table 1. Another key parameter for the device simulation is the size of the mesh. We chose the mesh refinement size such that the source, drain, channel and well contact regions are tightly meshed as shown in the figure. The 2D device had a total of 14000 elements after meshing. 3.2. Simulation models and parameters for device simulation Particle strike is modeled as a cylindrical column of charge with a Gaussian radial distribution. Its impact on the device is simulated using the ‘Heavy Ion’ module in Sentaurus Device [22]. Mobility degradation effects due to impurity scattering, carrier-carrier scattering, high electric fields and mobility degradation at the siliconinsulator interface are specified using the physics models of Sentaurus Device such as: “DopingDependence”, “CarrierCarrierScattering”, “HighFieldsaturation” and “Enormal” respectively. Generation and recombination processes of electron-hole pairs are modeled using “Auger” and “SRH” recombination models. Quantization effects are modeled using the “VanDort” model. These physics models are consistent with the models used in Refs. [2,23]. We study the impact of device/particle parameters on charge collection by varying the particle LET, incident direction, device separation and potentials. In Table 2, we show the values of these parameters assumed in our study. We assume 15 strike locations uniformly across the device layout. When the particle strikes the STI region, the cylindrical column of charge is assumed to start from a point below the STI and not inside it (see Fig. 1). This is because the electron hole pairs are assumed to recombine inside the STI [24,25] and hence, will create no charge inside. Considering all possible combinations of these variables will result in nearly 17000 simulation cases (64 cases while varying the voltages of the gate, source and drain of the two transistors * 15 strike locations * 6 LETs * 3 separations for a given particle direction). To limit the number of simulation cases, we identify two voltage combinations called the worst case and best case voltage conditions described in the next section. Only these voltage combinations are then used to simulate while varying the other parameters. There are still about 2700 (15 strike locations * 2 voltage combinations * 6 LETs * 3 separations * 5 angles) simulation cases and hence they are run in the 2D mode. Each 2D simulation took nearly 15 min to run. For each simulation, we extract the charge collected at the four source/drain regions for the lay-

Fig. 10. Transient current plots for a particle strike of LET 11 MeV-sq. cm/mg occurring midway between the 2 NMOS devices (on the well contact), at different angles of incidence (2◦ –90◦ ).

3.1. Device construction and validation In Fig. 1, we show the layout of two NMOS devices constructed as per the 65 nm STMicro (STM) technology requirements [18] using the tool- Sentaurus Structure Editor (SDE). In the figure, A1, B1 and A2, B2 are the source/drain regions of the two devices respectively. Devices are separated by a shallow trench isolation (STI) and a well contact (W). The doping concentrations of source or drain regions, source/drain extension regions (shallow source/drain regions underneath the gate) and halo regions (highly doped p-type regions adjacent to the source/drain to reduce short channel effects) [19,20] are calibrated to meet the on/off current (Ion and Ioff ) and sub-threshold slope requirements of the STM 65 nm data. These specifications require an Ion of 700 nA/μm, Ioff of 1 nA/μm and a sub-threshold slope (SS) of 89 mV/decade. In Fig. 2, we show a plot of the drain current (logarithmic scale) versus gate to source voltage (Vgs ) of our device (denoted by Sim) versus the STM specifications (denoted by Spec) [18], for a drain-

Fig. 11. Layout of three 65 nm NMOS transistors. Arrow indicates the particle strike location.

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Fig. 13. Layout 1: Layout of two inverters with adjacent signal rails B and C. Dashed rectangle indicates the 2 NMOS transistors simulated in 2D. Particle strike is assumed to occur between B and C. The highlighted circle indicates that two signal rails of the inverters are adjacent to each other and to the strike location.

Fig. 12. (a) Charge collection in the three source/drain regions due to a particle strike of LET = 11 MeV-sq. cm/mg. Dotted line indicates the strike location. High voltage is Vdd , low voltage is 0 V. (b) Transient current plots in the three transistors when the respective source/drain regions are biased high.

out shown in Fig. 1. The entire process from simulation to measurement of charge collection is automated using a set of python scripts. 3.3. The role of potentials on multiple node charge collection: picking the worst case/base case voltages

Fig. 14. Layout 2: Layout of two inverters with outputs at B and D. Particle strike is assumed to occur between B and C. The highlighted circle indicates that there is only one signal rail B adjacent to the strike location and the other is a power/ground rail.

Let us consider the case where a particle strike occurs midway between the two transistors on the well contact. We vary the potentials of the gate, source and drain regions of both the transistors and measure the collected charge. Throughout this paper, high voltage means Vdd of 1.2 V and low voltage means 0 V. One of the key findings is that, when the voltage of the adjacent source/drain nodes B1 and A2 of the two transistors is high, it results in maximum charge collection in “both” transistors. We call this the ‘worst case’ (WC) voltage condition. In this case, the gates G1, G2 were biased high and A1, B2 were biased low. This is plotted in Fig. 3. Charge collected in a source/drain node is substantially lower when that node is biased low. For instance, when A2 and B1 are biased low, the charge in the respective nodes reduces substantially. We then bias all the device terminals to a low voltage and this results in the least amount of charge collection in both the transistors. We call this the ‘best case (BC) voltage condition’. It is important to note that, to arrive at the worst case and best case voltage conditions, we measure the charge collection in ‘more than one’ transistor. We see a factor of 5× variation between the worst case and best case charge collection. Thus, that potentials of the source/drain regions play an important role in the amount of charge collected in multiple transistors. For the rest of our analysis, we consider only the worst and best case voltage scenarios.

4. Analysis: quantifying the extent to which multiple transistors are affected In this section, we introduce the notion of critical charge for a logic gate. Based on this, we quantify the extent to which multiple logic gates are affected, through the notion of ‘critical area fraction’. We calculate the critical area fractions for the 2D layout for different device separations, particle LETs and angles of incidence. 4.1. Critical charge and critical area fraction We introduce the notion of ‘critical charge’ or charge threshold for a logic gate. It is defined as that charge which when exceeded, causes an observable difference in the output, which is greater than the threshold voltage Vt . It may result in a glitch in a logic gate or a flip in the output in the case of a flip-flop. We consider a single standard cell inverter in 65 nm technology, which has a threshold voltage Vt of 0.4 V. We perform a transient simulation in SPICE, in which the output of the inverter is held high and we inject charges of different magnitudes to 91

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Microelectronics Journal 72 (2018) 86–99

to measure the charge collected at the signal nodes of both the logic gates. The fraction of strikes (or fraction of the layout) which results in both logic gates (represented by the two transistors in 2D) collecting a charge greater than their respective critical charge is calculated as the critical area fraction. Suppose that the critical charge is 30 fC. If the particle strike anywhere between locations A and B in the layout results in charge collection greater than 30 fC in both the devices (source or drain regions), we calculate CAF in terms of multiple node charge collection (MNCC) as follows: .CAF =

Area susceptible to MNCC Total area where strikes occur

(1)

In other words, we define CAF in terms of the number of strikes as follows. CAF =

No of strike locations leading to MNCC Total number of strikes

(2)

In this example of Fig. 5, we see that evaluating equation (2) gives us a CAF of 0.66 (12 out of 18 strike locations between A and B result in multiple node charge collection). This means that particle strikes occurring in 66% of the layout will result in charge collection greater than the critical charge in ‘multiple’ logic gates. If the fraction is large, it means that strikes in large parts of the layout will affect multiple gates.

Fig. 15. Layout 3: Layout of two inverters with outputs at A and D. Particle strike is assumed to occur between B and C. The highlighted circle indicates that there is no signal rail adjacent to the strike location.

the drain of one of the transistors in the inverter. We then find out the charge which causes the output of the gate to change by a magnitude equal to the threshold voltage. This charge is the critical charge for the inverter. Similarly, we inject charges of different magnitudes on one of the four transistors of the 2-input NAND gate, and observe the change in its output. In Table 3, we show the critical charge for different sizes (in terms of the width of the PMOS Wp and width of the NMOS Wn ) of an inverter standard cell and a NAND standard cell. In Fig. 4, we show the waveforms for the output of the inverter for different charge injections. Through this experiment we get an idea about the range of critical charge values for a standard cell in 65 nm. We find that charges as small as 5 fC can cause the output of the gate (in this case the inverter) to glitch in 65 nm technology. Having defined critical charge, we now introduce the notion of ‘critical area fraction’ (CAF). Given a particle strike, we find out the probability that multiple logic gates are affected, that is, the probability that they collect more than their critical charge. We call this the critical area fraction, and its values can range from 0 to 1. In other words, it is the fraction of a layout where a particle strike will affect multiple logic gates. If multiple logic gates are to be affected, then multiple transistors which are part of these logic gates are certainly going to be affected. So, we consider the two NMOS transistors of Fig. 5 which are assumed to be part of two adjacent inverters, each having a certain critical charge. In this layout, S, G, D stand for source, gate, drain of the transistor respectively and the devices are separated by an STI. We assume a set of particle strikes which are uniformly distributed across the layout as shown in the figure. For each strike location, we perform a simulation

4.2. Critical area fraction calculation from the 2D simulations We now perform particle strike simulations with all possible combinations of the variables described in Table 2 for the worst case and best case voltage conditions on the layout shown in Fig. 1. We measure the charge collected in the two transistors and calculate the critical area fraction for the layout. The two transistors are assumed to be part of two adjacent inverter standard cells. The critical charge for the simulated layout was found to be 30 fC/μm from the experiment described in Section 4.1. We should note that our definition of critical charge is inclusive of the charge collected by the NMOS and the PMOS. So, if we were to consider just the NMOS transistors (as done in our study), the critical charge will be even lesser. To calculate the CAF, we find out the fraction of the layout area where a strike can cause the two transistors to collect more than 30 fC/μm. Since we are estimating CAF for logic gates using the two transistors in 2D, the estimated CAF can be a slight overestimate. In Fig. 6, we plot the critical area fraction at different particle LETs, for the worst case voltage condition. The three plots in the figure correspond to three device separations S = 7 λ, 9 λ and 15 λ, (where 2 λ = 65 nm and the separation is measured between the edge of B1 and A2). At the best case voltage condition, the CAF was found to be 0 at all particle LETs for this critical charge. If we were to vary the critical charge from say, 5 fC/μm to 45 fC/μm, the critical area fractions for these charge thresholds would be different. In Fig. 7, we show a plot of

Table 4 Critical area fraction for the three layout scenarios for a particle strike at 90◦ in between the two inverters. The simulated layout had a critical charge of 30 fC. The CAF values corresponding to it are highlighted. Charge threshold

5 fC 10 fC 15 fC 20 fC 25 fC 30 fC 35 fC 40 fC

11 MeV-sq.cm/mg

7 MeV-sq.cm/mg

3 MeV-sq.cm/mg

Layout 1

Layout 2

Layout 3

Layout 1

Layout 2

Layout 3

Layout 1

Layout 2

Layout 3

1 1 1 1 1 0.71 0.5 0.31

1 1 1 1 1 0.71 0.5 0.25

1 1 1 1 1 0.62 0.44 0.25

1 1 1 1 0.56 0.25 0 0

1 1 1 0.67 0 0 0 0

1 1 1 0.67 0 0 0 0

1 0.71 0.25 0 0 0 0 0

1 0.1875 0 0 0 0 0 0

1 0 0 0 0 0 0 0

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Fig. 16. n + guard-region in between the two NMOS devices, tied to Vdd .

Table 5 Impact of guard-region (GR): CAF values obtained at the worst case voltage conditions for Qcrit = 30 fC. LET (MeV-sq. cm/mg)

No GR

n + GR

p + GR

1 3 5 7 9 11

0 0 0 0.1875 0.5 0.75

0 0 0 0.25 0.5 0.75

0 0 0 0 0.0625 0.375

the critical area fractions for different critical charges and voltage conditions for a particle LET of 11 MeV-sq. cm/mg. In Fig. 8, we show these plots for a particle LET of 5 MeV-sq. cm/mg. These plots are obtained for a particle incident at 90◦ to the layout (vertically incident). In Fig. 9, we show the CAF values for different angles of incidence for a critical charge of 30 fC. We find that the CAF is heavily dependent on the voltages. The worst-case and best-case CAF values are widely different. At high particle LETs, the worst case CAF is 1, which means that particle strike in 100% of our layout (layout which spans a distance of 30 λ) affects multiple logic gates. Even at device separations as large as 7 λ, the best case CAF values can go up to 0.4. So, even in the best case conditions, particle strikes in as much as 40% of the layout can affect multiple transistors/logic gates. Further, CAF values are large at small critical charge values and reduce at higher charge thresholds. Thus, if there is a region of the layout which consists of logic gates having small charge thresholds, then multiple gates are more likely to be affected in that region. This is interesting because, if such a scenario is avoided, then the probability of multiple transients can be potentially reduced. Also, CAF increases as the angle of incidence reduces. This means that, when a particle is incident at an angle, the influence of a particle strike lasts over larger distances affecting multiple transistors. The transient current plots for a particle of LET 11 MeV-sq. cm/mg incident midway between the two devices at different angles of incidence (2–90◦ ) is shown in Fig. 10.

Fig. 17. Transient current plot at LET = 7 MeV-sq. cm/mg, showing the impact of guardregions.

simulate a particle strike of LET = 11 MeV-sq. cm/mg which is assumed to occur in between the first two devices (midway between B1 and A2 on the well contact). We measure the charge collected in all the three source/drain regions, when the respective terminal is biased high/low and plot it in Fig. 12(a). The charge collected in the source/drain of the nearest two transistors, that is, at B1 and A2 is at least four times higher than the charge collected in device 3 (for instance, in A3). This is also indicated by the transient current plots in Fig. 12(b). Thus, we can say that the nearest two transistors are the most affected, and the ones farther away are less likely to be affected due to a particle strike. So, we limit our study to two transistors/logic gates throughout this paper. 5. Impact of layout techniques: 2D analysis

4.3. Is it sufficient to consider just two transistors for the study?

In this section, we explore a few simple layout techniques to reduce charge collection in multiple transistors. We modify the transistor orientations to control the potentials of adjacent signal rails and try adding

To understand the impact of a particle strike beyond two transistors, we consider a layout of three NMOS transistors as shown in Fig. 11. We 93

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Fig. 18. (a) and (b) 3D layout of two inverters in 65 nm technology: top and side views respectively. Strike locations are indicated by yellow circles P, M, N. Body contacts are denoted by B1 to B4. This layout is called ‘Orientation-1’. (c) Cross section of the PMOS and NMOS transistors which are part of the 3D layout. (For interpretation of the references to colour in this figure legend, the reader is referred to the Web version of this article.)

Fig. 19. 3D: Three layout configurations with different number of signal rails adjacent to the strike location.

guard-regions to see if charge collection in multiple transistors reduces.

tials of adjacent signal rails. Our goal is to reduce the CAF which is a measure of the extent to which multiple logic gates are affected. We modify the layout such that, amongst the neighboring source/drain nodes, there is at most one signal rail and the rest are power/ground rails, so that only one signal rail is affected. We consider three possible ways of doing the layout of a pair of inverters, as shown in the schemat-

5.1. Reducing the number of adjacent signal rails Since the potential of adjacent source/drain nodes has a significant impact on multiple node charge collection, we try to control the poten94

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Fig. 20. 3D inverter layout with three different orientations of body contacts.

ics in Figs. 13–15. We call these layouts as ‘Layout 1’, ‘Layout 2’ and ‘Layout 3’ respectively. When a particle strike occurs in between the two inverters in ‘Layout 1’, maximum charge will be collected in the signal rails B and C, when they are high for two reasons: a) since they are adjacent to the strike location and b) since the signal rails which are at a high potential collect large amounts of charge as observed earlier. Thus the outputs of both inverters are affected. In ‘Layout 2’, we take the outputs of the inverters at B and D. So, for the same strike location, only one signal rail B adjacent to the strike location is affected, thus affecting only a single logic gate. In ‘Layout 3’, we take the outputs of the inverters at A and D. Since the separation between the outputs is large, we expect that the charge collected in the signal rails or the outputs will be least in this case, thus affecting the two gates to a smaller extent. So, we expect that the CAF will reduce with Layout 3. We evaluate CAF for the three layouts, by simulating the two NMOS transistors highlighted in the figures (dashed rectangle), in the 2D mode. We assume a particle strike in between the two inverters (at 90◦ ) and we hold the outputs of the inverters high (worst case). We then measure the charge at the outputs of the inverters and eval-

uate the CAF. We ignore the charge collected in the power/ground rails. In Table 4, we show the CAF values of the three layouts obtained by measuring the charge collected in the signal nodes, and highlight the CAF values at Qcrit = 30 fC. The CAF values for Layout 3 is the least across all critical charge values, and shows significant improvement at lower particle LETs. But the CAF is still substantial at high particle LETs with Layout 3. Thus, changing the transistor orientation to control the potential of adjacent signal rails helps only at lower LETs since the range of impact of the particle strike (radius of the charge track) is low at lower LETs. 5.2. Impact of guard-regions Guard-regions or guard-rings are structures typically constructed around transistors using an n+ diffusion (tied to the high voltage rail Vdd ) in a p-substrate or a p + diffusion (tied to ground) in a n-well. This setup is expected to collect the extra charge generated due to the particle strike. The depth of these diffusion regions is typically almost equal to that of the source/drain regions [26]. Experimental results performed on 0.35 μm technology devices show nearly 30% reduction in charge collection due to guardrings as reported by other authors [26]. However, the impact of guard-regions in 130 nm and 90 nm technologies is not found to be substantial as discussed by the authors in Refs. [13,15]. We explore the impact of guard-regions on our 65 nm 2D NMOS device layout. We modify the layout to have body contacts on either sides of the devices, with an n+ guard-region (GR) in between the two devices doped with Arsenic with a concentration of 5e18 cm−3 . It is tied to high voltage (Vdd ) as shown in Fig. 16. This creates a reverse biased p-n junction which is expected to collect the electron hole pairs

Table 6 Charge collected at the inverter outputs for the three layout configurations (LET = 11 MeV-sq.cm/mg strike). Strike location

Layout 1 Layout 2 Layout 3

Q-Inv1 (fC)

Q-Inv2 (fC)

‘M’

‘N’

‘P’

‘M’

‘N’

‘P’

0.481 0.465 0.46

1.25 1.22 0.72

0.498 0.503 0.434

0.536 0.521 0.51

1.24 0.853 0.825

0.52 0.422 0.417

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nm technology. The layouts chosen are: inverter layouts with different cell orientations, different positions of body contacts and layout with guard-regions. 6.1. Reducing the number of adjacent signal rails In Fig. 18, we show a 3D layout of two adjacent inverters whose size is 12 λ∕6 λ and the separation between the two inverters is 7 λ (where 2 λ = 65 nm). This 3D device was constructed with similar doping concentrations as that of the 2D device. After meshing, the layout had a total of 292000 elements. We simulate particle strikes for the same layouts that were simulated in 2D: Layouts 1, 2 and 3, whose schematics were shown in Figs. 13–15 and whose layouts are shown in Fig. 19. We do not perform a ‘critical area fraction’ evaluation, since it involves particle strike simulations across numerous parts of the layout, which are time consuming in 3D (a single simulation takes nearly 12 h). Hence, we assume three particle strike locations, indicated by ‘P’, ’M’and ‘N’, which stand for PMOS strike, mid-strike and NMOS-strike respectively as shown in Fig. 18. We simulate the worst case voltage condition, that is, outputs of both the inverters are held high and we measure the charge collected at both the inverter outputs. In Table 6, we report the charge collected at inverter 1 output (Q-Inv1) and inverter 2 output (Q-Inv2) for a particle LET of 11 MeV-sq. cm/mg. Layout 3 reports the least charge collection as expected, because the outputs of the inverters are farther away from the strike location. Layout 2 reports lesser charge collection compared to Layout1 for Inverter 2 output, again as expected, for the

Fig. 21. Charge collection at the two inverter (Inv1 and Inv2) outputs for a particle strike of LET 11 MeV-sq. cm/mg, with the three positions of body contacts: Orientation 1 (O1), Orientation 2 (O2) and Orientation 3 (O3).

generated due to the particle strike. Alternately, we also explore the impact of a p + guard-region tied to ground (nothing but an additional body contact). We simulate a particle strike in between the two devices and measure the charge collected in the source/drain regions. From the charge values, we calculate the CAF for all particle LETs. We report these values in Table 5. We find that p + guard-region (additional body contact) helps reduce the critical area fraction to a great extent. With the n+ guard-region, we find that the reduction in CAF is less. This is probably because it collected just electrons. The transient current plots measured at the drain of the first transistor are shown in Fig. 17 for a particle LET of 7 MeV-sq. cm/mg. These plots indicate a slight reduction in the charge collection (charge is area under the transient current curve) with a p + guard-region. Thus, from the 2D analysis we find that, a particle strike can affect multiple transistors (especially the nearest two), and the susceptible area is large: impact can spans a distance of nearly 30 λ. Potentials of adjacent source/drain regions play a significant role in multiple node charge collection, which gets worse when the particle is incident at an angle to the substrate. Simple layout techniques such as increasing the distance between the signal rails and adding guard-regions do help reduce charge collection, but the reduction is not substantial especially at higher particle LETs. 6. Impact of layout techniques: 3D analysis In the 2D analysis, we saw that simple layout methods do not help reduce charge collection substantially. To confirm these conclusions, we perform 3D simulations of a layout of two adjacent inverters in 65

Fig. 22. Charge collection at the two inverter (Inv1 and Inv2) outputs for a particle strike of LET 5 MeV-sq. cm/mg, with the three positions of body contacts: Orientation 1 (O1), Orientation 2 (O2) and Orientation 3 (O3). 96

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Fig. 25. 3D analysis: Impact of guard-regions (GR) and additional body contacts. Charge collected in Inverter 1 (Inv1) and Inverter 2 (Inv2) is plotted for different strike locations.

Fig. 23. Transient current plots of Inverter 1 output for the three positions of body contacts (indicated by body1, body2, body3). The plots are for a particle strike of LET 5 MeV-sq. cm/mg at location ‘N’.

Fig. 26. 3D analysis: Transient current plots at the output of Inverter 1, with and without the guard-region (GR) and additional body contact. The plots are for a particle strike of LET 5 MeV-sq. cm/mg at location ‘N’.

Fig. 24. 3D layout of two inverters in 65 nm technology with guard-region (GR) in between.

same reason mentioned above. However, the reduction in charge is not substantial.

strike. These plots also indicate that the position of the body contacts does not have much impact on the transient current.

6.2. Impact of positions of body contacts 6.3. Impact of guard-regions We now study the impact of different positions of the body contacts to see if its proximity to the signal rails has any impact on charge collection. The layout with body contacts B1 to B4 positioned as shown in Fig. 18, is called ‘Orientation-1’ (O1). When all four body contacts are positioned in between the two inverters (adjacent to B and C), we call the layout ‘Orientation-2’ (O2). When the body contacts are on either sides of the two inverters (either sides of A and D), we call the layout ‘Orientation-3’ (O3). The three positions of the body contacts are shown in Fig. 20. Simulations are performed for the three particle strike locations P, M and N, for each of these layouts. In Figs. 21 and 22, we present the charge collected at the outputs of the two inverters, for the three strike locations at particle LET of 11 MeV-sq. cm/mg and 5 MeV-sq. cm/mg respectively. We see that the position of body contacts does not have much impact on charge collection. Transient current plots of Inverter 1 output for the three layouts are shown in Fig. 23 for a 5 MeV-sq. cm/mg

We modify the 3D layout to have body contacts on either sides of the devices, with a guard-region in between the two devices. A p + guardregion (GR) is tied to ground for the PMOS transistor in the N-well and an n+ guard-region is tied to high voltage (Vdd ) for the NMOS transistor in the p-substrate, as shown in Fig. 24. This setup creates a reverse biased p-n junction which is expected to collect the extra electron hole pairs generated due to the particle strike. We also explore the possibility of an n+ guard-region tied to Vdd for the PMOS transistor and a p + guard-region tied to ground for the NMOS transistor (this is nothing but an additional body contact). We perform particle strike simulations at the three strike locations at particle LETs of 5 MeV-sq. cm/mg and 11 MeV-sq. cm/mg. In Fig. 25, we present the charge collected at the two inverter (Inv1 and Inv2) outputs (taken at B and C) with and without the guardregion/additional body contact. We see that both the guard-region and 97

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Fig. 27. Logic gates G1 to G6 are shown with their critical charges. Black circle is the particle strike location. (a) Transients are created in small gates belonging to different logic cones. (b) Scenario of small gates adjacent to large gates results in a single transient at the small gate. (c) Transients are created in adjacent small logic gates belonging to the same logic cone.

additional body contact result in an insignificant amount of reduction in the collected charge. This can also be observed from the transient current plots in Fig. 26. Similar observations about guardbands are made in Refs. [13,15] for 90 nm and 130 nm technologies. The authors report that guardbands reduce charge collection only in PMOS. This is because, the guard-band cannot reduce the diffusion effects in NMOS which is the main cause of charge sharing [15]. Overall, from the 3D analysis we find that, simple layout techniques such as increasing the distance between the signal rails, changing the positions of the body contacts and adding guard-regions do help reduce charge collection, but the reduction is not substantial. Thus, multiple logic gates (especially the nearest two) are almost surely affected. This conclusion is similar to that found from the 2D analysis.

Fig. 28. (a) Schematic of 3:8 decoder which shows U19 and U26 connecting to U24 and reg7 (b) SETs on U26 and U19 merge to produce a wider SET on U24.

in Fig. 27(c), so that multiple flip-flops do not get affected. In other words, the layout will need to be aware of the structure of the circuit, and the fraction of the layout which has small gates next to each other, should be as small as possible. It should be noted that, even if we limit the gates to the same logic cone, two SETs can merge and produce an SET of larger width at the input of a flip-flop (especially if the paths are unequal). We demonstrate this using a simulation of a 3:8 decoder example shown in Fig. 28(a). The highlighted gates U19 and U26 connect to U24 and flip-flop reg7. From the waveforms in Fig. 28(b), we observe that the SETs on U19 and U26 merge to produce a wider SET on U24. This can increase the probability of the flip-flop capturing the SET. So, existing error tolerant latch designs may need to be revisited to handle such scenarios. To sum up, multiple SETs are quite likely and will have serious implications on circuit reliability unless careful circuit-aware layout design or other circuit/system level approaches are implemented.

7. Discussion: circuit level implications We have seen that simple layout techniques do not help to reduce the CAF substantially. Further, we found that the fraction of a layout consisting of small gates in close proximity is likely to be more susceptible to multiple SETs. This implies that a circuit-aware layout design approach may be helpful to reduce the likelihood of multiple transients. A few studies in Refs. [27–30] suggest such circuit-aware approaches, in which they alter the standard cell placement based on their logic cones, adjacent cell sensitivity etc., to reduce the multiple error rate. We propose an alternate cell placement method which is based on our observation that the multiple SETs are generated when two small gates (gates with small critical charge) are in close proximity and belong to different logic cones. This will result in an SET in both the gates, which can propagate and affect multiple flip-flops, as shown in Fig. 27(a). So, we propose that the cell placement be modified such that small gates do not lie in close proximity. The best case situation is when there are two large gates next to each other (critical charge is large) or a large gate next to a small gate as shown in Fig. 27(b). In such a case, an SET may not get generated or will get generated in only one gate respectively. If this is not possible, they should belong to the same logic cone as shown

8. Conclusion We have performed a device simulation based characterization to quantify the part of the layout where a particle strike can affect multiple logic gates, by introducing the notion of a critical area fraction. We performed our study on a 2D layout of adjacent 65 nm planar transistors which spans a distance of nearly 30 λ. We find that CAF can be as high as 1, which means that 100% of the simulated layout area is vulnerable to multiple transients. Since the range of impact is large, 98

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multiple transistors are surely affected. Simple layout techniques do not reduce the CAF substantially; the nearest two logic gates are certainly affected. We confirm these observations by performing 3D simulations of inverter layouts. A key observation is that, CAF is high in the region of the layout which consists of multiple small gates in close proximity. The circuit level implications of multiple SETs can be quite serious unless enough precautions are taken. Multiple SETs in the same logic cone can merge to create a wider SET increasing its possibility of getting captured. Thus, approaches such as, careful circuit-aware layout placement of vulnerable gates and alternate error tolerant latch designs may be needed to alleviate the problem.

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