- Email: [email protected]
Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology
Microelectronics Reliability 88–90 (2018) 965–968
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology
T
N. Maciela,*, E.C. Marquesa, L.A.B. Navinera, H. Caia,b a b
Télécom ParisTech, Université Paris-Saclay, 46 Rue Barrault, Paris, France National ASIC System Engineering Center, Southeast University, Nanjing 210096, China
A R T I C LE I N FO
A B S T R A C T
Keywords: Single-event transient 28 nm FDSOI Dynamic comparator Reliability analysis
The comparator is a key component of analog to information converters. The speed and the accuracy of the comparator determine the conversion quality. As device-scaling enters in the nanometer dimensions, the circuit becomes more susceptible to temporary faults. In this work, Single-Event Transient effects on a dynamic comparator in 28 nm FDSOI CMOS technology are investigated. The sensitivity of the circuit is simulated combined with the polarity of differential inputs and the working phases of the comparator. Moreover, the body-bias and the transistor channel modulation impact were analyzed. The minimum charge Qc to produce incorrect outputs is determined according to the striking time and the transistor involved by the strike. Results show that circuit vulnerability is a function of the individual transistor, the striking time, body-bias and the transistor channel modulation. Moreover, the minimum Qc value increases by 4.3% and 12.4% using the poly technique and the flip-well with back-bias configuration, respectively.
1. Introduction The amount of information to transmit or process is increasingly growing [1]. Compressed sensing (CS) theory, which merges data acquisition and data compression processes, appears to be an efficient solution to deal with this phenomenon [2]. CS approach allows to replace traditional Nyquist based analog-to-digital converters (ADC) by analog to information converters (AIC) and significantly reduce the number of necessary measurements [3]. Nevertheless, the low number of acquired measurements makes the reliability of AIC become a major issue. The comparator is a pivotal component of an AIC. Its speed, accuracy, and power consumption determine the conversion efficiency. Therefore, high quality-demand, low power or critical applications as cognitive radio, aerospace, and radar sensors require highly effective comparators [4]. Comparators can be classified into static or dynamic depending upon whether its operation is controlled by clock signal [5]. Dynamic comparators [6] have been proposed to overcome high-power consumption and low-speed issues generally presented by static comparators [7]. Moreover, with down-scaled device dimensions to nanometers, circuits become increasingly susceptible to transient disturbances named Single Event Transient (SET) [8]. SET results of deposited charge when ionizing energetic particles hit a sensitive region of the *
circuit [9]. The SET effects of a dynamic comparator were evaluated in [10] and [11] for 90 nm and 65 nm CMOS bulk technologies, respectively. The results show that circuit vulnerability strongly depends on technology, topology, and individual transistor currents. As many others, the works above do not deeply explore the relationship between the effect of a given SET and the striking time or the transistor concerned by that SET. However, it could be interesting to assess how striking time impacts the minimal SET's charge needed to change the comparator's output. Likewise, information either SET in different transistors/locations leads to different impacts on the comparator's output would enable implementation of effective reliability improvement strategies. On the other hand, fully depleted silicon-on-insulator (FDSOI) technologies are attractive due to their high-speed/low-power features [12] and its reliability has been extensively studied [12–14]. Nonetheless, to the best to our knowledge, SET effects on FDSOI based comparators have not yet been reported. In this work, SET effects on a 28 nm FDSOI dynamic comparator are investigated. The critical charge is determined according to the striking time and the transistor involved by the strike. Moreover, the most sensitive parts of the circuit are identified based on the SET impact analysis according to body-bias and transistor channel modulation. The rest of the paper is organized as follows. The comparator design is described in Section 2. Simulation results are presented and discussed
Corresponding author. E-mail address: [email protected] (N. Maciel).
https://doi.org/10.1016/j.microrel.2018.07.114 Received 31 May 2018; Received in revised form 13 July 2018; Accepted 14 July 2018 0026-2714/ © 2018 Published by Elsevier Ltd.
Microelectronics Reliability 88–90 (2018) 965–968
N. Maciel et al.
Fig. 3. Comparator output V
op
when a SET occurs at the rising clock edge.
Fig. 1. StrongArm comparator.
transistor. in Section 3. Finally, Section 4 concludes the work.
Iinj (t ) = 2. Comparator design
• Reset phase: when Clk = 0 V, M1 is off, while M6, M7, M8, and M9 are on. V and V are pre-charged to V by M9 and M8. Comparison phase: when Clk = V , M1 is on, while M6, M7, M8, • on
(e
−t τ1
−t
− e τ2
)
(1)
Only one SET is considered each time. Critical charge Qc is denoted as the minimum charge in a transistor that leads to incorrect output values. Simulations were carried out to identify the sensitivity of the circuit against SET. In order to do this, the SET charge in each transistor was set to vary from 0 C to 20 fC, and the striking time was varied during one period of clock. The circuit outputs are considered correct, in the falling clock edge, if V op − V on > V DD/2 when V ip > V in or if V on − V op > V DD/2 when V in > V ip. Fig. 3 illustrates the output V op for different SET charge values. In this example, the current SET pulse is applied at the rising clock edge. It can be seen that the output is flipped depending on the SET charge applied. The SET impact of the comparator is analyzed for two setups. In the simulations, the input voltages of the circuit were set as V cm + ΔV in/2 and V cm −ΔV in/2, where V cm is the common-mode voltage and ΔV in is the differential-mode voltage.
Fig. 1 shows the schematic diagram of the comparator considered in this work [15]. This is the StrongArm comparator, which is widely used in ADCs [10,11,16]. This circuit produces an output V op (and this opposite V on) which is according to the difference between the input voltages (V ip and V in). Its working principle includes two phases:
op
Qinj τ1 − τ2
DD
DD
and M9 are off. For V ip > V in, V on decreases until V on = 0 V and V op = V DD. Otherwise, when V in > V ip, V op decreases until V op = 0 V and V on = V DD.
3. Simulation results A 28 nm CMOS FDSOI design-kit is utilized to implement and simulate the comparator. The design considers low threshold voltage (LVT) transistors using n-well below nFET and p-well below pFET devices. This flipped-well configuration is used to improve the powerdelay performance [17,18]. SET is generated by a double-exponential current pulse on the transistor drain. The current Iinj(t) is defined by Eq. (1) where Qinj is the charge injection level, τ1 is the collection time constant for a junction, and τ2 is the ion track establishment time constant [19,20]. In this work, τ1 = 20 ps and τ2 = 1 ps. Fig. 2 shows the current flow resulting from the single event strike. It depends upon the polarity of the
3.1. Setup 1 In Setup 1, each transistor is set to width W = 80 nm and length Li, where Li varies according to the simulation. The clock frequency is fclock = 200 MHz, V DD = 1.0 V, V cm = 0.6 V, ΔV in = 100 mV. Back gates of transistors are connected to 0 V. The striking time was varied from 2.5 ns (first falling clock edge) to 7.5 ns (second falling clock edge). Fig. 4 shows the Qc value for the transistors that have Qc lower than 2 fC when V ip > V in and Li = 30 nm. It can be noticed that the critical striking time (4.996 ns) is before the rising clock edge (5 ns). Then, the SET robustness is evaluated varying the Li value. Using poly biasing, i.e., modulation of body gate length, it can achieve leakage power reduction at the expense of lower speed [18]. The length gate value was increased up to 16 nm (i.e., Li varies until 46 nm). It was observed that the most sensitive transistors are the same than in the simulation with Li = 30 nm. Table 1 presents the minimum Qc value for each transistor in all simulations performed. The bold items in the table highlight the lowest minimum Qc value found in each setting. The results show that depending on the transistor location/role reached by the SET, the SET robustness of the circuit can increase or decrease. For example, with Li = 46 nm, if a SET occurs in the M3, the circuit is less robust than if Li = 30 nm. Otherwise, if M8 is reached by the SET, the comparator is more robust with Li = 46 nm. In addition, it can be seen that increasing the Li value allows the comparator to become more
Fig. 2. Modelling the SET in (a) NMOS and (b) PMOS. 966
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Fig. 5. FDSOI device configurations: (a) Flip-well (b) Flip-well with back-bias. Fig. 4. Value of Qc (fC) for Setup 1 and V
ip >
V in.
Table 1 Minimum Qc (fC) values for Setup 1. V V
ip in
> V in > V ip
Li = 30 nm Li = 34 nm Li = 40 nm Li = 46 nm
M3 M2
M5 M4
M6 M7
M8 M9
M10 M11
0.238 0.237 0.228 0.227
0.163 0.168 0.170 0.170
0.375 0.414 0.439 0.453
0.277 0.297 0.327 0.347
0.277 0.297 0.327 0.347
robust, that is, the minimum Qc value increases by 4.3% compared to the minimum Qc when Li = 30 nm. The simulations results point out that the comparator presents different behaviours according to the transistor reached by the SET and the striking time. Moreover, it can be noticed similarity of some results due to the symmetry in the comparator structure. It can be seen that M4 and M5 are the most critical transistors, as they present the lowest Qc value.
Fig. 6. Value of Qc (fC) for Setup 2 in different body-bias. Table 3 Minimum Qc (fC) value for Setup 2.
3.2. Setup 2
V V
Similarly to [11], Setup 2 considers fclock = 2.5 GHz, V DD = 1.2 V, V cm = 0.73 V and ΔV in = 300 mV. The transistors sizes have been adapted to 28 nm FDSOI CMOS technology, as shown in Table 2. Fig. 5 illustrates the back-bias of FDSOI device used in this Setup. In the Flip-well configuration (Case 1), the NMOS and the PMOS body is connected to 0 V. Otherwise, the NMOS body is connected to V DD and PMOS body is connected to 0 V in Flip-well with back-bias configuration (Case 2). The striking time is varied from 200 ps (first falling clock edge) to 600 ps (second falling clock edge). Fig. 6 shows the Qc value for the transistors with Qc lower than 20 fC when V ip > V in. In Fig. 6, the continuous lines represent the simulations of Case 1, while the broken lines denote the simulations of Case 2. Table 3 shows the minimum Qc value for each transistor. The bold items in the table highlight the lowest minimum Qc value found in each setting. In Case 1, if a SET occurs in M8 or M10, the SET charge must be
Width W (nm)
Length L (nm)
M1, M6, M4, M2,
1500 1000 1500 2000
30 30 30 40
M8, M9 M7 M5, M10, M11 M3
in
> V > V
Case 1 Case 2
in ip
M3 M2
M5 M4
M8 M9
M10 M11
6.98 7.24
3.64 4.09
> 20 14.95
> 20 14.95
greater than 20 fC (Qc > 20 fC) for an error to occur at the comparator's output. Otherwise, in Case 2, if a SET occurs in M8 or M10 with a charge more than 14.95 fC at the critical striking time, there will be incorrect output values. It can be noticed that for the NMOS transistors (M2, M3, M4 and M5), the Case 2 configuration improves the comparator SET robustness which was indicated by the increase of the Qc value when a SET occurs in a NMOS. At the critical striking time, the flip-well with back-bias configuration increases Qc by 12.4% if the M5 is reached by the strike. On the other hand, when a SET occurs in a PMOS transistor (M8, M9, M10 and M11), the circuit is more robust with Case 1 configuration. Furthermore, it can be seen that the critical transistors are the same in the two cases. The transistors with the minimum Qc values at the critical striking time are M4 and M5, that is, they are the most critical transistors of the circuit. The results show that the robustness of the circuit against SET depends on the striking time and the transistor involved by the strike. In addition, the SET robustness of the comparator is improved when NMOS body is connected to V DD and PMOS body is connected to 0 V. In
Table 2 Size of the transistors in Setup 2. Transistors
ip
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other words, the Qc at the critical striking moment is bigger than when NMOS and PMOS body is connected to 0 V. In summary, it can be said that analysis of the SET impact allows to check either the circuit complies with the application requirements. If the circuit is not SET robust enough, Qc results enable ranking transistors and therefore an appropriate change.
[3] F. Pareschi, P. Albertini, G. Frattini, M. Mangia, R. Rovatti, G. Setti, Hardwarealgorithms co-design and implementation of an analog-to-information converter for biosignals based on compressed sensing, IEEE Trans. Biomed. Circuits Syst. 10 (1) (Feb 2016) 149–162. [4] E. Maricau, G. Gielen, Analog IC Reliability in Nanometer CMOS, Springer, 2013. [5] R. Jain, A.K. Dubey, V. Varshney, R.K. Nagaria, Design of low-power high-speed double-tail dynamic CMOS comparator using novel latch structure, 2017 4th IEEE Uttar Pradesh Section International Conference on Electrical, Computer and Electronics (UPCON), Oct 2017, pp. 217–222. [6] D. Xu, S. Xu, G. Chen, High-speed low-power and low-power supply voltage dynamic comparator, Electron. Lett. 51 (23) (2015) 1914–1916. [7] B. Razavi, B.A. Wooley, Design techniques for high-speed, high-resolution comparators, IEEE J. Solid State Circuits 27 (12) (Dec 1992) 1916–1926. [8] International Technology Roadmad for Semiconductors: Front End Processes, ITRS 2009 Edition. [9] E. Mikkola, B. Vermeire, H.J. Barnaby, H.G. Parks, K. Borhani, SET tolerant CMOS comparator, IEEE Trans. Nucl. Sci. 51 (6) (Dec 2004) 3609–3614. [10] T. Wang, L. Chen, A. Dinh, B. Bhuva, Single-event transients effects on dynamic comparators in a 90 nm CMOS triple-well and dual-well technology, IEEE Trans. Nucl. Sci. 56 (6) (Dec 2009) 3556–3560. [11] H. Chunmei, S. Chen, P. Huang, Y. Liu, J. Chen, Evaluating the single event sensitivity of dynamic comparator in 5 Gbps SerDes, IEICE Electron. Express 12 (2015). [12] R. Liu, Study of Radiation Effects on 28 nm UTBB FDSOI Technology (Ph.D. dissertation), University of Saskatchewan, 2017. [13] W.C. Bartra, A. Vladimirescu, R. Reis, Process and temperature impact on singleevent transients in 28 nm FDSOI CMOS, 2017 IEEE 8th Latin American Symposium on Circuits Systems (LASCAS), Feb 2017, pp. 1–4, , https://doi.org/10.1109/ LASCAS.2017.7948062. [14] W.C. Bartra, A. Vladimirescu, R. Reis, FDSOI and bulk CMOS SRAM cell resilience to radiation effects, Microelectron. Reliab. 64 (2016) 152–157 Proceedings of the 27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis. [15] B. Razavi, The StrongARM latch [a circuit for all seasons], IEEE Solid-State Circuits Mag. 7 (2) (Spring 2015) 12–17. [16] A.V. Fonseca, R.E. Khattabi, W.A. Afshari, F.A.P. Barúqui, C.F.T. Soares, P.M. Ferreira, A temperature-aware analysis of latched comparators for smart vehicle applications, 2017 30th Symposium on Integrated Circuits and Systems Design (SBCCI), Aug 2017, pp. 1–6. [17] Y. Wang, H. Cai, L. Naviner, X. Zhao, Y. Zhang, M. Slimani, J. Klein, W. Zhao, A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI, Microelectron. Reliab. 64 (2016) 26–30 Proceedings of the 27th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis. [18] H. Cai, Y. Wang, L.A.B. Naviner, W. Zhao, Robust ultra-low power non-volatile logic-in-memory circuits in FD-SOI technology, IEEE Trans. Circuits Syst. Regul. Pap. 64 (4) (April 2017) 847–857. [19] G.C. Messenger, Collection of charge on junction nodes from ion tracks, IEEE Trans. Nucl. Sci. 29 (6) (Dec 1982) 2024–2031. [20] M. Singh, I. Koren, Fault-sensitivity analysis and reliability enhancement of analogto-digital converters, IEEE Trans. Very Large Scale Integr. VLSI Syst. 11 (5) (Oct 2003) 839–852.
4. Conclusion This work addresses the problem of SET impact on comparators. SET effects on a dynamic comparator in a 28 nm FDSOI CMOS technology were evaluated considering the polarity of differential inputs and the working phases for two different setups. The different body biases and poly bias technique have been considered. The minimum amount of charge necessary to produce incorrect circuit outputs was analyzed. When the poly bias technique was used, the minimum Qc value increased by 4.3% in Setup 1. In Setup 2, the flip-well with backbias configuration increased the minimum Qc value by 12.4%. The analysis allowed the identification of critical transistors and the critical striking time. For these setups, the most sensitive transistors are the NMOS in the cross-coupled inverter. The results showed that interesting gains can be achieved with different configurations of the FDSOI devices. Therefore, simulations that take into account other effects like multiple hits and more accurate models using TCAD tools to support the conclusions presented here are future steps that motivate the continuation of this work. Thus, appropriate strategies for SET hardening can be developed and implemented. Acknowledgement This work received financial support from Brazilian Ministry of Defense and Pilot School Reform Funding Program in Southeast University 2242018K40100. References [1] N. Zhang, P. Yang, J. Ren, D. Chen, L. Yu, X. Shen, Synergy of big data and 5G wireless networks: opportunities, approaches, and challenges, IEEE Wirel. Commun. 25 (1) (February 2018) 12–18. [2] D.L. Donoho, Compressed sensing, IEEE Trans. Inf. Theory 52 (4) (April 2006) 1289–1306.
968
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Single-event transient effects on dynamic comparator in 28 nm FDSOI CMOS technology
T
N. Maciela,*, E.C. Marquesa, L.A.B. Navinera, H. Caia,b a b
Télécom ParisTech, Université Paris-Saclay, 46 Rue Barrault, Paris, France National ASIC System Engineering Center, Southeast University, Nanjing 210096, China
A R T I C LE I N FO
A B S T R A C T
Keywords: Single-event transient 28 nm FDSOI Dynamic comparator Reliability analysis
The comparator is a key component of analog to information converters. The speed and the accuracy of the comparator determine the conversion quality. As device-scaling enters in the nanometer dimensions, the circuit becomes more susceptible to temporary faults. In this work, Single-Event Transient effects on a dynamic comparator in 28 nm FDSOI CMOS technology are investigated. The sensitivity of the circuit is simulated combined with the polarity of differential inputs and the working phases of the comparator. Moreover, the body-bias and the transistor channel modulation impact were analyzed. The minimum charge Qc to produce incorrect outputs is determined according to the striking time and the transistor involved by the strike. Results show that circuit vulnerability is a function of the individual transistor, the striking time, body-bias and the transistor channel modulation. Moreover, the minimum Qc value increases by 4.3% and 12.4% using the poly technique and the flip-well with back-bias configuration, respectively.
1. Introduction The amount of information to transmit or process is increasingly growing [1]. Compressed sensing (CS) theory, which merges data acquisition and data compression processes, appears to be an efficient solution to deal with this phenomenon [2]. CS approach allows to replace traditional Nyquist based analog-to-digital converters (ADC) by analog to information converters (AIC) and significantly reduce the number of necessary measurements [3]. Nevertheless, the low number of acquired measurements makes the reliability of AIC become a major issue. The comparator is a pivotal component of an AIC. Its speed, accuracy, and power consumption determine the conversion efficiency. Therefore, high quality-demand, low power or critical applications as cognitive radio, aerospace, and radar sensors require highly effective comparators [4]. Comparators can be classified into static or dynamic depending upon whether its operation is controlled by clock signal [5]. Dynamic comparators [6] have been proposed to overcome high-power consumption and low-speed issues generally presented by static comparators [7]. Moreover, with down-scaled device dimensions to nanometers, circuits become increasingly susceptible to transient disturbances named Single Event Transient (SET) [8]. SET results of deposited charge when ionizing energetic particles hit a sensitive region of the *
circuit [9]. The SET effects of a dynamic comparator were evaluated in [10] and [11] for 90 nm and 65 nm CMOS bulk technologies, respectively. The results show that circuit vulnerability strongly depends on technology, topology, and individual transistor currents. As many others, the works above do not deeply explore the relationship between the effect of a given SET and the striking time or the transistor concerned by that SET. However, it could be interesting to assess how striking time impacts the minimal SET's charge needed to change the comparator's output. Likewise, information either SET in different transistors/locations leads to different impacts on the comparator's output would enable implementation of effective reliability improvement strategies. On the other hand, fully depleted silicon-on-insulator (FDSOI) technologies are attractive due to their high-speed/low-power features [12] and its reliability has been extensively studied [12–14]. Nonetheless, to the best to our knowledge, SET effects on FDSOI based comparators have not yet been reported. In this work, SET effects on a 28 nm FDSOI dynamic comparator are investigated. The critical charge is determined according to the striking time and the transistor involved by the strike. Moreover, the most sensitive parts of the circuit are identified based on the SET impact analysis according to body-bias and transistor channel modulation. The rest of the paper is organized as follows. The comparator design is described in Section 2. Simulation results are presented and discussed
Corresponding author. E-mail address: [email protected] (N. Maciel).
https://doi.org/10.1016/j.microrel.2018.07.114 Received 31 May 2018; Received in revised form 13 July 2018; Accepted 14 July 2018 0026-2714/ © 2018 Published by Elsevier Ltd.
Microelectronics Reliability 88–90 (2018) 965–968
N. Maciel et al.
Fig. 3. Comparator output V
op
when a SET occurs at the rising clock edge.
Fig. 1. StrongArm comparator.
transistor. in Section 3. Finally, Section 4 concludes the work.
Iinj (t ) = 2. Comparator design
• Reset phase: when Clk = 0 V, M1 is off, while M6, M7, M8, and M9 are on. V and V are pre-charged to V by M9 and M8. Comparison phase: when Clk = V , M1 is on, while M6, M7, M8, • on
(e
−t τ1
−t
− e τ2
)
(1)
Only one SET is considered each time. Critical charge Qc is denoted as the minimum charge in a transistor that leads to incorrect output values. Simulations were carried out to identify the sensitivity of the circuit against SET. In order to do this, the SET charge in each transistor was set to vary from 0 C to 20 fC, and the striking time was varied during one period of clock. The circuit outputs are considered correct, in the falling clock edge, if V op − V on > V DD/2 when V ip > V in or if V on − V op > V DD/2 when V in > V ip. Fig. 3 illustrates the output V op for different SET charge values. In this example, the current SET pulse is applied at the rising clock edge. It can be seen that the output is flipped depending on the SET charge applied. The SET impact of the comparator is analyzed for two setups. In the simulations, the input voltages of the circuit were set as V cm + ΔV in/2 and V cm −ΔV in/2, where V cm is the common-mode voltage and ΔV in is the differential-mode voltage.
Fig. 1 shows the schematic diagram of the comparator considered in this work [15]. This is the StrongArm comparator, which is widely used in ADCs [10,11,16]. This circuit produces an output V op (and this opposite V on) which is according to the difference between the input voltages (V ip and V in). Its working principle includes two phases:
op
Qinj τ1 − τ2
DD
DD
and M9 are off. For V ip > V in, V on decreases until V on = 0 V and V op = V DD. Otherwise, when V in > V ip, V op decreases until V op = 0 V and V on = V DD.
3. Simulation results A 28 nm CMOS FDSOI design-kit is utilized to implement and simulate the comparator. The design considers low threshold voltage (LVT) transistors using n-well below nFET and p-well below pFET devices. This flipped-well configuration is used to improve the powerdelay performance [17,18]. SET is generated by a double-exponential current pulse on the transistor drain. The current Iinj(t) is defined by Eq. (1) where Qinj is the charge injection level, τ1 is the collection time constant for a junction, and τ2 is the ion track establishment time constant [19,20]. In this work, τ1 = 20 ps and τ2 = 1 ps. Fig. 2 shows the current flow resulting from the single event strike. It depends upon the polarity of the
3.1. Setup 1 In Setup 1, each transistor is set to width W = 80 nm and length Li, where Li varies according to the simulation. The clock frequency is fclock = 200 MHz, V DD = 1.0 V, V cm = 0.6 V, ΔV in = 100 mV. Back gates of transistors are connected to 0 V. The striking time was varied from 2.5 ns (first falling clock edge) to 7.5 ns (second falling clock edge). Fig. 4 shows the Qc value for the transistors that have Qc lower than 2 fC when V ip > V in and Li = 30 nm. It can be noticed that the critical striking time (4.996 ns) is before the rising clock edge (5 ns). Then, the SET robustness is evaluated varying the Li value. Using poly biasing, i.e., modulation of body gate length, it can achieve leakage power reduction at the expense of lower speed [18]. The length gate value was increased up to 16 nm (i.e., Li varies until 46 nm). It was observed that the most sensitive transistors are the same than in the simulation with Li = 30 nm. Table 1 presents the minimum Qc value for each transistor in all simulations performed. The bold items in the table highlight the lowest minimum Qc value found in each setting. The results show that depending on the transistor location/role reached by the SET, the SET robustness of the circuit can increase or decrease. For example, with Li = 46 nm, if a SET occurs in the M3, the circuit is less robust than if Li = 30 nm. Otherwise, if M8 is reached by the SET, the comparator is more robust with Li = 46 nm. In addition, it can be seen that increasing the Li value allows the comparator to become more
Fig. 2. Modelling the SET in (a) NMOS and (b) PMOS. 966
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Fig. 5. FDSOI device configurations: (a) Flip-well (b) Flip-well with back-bias. Fig. 4. Value of Qc (fC) for Setup 1 and V
ip >
V in.
Table 1 Minimum Qc (fC) values for Setup 1. V V
ip in
> V in > V ip
Li = 30 nm Li = 34 nm Li = 40 nm Li = 46 nm
M3 M2
M5 M4
M6 M7
M8 M9
M10 M11
0.238 0.237 0.228 0.227
0.163 0.168 0.170 0.170
0.375 0.414 0.439 0.453
0.277 0.297 0.327 0.347
0.277 0.297 0.327 0.347
robust, that is, the minimum Qc value increases by 4.3% compared to the minimum Qc when Li = 30 nm. The simulations results point out that the comparator presents different behaviours according to the transistor reached by the SET and the striking time. Moreover, it can be noticed similarity of some results due to the symmetry in the comparator structure. It can be seen that M4 and M5 are the most critical transistors, as they present the lowest Qc value.
Fig. 6. Value of Qc (fC) for Setup 2 in different body-bias. Table 3 Minimum Qc (fC) value for Setup 2.
3.2. Setup 2
V V
Similarly to [11], Setup 2 considers fclock = 2.5 GHz, V DD = 1.2 V, V cm = 0.73 V and ΔV in = 300 mV. The transistors sizes have been adapted to 28 nm FDSOI CMOS technology, as shown in Table 2. Fig. 5 illustrates the back-bias of FDSOI device used in this Setup. In the Flip-well configuration (Case 1), the NMOS and the PMOS body is connected to 0 V. Otherwise, the NMOS body is connected to V DD and PMOS body is connected to 0 V in Flip-well with back-bias configuration (Case 2). The striking time is varied from 200 ps (first falling clock edge) to 600 ps (second falling clock edge). Fig. 6 shows the Qc value for the transistors with Qc lower than 20 fC when V ip > V in. In Fig. 6, the continuous lines represent the simulations of Case 1, while the broken lines denote the simulations of Case 2. Table 3 shows the minimum Qc value for each transistor. The bold items in the table highlight the lowest minimum Qc value found in each setting. In Case 1, if a SET occurs in M8 or M10, the SET charge must be
Width W (nm)
Length L (nm)
M1, M6, M4, M2,
1500 1000 1500 2000
30 30 30 40
M8, M9 M7 M5, M10, M11 M3
in
> V > V
Case 1 Case 2
in ip
M3 M2
M5 M4
M8 M9
M10 M11
6.98 7.24
3.64 4.09
> 20 14.95
> 20 14.95
greater than 20 fC (Qc > 20 fC) for an error to occur at the comparator's output. Otherwise, in Case 2, if a SET occurs in M8 or M10 with a charge more than 14.95 fC at the critical striking time, there will be incorrect output values. It can be noticed that for the NMOS transistors (M2, M3, M4 and M5), the Case 2 configuration improves the comparator SET robustness which was indicated by the increase of the Qc value when a SET occurs in a NMOS. At the critical striking time, the flip-well with back-bias configuration increases Qc by 12.4% if the M5 is reached by the strike. On the other hand, when a SET occurs in a PMOS transistor (M8, M9, M10 and M11), the circuit is more robust with Case 1 configuration. Furthermore, it can be seen that the critical transistors are the same in the two cases. The transistors with the minimum Qc values at the critical striking time are M4 and M5, that is, they are the most critical transistors of the circuit. The results show that the robustness of the circuit against SET depends on the striking time and the transistor involved by the strike. In addition, the SET robustness of the comparator is improved when NMOS body is connected to V DD and PMOS body is connected to 0 V. In
Table 2 Size of the transistors in Setup 2. Transistors
ip
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other words, the Qc at the critical striking moment is bigger than when NMOS and PMOS body is connected to 0 V. In summary, it can be said that analysis of the SET impact allows to check either the circuit complies with the application requirements. If the circuit is not SET robust enough, Qc results enable ranking transistors and therefore an appropriate change.
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4. Conclusion This work addresses the problem of SET impact on comparators. SET effects on a dynamic comparator in a 28 nm FDSOI CMOS technology were evaluated considering the polarity of differential inputs and the working phases for two different setups. The different body biases and poly bias technique have been considered. The minimum amount of charge necessary to produce incorrect circuit outputs was analyzed. When the poly bias technique was used, the minimum Qc value increased by 4.3% in Setup 1. In Setup 2, the flip-well with backbias configuration increased the minimum Qc value by 12.4%. The analysis allowed the identification of critical transistors and the critical striking time. For these setups, the most sensitive transistors are the NMOS in the cross-coupled inverter. The results showed that interesting gains can be achieved with different configurations of the FDSOI devices. Therefore, simulations that take into account other effects like multiple hits and more accurate models using TCAD tools to support the conclusions presented here are future steps that motivate the continuation of this work. Thus, appropriate strategies for SET hardening can be developed and implemented. Acknowledgement This work received financial support from Brazilian Ministry of Defense and Pilot School Reform Funding Program in Southeast University 2242018K40100. References [1] N. Zhang, P. Yang, J. Ren, D. Chen, L. Yu, X. Shen, Synergy of big data and 5G wireless networks: opportunities, approaches, and challenges, IEEE Wirel. Commun. 25 (1) (February 2018) 12–18. [2] D.L. Donoho, Compressed sensing, IEEE Trans. Inf. Theory 52 (4) (April 2006) 1289–1306.
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