- Email: [email protected]
Noise immunity of CMOS integrated circuits
Noise immunity of CMOS integrated circuits by T. Chesney and R. Funkt
Sources of noise in Iog!c circuits are discussed and definitions stated. The good noise performance of CMOS devices is then explained.
1. Introduction The excellent noise immunity of CMOS digital integrated circuits is a paramount reason for their preferred and successful use in high noise automotive, process control, production monitoring, and similar noisy applications. The development of the RCA B-series CMOS devices improves the well known noise immunity advantages of this technology in two important ways: (i) Improved noise energy immunity as a result of balanced low impedance output circuitry. (ii) Standardised (EIA-JEDEC standards) dc noise immunity and noise margin ratings for buffered and unbuffered CMOS-logic types. 2. Logic system noise concepts Successful application of any digital logic IC family requires consideration of the following: (i) Externally or internally generated noise- both radiated and conducted. (ii) The inherent noise immunity capability of the logic family selected. (iii) System noise rejection measures. Without co-ordination of these three points, a system design may perform unfavourably. Consider first the various system or environmental noise generating sources. External system noise may include the noise imposed upon a logic system by electric motors, welders, rf transmitters, X-ray machines, high current solenoids or relays, pulsed lasers, and circuit breakers. All of these emit electromagnetic interference, and many produce power line or ground path noise disturbance. External noise is Characterised by randomly occurring high energy transients which are not easily anticipated. Usually, this noise is coupled electromagnetically or capacitively to signal, supply, tRCA, Sunbury-on-Thames, UK.
and ground lines. Internal logic system noise is usually g e n e r a t e d on logic signal lines by capacitively coupled
crosstalk or by logic switching current surges on supply lines or ground lines. In ultra-high speed logic families such as ECL, reflection noise resulting from an impedance mismatch is also an internal noiseproblem, but because of relatively long output transition times of CMOS devices (more than I0ns), reflection noise can be excluded from further consideration. Since both external and internal noise must be considered, logic systems must be designed to survive in a medium-to-se~,ere noise environment, a fact that leads to the second consideration: selection of an IC logic family having noise rejection characteristics appropriate to the application. No matter how good the noise rejection capability of an IC logic family system design measures to reduce noise entry into logic signal lines, power supply lines, and the ground are usually necessary. The methods most commonly used to minimise noise effects in CMOS logic s y s t e m s are as follows: (i) Power line decoupling. Good practice suggests the use of a small value series resistor and zener diode and a capacitor to ground on each logic
card or for each 50 to 100 integrated circuit packages. High voltage supply transients can usually be rejected by this simple m e a s u r e . Separate lines should be used for logic circuits and power switching circuits. (ii) Ground line noise. In a system involving many high current switching components, such as motors, relays, and SCRs, logic grounds should be separated from high energy component grounds. The logic grounds should be returned to a common point. (iii) AC noise on system signal inputs. 6 0 H z is a commonly used frequency reference. Raw ac power lines should be isolated using a transformer or optical coupler. Zener diode
MICROELECTRONICS JOURNAL Vol. 10 No. 1 © 1979 Mackintosh Publications Ltd., Luton.
1R
Noise Immunity
of CMOSintegrated circuits c o n t i n u e d f r o m p a g e 15
limiters are also effective. 60Hz signals can be shaped by using CMOS Schmitt trigger circuits. 3. Noise specifications CMOS noise immunity is characterised by dc specifications, ac noise immunity performance, and noise energy immunity performance. Each of these characteristics is defined below.
3.1 DC specifications Table I shows the industry standardised (JEDEC) noise immunity and noise margin ratings, Vn. and Vra. Table I
JEDEC Standards for dc Noise Immunity -
Characteris//c.$
Test Conditions
VDD (v)
V0
(v)
Input
Voltage (v)
upsetting the logic or causing any output to exceed the Vo ratings of Table I. Of the two CMOS dc noise definitions, immunity and margin, RCA prefers the noise immunity specification as the more practical definition because CMOS outputs are normally 50mV off the rails. However, designers familiar with TTL may prefer to use the noise margin voltage for system analysis. AC noise immunity CMOS ac noise immunity takes into account both the device switching threshold (de noise immunity) and the noise pulse width. The latter is affected primarily by the CMOS integrated circuit band-width, especially output transition times. Figure 1 shows the usual CMOS noise voltage amplitude, Vt, as a function of noise pulse width, tv. 3.2
' Input lowvoltage VIL max.
B types.
0.5•4.5 1/9 1.5/13.5 0.5/4.5 1/9 1.5/!3.5
UB types
5 10 15 5 10 15
1.5 3 4 1 2 2.5
" Input highvoltage Vm nan. '
0.5/4.5 1/9 1.5/1315 0.5/4.5 1/9 1.5/13.5
5 10 15 5 10 15
3.5 7 11 4 8 12.5
Note that separate specifications have been established for B (buffered) types and UB (unbuffered) types. 1 Two important noise characteristics can be defined by using the V~ and Vm ratings, • (i) N o i s e immuniW..The V I L and Vm limits are the deyice input signal noise immunity ratings which, as defined in Table II, are 30%, 30%, and 27%, respectively, of the 5, 10, and 15V supply voltages. Percentages are lower for unbuffered gates, as shown in Table II. The Vn. and Vm ratings define the maximum permissible additive noise voltages at an input terminal when input signals are 50mV off the supply rails. B-series Noise Immunity and Noise Margin (TA=25°C) Noise lmmuhity (%) Noise Margin Voltage (V)
VDD
B-series
UB-series
B-series •
UB-series
10
30 " 30, 27
20 20 17
1 2 2.5
0.5 1 1
(ii) N o i s e margin. The difference between VrL and Vo or Vm and Vo is the device noise margin voltage for the non-inverting case. Table II designates the B and UB noise margin voltages. Noise margin voltage is defined as that noise voltage which can be impressed upon Vrs at any (or all) logic input/output terminals without 16
~
t"-i it_ 5; <
V t h mif
LIBtypes
15
ILl
Ul
B types
Table II
>
I I I I I tpmin
-J
o> i O9
o Z
POINT usED FOR CALCULATION _..~ENmin' OF FIG.2
"-
NOISE PULSE WIDTH (to)ns Fig. 1 Generic ac noise immunity curve.
Because noise pulses are narrow compared with device output transition time, noise voltage rejection is high. As the pulse widths approach the IC bandwidth, the curve flattens out at the device switching threshold voltage. AC noise voltage immunity curves, such as those in Fig. 1, are applicable to: (i) Positive noise pulses on signal lines in the 0 state. (ii) Negative noise pulses on signal lines in the 1 state. (iii) Positive noise pulses on the ground terminal. (iv) Negative noise pulses on the positive supply terminal. Curves of this type indicate the frequency (as defined by noise pulse characteristics)at which the user has satisfactory de noise performance. The curves are especially useful in calculating typical noise energy performance, a parameter which takes into account the circuit impedance. 3.3 Noise e n e r g y immunity Noise energy immunity takes into account the pulse width and the circuit impedance at the point where the noise is introduced. Noise energy immunity is calculated as follows:
E~
=
~ : Ro
~,
Figs. 3 and 4 and Table I indicates that the values of Vn. and Vm for these devices are well within the standard J E D E C specifications. The Vm and VxHvalues for any typical CMOS device indicate a typical de noise immunity close to 50% of the supply voltage, a paramount advantage of CMOS logic devices over TI'L, ECL, PMOS, and logic devices.
el
A
z
ILl
>(.9
3D4OO1UB IA=23"C
f,/) .,..,
rr uJ
zLM ENmi n
I.IJ
O
15
I I
I
to O z
tpmin NOISE PULSE WIDTH __(tp)ns
D O >
r
(.9 10
Fig. 2 G e n e r i c no~se energy immunity curve. where F_mis noise energy immunity in nanojoules, Vth is the device switching voltage threshold for a given noise pulse width, tv is the noise, voltage pulse• width in nanoseconds, and R0 Is the impedance to ground in ohms at the point of noise entry. Ro is usually the output resistance of the CMOS device. By using values, of V and Iv obtained from the curve of Fig. 1, the noise energy immunity curve of Fig. 2 is generated for a given value of Ro. A comparison of Figs. 1 and 2 shows that the minimum values of noise energy immunity occur ~t an input noise pulse width for which the noise voltage amplitude of Fig. 1 begins to approach the dc noise immunity or threshold voltage of a device. The minimum noise energy immunity is the basis for the calculationsand comparisons involving most IC families. 4. N o i ~ i m m u n i t y t e s t 4.1 De noise immuniW test data CMOS dc noise immunity performance is obtained by plotting the voltage transfer characteristic of a CMOS gate, inverter, or buffer. Figures 3 and 4 show the voltage transfer characteristics of the CD4001B, a buffered qua d 2-input NOR gate, and the CD4001UB, an unbuffered version of the same gate. Comparison of
CD4001B TA=23"C
o~
15 FD
~.-
-d
0 > 12.
F-0
L
0
5
Fig. 4 CD4001UBvoltage transfer characteristic. 4.2 AC noise immuniWtest d a t a Figure 5 shows the test circuit used in the evaluation of the ac noise immunity of B-series CMOS devices. The criterion used is the triggering of a typical CD4013B flip-flop at the clock input. The circuit of Fig. 5 accounts for typical CMOS loading factors and generally reflects the ac noise performance of typical B-series devices. The device types used in the evaluation include the following: (1) CD4001UB unbuffered quad 2-input NOR gate (2) CD4001B buffered quad 2-input 2-input NOR gate (3) CD4011UB unbuffered quad 2-input NAND gate (4) CD4069UB hex inverter (5) CD4049UB hex inverting buffer. The above list includes the most commonly used CMOS gates, inverters, and buffered devices. The ac noise immunity characteristics of the buffered NOR gate (CD4001B) reflect the noise immunity performance of buffered CMOS products of all descriptions. D
'VDD
I I
II
v;s
I' I I I
I-
O.~F
0
5
10
_J-I_
15
-U-
INPUT VOLTAGE (VIN)Volts Fig. 5 Fig. 3
15
I
g
0
10
INPUT VOLTAGE (ViN}Volts
~
' " 10 < i--.J 0 >
\
CD4001B voltage transfer characteristic.
I
I '
~_1_ /
Vss
MONITOR FOR STATE CHANGE
Test circuit used in the evaluation of B-series C O S / M O S devices. 17
N o i s e i m m u n i t y of C M O S i n t e g r a t e d circuits continued from page 17
4.3 Signal line or external noise immuniW The following analysis was used to determine the immunity o f a CMOS gate to noise on the input line at both the 0 (low level) and 1 (high level) logic states. 0-state analysis. The signal line noise immunity of CMOS gates and inverters was evaluated by means of the test circuit shown in Fig. 6. The CMOS units tested were the same as in the previous test. Figure 7 shows the results obtained. The test circuit is designed to measure the voltage required at the input of the unit under test to trigger a CD4013 flip-flop. VDD
ALL UNUSED
,
c
[
oo,
o
,CD IUB: 0.1~E =
1
,, I
_L
CD4069UB CD4049UB
J-L_ Fig. 6 Test circuit used to evaluate signal line noise immunity of CMOS gates and invertors.
During test, a positive going noise pulse is introduced into the signal line of the unit under test. At some voltage level, depending on the width of the pulse and the gate thresholds, this pulse causes the flip-flop to be clocked via the CD4001B gate. This voltage level defines the permissible input range for a logical 0. A de analysis of the transfer characteristics of the components included in the test set-up can also be used to determine the noise level required to clock the flipflop. Figure 8a shows that a signal of 4.15V is required at the input to the CD4001B gate to produce an output of 4.5V at a supply voltage, VDD, of 10V. Figure 8b shows that an input of 5.25V is required to trigger the CD4013 flip-flop at a supply voltage, VDD, of 10V. All measured values shown in Fig. 8 were obtained from measurements on gates that have typical threshold switching characteristics. Careful analysis of the ac noise curves of Fig. 7c (for the CD4049UB) for 0-state signal line noise shows a voltage pedestal effect occurring at noise pulse widths associated with the noise threshold region of the units under test. A comparison of the voltage transfer curves of Fig. 8c with the dynamic input capacitance curves for the CD4049UB (Fig. 9) reveals that this pedestal effect occurs in the same region as the peak Miller input capacitance, where the inverter is in its maximum linear gain region. Most 0- and 1-state noise voltage characteristics curves in this article exhibit this pedestal effect to some degree. 1-state analysis. Figure 10 shows the test
16 I 14 >- 12 ~10 •. 3 8 ~x~x ~. ~g -- 6 i
%_1 ~
~-
52 0
0 z
200 400 PULSE W I D T H - ns CD4001B, CD4OO1UB 100
(a)
-l O- V
I 300
z
> lCt , ~12
•--CD4011UB
500
crcC
21 100
0
(b)
200 300 400 PULSE W I D T H - n s
CD4011UB
TA=25"CI
1
Jr~= IB-V uJ
. . . .
03
I--
- - -
0 Z
0
100
200 PULSE
(c)CD4049UB,
300 400 W I D T H -ns
500
CD4069UB
Fig. 7 Results oflYstate signal line noise immunity tests. 18
'
I
io
'nn=15Vl
-<---
TA=25" q
> 14, 12 10 8
.--CD4~JOIUB cn,~ 3131R
500
20
>o I-
20
CD4OOIB TA=25"C
OD4OI3B TA=2~ C
(/}
VDD=15V 15 F-
O >
>O 10
< t-J o > I13.. IE:) O
1OV "(.9 ' <
VIN
I(
~IN =
-.15~
0> I-
5V
5.25V
0-
I-
I
0
o 10
5
15
O
INPUT VOLTAGE ( V l N ) V o l t s
5
O
15
INPUT VOLTAGE ( V i N ) V o l t s
(a) CD4OO1B
(b) CD4013B 20
CD4049UI TA= 25"C
03
t-
15
O > " ' 101 (.9 < !-V .-
,J
O > f-
PEAIC MILLER NPUT / C A P A C I T A N C [ REGION / ~ _ WHERE PEDE= T A L
~
4~ ' =~ ' ,'uv~/ "
"-EFFECTOC(:URS
5
IO O
10
5
15
INPUT V O L T A G E ( V l N ) V o l t s
(c) CD4049UB Fig. 8 Transfer characteristics of components used in the circuit of Fig. 6. 14_ Q.
.
140 z
CD4049t.W
A L L UNUSED INPUTS TO GND.
120 ,,I.I
T
I
< a.. <
80
Iv ~ v 10v
60
I." z
40 20
,< z>.r',,
O
ev.,,,r406o.1 T
k._ 5
10
5
20
]J
INPUT V O L T A G E {ViN)Volts
Fig. 9 Dynamic input capacitance curves for the CD4049UB; TA--250C,
Fig. 10 Test circuit used to measure noise immunity of CMOS logic gates and inverters when input is high and a negative going pulse is superimposed on the signal line.
Noise immunity of CMOS integrated circuits continued from page 19
1E
•~ C D 4 O O 1 U B C D4001B TA= 25"C
>14 I
,
10\ b-W
Ill
O
i
1OO
CD4OIIUB TA=25"(~
,'DO='15 5 z
>,
/DO=15V ~E IOV m
5V
....._.._
o z
200 300 400 PULSE W I D T H - n s
(a) CD4OO1B
500
O
1OO
5OO
(b) CD4011UB
CD4OO1UB
D
--
! 1
200 300 400 PULSE W I D T H - n s
d
UB
TA= 25"C
.
.
.
.
.
.
! - L~l.,n
,~-
[
Lo_
O O
100
200 PULSE
300 400 WIDTH -ns
(c) CD4049UB, CD4069UB
500
T A = 25°C
Rg. 11 Results of 1-state signal line noise immunity test.
arrangement used and Fig. 11 the results obtained from noise immunity measurements on the CMOS logic gates and inverters identified above when the input is high and a negative going pulse is superimposed on the signal line.
voo I REQU ,,
tll
vd6.
,. -
,
R G.
)VDD1
o
I-..---CD4,O~IB I
[ t:.L__~.
Ill
oFo r _ ~.~ CD4OllUB '1
,,b
-=-
CD404~,CD4069UB t ~ ALL UNUSED INPUTS TO GND. EQUIVALENT RESISTANCE REQU (ohms) 1OO 50 33 25
MINIMUM PULSE WIDTH ~ (nanoseconds)
53.4 55.5 47.5 51.1
4.4 Power supply noise immunity The test configuration shown in Fig. 12 measures the ability of test units to withstand a negative going noise pulse superimposed on the supply line without a change in state. Figure 13 shows results of tests. A pulse of sufficient amplitude causes the output of the gate to decrease so that, at some point, the CD4013B flip-flop is triggered from the rising voltage at the output of the driving inverter stage. It should be noted that two power supplies are used in the arrangement of Fig. 12. An equivalent resistor or inductor for simulating contact resistance and lead length is used in the VDo line of the unit under test. Without this resistance the test unit will not react to the noise pulse. 4.5 Ground noise immunity Noise on the power line may be effectively reduced or eliminated by the use of decoupling capacitors; however, ground line noise cannot be reduced so easily and, therefore, is more objectionable. Figure 14 shows the test circuit used to measure the ground line noise immunity of CMOS gates and inverters. Figure 15 shows curves of the results obtained. Again, the units under test would not react to the noise unless a 25f~ resistor or small inductor simulating lead length or contact resistance were placed to ground.
VARIATION THE RESULT OF WAVE SHAPING
Fig. 12 Test circuit used to measure the ability of test units to withstand a negative going noise pulse on the supply line without a change in state. 20
4.6 Crosstalk noise immunity A test circuit used to evaluate crosstalk is s h o w n in Fig. 16. A noise pulse from a pulse generator is coupled to
16't
,\
>14
>- 12 FEE
16
[A=Z~C
.--~:I.~
~
"
,
TA~'25"Ci • ~CD4OI1UB
12
yDb=~SV I - . -
.
.
.
.
'
8
,
10~
-
0
100
500
300 400 PULSE W I D T H - ns 2O0
0
('a) CD4OO1B, CD4OO1UB !
bY
I
o z
I::;U
.~2 z
IOO
20O 300 400 P.ULS E W I D T H - n s
500
(b) CD4011UB
TA--25-CI
f
z ~ 8 -
6
I
to 4
.....
J___
~2 z
100
0
2O0 300 400 PULSE WIDTH -ns
(c)CD4049UB,
''1
:1
5O0
CD4069UB
Fig. 13 Power line noise immunity.
the signal line of the gate or inverter through a capacitor. The noise voltage necessary to trigger the flip-flop is then measured for different values of capacitance under high and low input conditions. Figure 17 shows the effect of capacitance on the inputs of the units under test. The circuit shown in Fig. 18 more closely approximates crosstalk caused by adjacent signal lines. The response of the test circuit to a noise pulse may be
CD4OOIB
(1)
CD4OO1B CD4OOIUB
I
~D~ RTER I~'
Q~---o
explained by analysis of the response of a high pass RC circuit to a ramp input of Vi=~t, where ctis the coefficient of coupling and t is the rise time, 10 to 90%. The output voltage V0 may be expressed by the following equation: V0=aRC (1-e-vRc) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1)
The equivalent circuit for the part of the test configuration used in this analysis is shown in Fig. 19. On the basis of this equivalent circuit, equation (1) may be rewritten as follows: V~(max) = :c (ZoI[z~ C[1--et~(zdlzt")Cl . . . . . . . . . . . . .
(2)
If V, is assumed to be ~.t during the period in which the output voltage switches from 10% to 90% of its total value, this change in output voltage can be expressed as follows:
.
_L _vo
jv0o
-r-- v~7~ . . . . ....
.~
~ . v ~ 9 U
.~OR
|
B
•
v,(z41z~)c [1--e-tr2(Z~lzlI 1 . . . . . . . (3)
AL, UNUSEO iNPUTS TO VSS
CO4049UB
~,25a~59p ~ 0.1/.F
~" r,~N _--L. ___-4-
AVo(max) "~
I ~ PULSE ~ __J L-- GENERATOR
Fig. 14 Circuit used to measure ground line noise immunity.
The results of this analysis may be applied to the various crosstalk waveforms obtained. Crosstalk measurements which simulate actual operation are made by means of the test Circuits shown in Figs. 20 and 21. The circuit of Fig. 20 simulates a round cable system and Fig. 21 a ribbon cable system. 91
Noise immunity of C M O S i n t e g r a t e d circuits continued from page 21
16
1E >I 14 >- 17 t-
,:~Cu4u(J]U~ ~- - C.D_4OO1B
,
~D~v
~4 5z 2 0
i100
-r
I
-~ 6
Vnrr=15~
-i or;,
~. 4
i
0v
7° 2I
500
0
(a/ CD4OO1B, CD4OO1UB
100
200 300 400 PULSE W I D T H - n s
500
(b) CD4011UB CD4OllUB
16
VDD=IO~. tp =25 -] 3Ons
> 14 ,,, 12 (.9
o ai > 13'
v,1
0Z 0
'--.CD4011UB '
I
-~ 200 300 4OO PULSE W I D T H - n s
[[A=25"C I
t 14 ~ 12
200
400
(c)CD4049UB,
600
800
1000
CD4069U B
Fig. 15 Ground line noise immunitymeasurements.
~
GATE UNDER
D
TEST
CD4OOIB CD4OO1UB
_L
CD4OllUB
4069UB
--C
49UB
ALL UNUSED INPUTS TO GROUND
Fig. 16 Circuit for measuringnoisevoltageas a functionof couplingcapacitance. 22
Fig. 18 Circuitcloselyapproximatingconditionsforcrosstalk on adjacent signallines.
"1
> 14 ' 12
kkl
~
2C
CD40(~UB CD4OC~B VDD:SV tpff 5 0 - 6 0 n s
't ~
o
I ~
i le i 14 12 IC
-~- ---vtt_
qI
tp=i5-3On~
\~ '~ ...... L~--- - L _ _ _ ! _
8
0
1OO 200 300 400 500 600 COUPLING CAPACITANCE-pF
28 26 >24 t22
,w
viii >
12 ~8
CD4011UB VDD=15V tp : 30-35n., =
'.4
UJ
>o
om
,,,14
~_
c/}
zlO
VIL O
200 4( COUPLING
0
~, 16 t 14 >~ 1 2 ~_~.
)O . IOOO CAPACITANCE- pF
'~CD~O49UB' CD4069UB
16 >14 212
CD4OllUB VDD=5V tp=50-6Ons
06
VIH
N4
2
VIL
0
z
200 3t IOO PULSE WIDTH - ns
~2E UJ 2,4
400
100 2 0 0 300 400 500 600 COUPLING C A P A C I T A N C E - p F
500
2C
CD21049UB CD4069UB VDD = 5V tp=50-6)ns
1-2C -J 0 1E
,,,16 14
1
T-
4 0 0 5OI 1OO 2 0 0 3 0 0 COUPLING CAPACITANCE- p F 28 ~24,-
~
~2C
'
--CD4049UB .CD4069UB
! ~,
voD= lOV
tp=~5-3Ons
\"~-__~ ~V,H \,'-----'~- ' _ ~--i-' . . . . . ,'------~-i";-V,L--!--
'"on 8 I.
O
200 400 600 800 1OOO COUPLING CAPACITANCE-pF
t
__-LS_V
0
VIH
LU
v,L 8 6
. . . .
200 400 600 800 1000 COUPLING C A P A C I T A N C E - p F
0
CD4OOIUB , .CD4OOIB VDD=I5V tp= 30 -35n:
1T;3,, - 7 • IL~
•
6
0 z
'--CD4OOIUB • CD4OO1B VDD =lOV _
O
0
10OO 200 400 600 800 COUPLING C A P A C I T A N C E - p F
-~- CD4049 U B --CD4069UB VDD = 15V tpi30-35n
"~
Ill
~4 0
z
O
200 400 600 800 lOt O COUPLING CAPACITANCE-3F
Fig. 17 Effect of coupling capacitan~:e on the inputs of the unit under test (TA=25°C).
Noise immunity of CMOS integrated circuits continued from page 23
=OUPLING > Zin ~OEF >GATE FICIENT >UNDER TEST
Zo GATE > UNDER > TEST
VIN Fig. 19 Equivalent circuit used in crosstalk analysis of test configuration shown in Fig. 18.
CD4013B B
~_
CD4OllB
CD4OO1B
I
~-J~gUB CD4049UB
L
!LO
0T
~-~ I -
VDD
-•
o
i
I
o
EQUIV. OF 6 FEET OF ROUND CABLE ALL WIRES ONE WIRE 94.7 pF/60 in. 56.1pF/60 in. 18.9pF/ft 11.2p/ft. Fig. 20 Circuit simulating a round cable system.
In Fig. 20, a sense line is placed tightly within five surrounding wires (No. 22 gauge) to form a 6 feet long cable with a capacitance of 18pFper foot (determined by measurement). In Fig. 21, a sense line is placed between two adjacent driving lines (No. 22 gauge) ofa 6 feet long ribbon cable with a capacitance of 16pF per foot (determined by measurement). The results of crosstalk are shown in the photographs of Figs. 22 and 23 for round cable and ribbon cable, respectively. The crosstalk was insufficient to trigger the CD4013B under any conditions of the circuits of Figs. 20 and 21. 24
~ E~IU--W..OF6 FEE RIBBON CABLE
=
90pF/62" 173pF/lft Fig. 21 Circuit simulating a ribbon cable system.
5. Noise energy immunity performance data Table III shows computed values of noise energy immunity for the gate, inverter, and buffer types identified above. Noise pulse width, Iv , and noise threshold voltage, VT, data were obtained directly from the I and 0 signal input ac noise immunity test curves presented earlier in Figs. 7 and 11. Values of Ro are typical output impedances for the CD4001B driving gate used in obtaining the curves. Figure 24 is a plot of high and low input state noise energy immunity for the CD4001B gate as a function of input pulse width. These curves show that noise energy immunity is high for noise bandwidths which exceed the speed capability of the
~--~-JJemgmmll plsmR
=mmmc_-smE:l ~~ mB ml ml mi mn m- mm mm mm
.~mm._.~m~-I
lmillm~immm ~oo.,V i m t l m m m m l m m l m m ,,.,,.,oo, •v,,-:lmilllilmmI , . , . , , I._~_~IN~.~Mmiv,,.,, 'v'*'lmmilummmmmlmmmmmmmm o,,,,.
mmmmmmmmmmm ,v,,. l m m m m m m a m m m m
,v,..iw~mnmr,
voo.,v ',",'~"
i
Voo., v
,v,,.
,,.,,.,o..
"V/N " ""
mmmm
,V.~, . . ", o,,,,,
''"
lmmm,V, t l l l V A i
,v,,. tb)
Io)
eZCS-lt$1T
Nmiilmmmm-iil jmlm iN ., mpmimmammmm voo.,ov mmmmmmammmm ,,.,,.,o.. 4v,,.llllalilmlmmmlmi ,.~,., '" mlmmmmmmmmm , ., ,' ., ., ,- ' mmommm~)qmi v,.. mmimmmmmmmm , - . ,,,,,,, l i i m F t a l l l I H r / I '"'" iir£amiimr~ialJl o,,,,t llml1111iwmi ,v,,. lmmmMmmm~mm ~I
%0.,0 v 4V/cm
lit '11 • I011| | * | MHi VIN'IE 0 STATES
I V/cm
(b)
(el
|ZC5- ZSm!l&t)
(d) HC$- ]e$~e4
mnnnnauummi am|nn|n|nl .,,o ,,,:.,.
aaataaaaHan
Munnmmumini
',",'o" "'~"'
Voo"" If'Ira lobs
;.-mnn;;;mnt,.;l
V,.a,.
E U m l l i R l l i l
p~'.. _ B _ . t . _ m d _ u _ ! i
ll;!ilUP~ialll
VDO'|~' V
,.,...
.v..lllllgllHlllllllllllm
o,,,,,,
4,,~. ~ : ~ ] ~ , ~ l H l l n l ,m q l ~ " ~ ;~"--mTl)lmmlmmi
V|N"
'"'-
|,,.,,.,o., " I MHI~
4V/(;~
v..
o ,,,,t .v...
U m ~ i H a ¢ l l 1¢ I
(e|
~ZCs-Zl315
[f| IlZC$*Z$lSd;5
Fig. 22
C r o s s t a l k in r o u n d - t a b l e system.
T a b l e III
Type
Supply Voltage
Fig. 23
C r o s s t a l k in r i b b o n cable system.
Typical Values of Noise Energy Immunity
Noise Pulse Width
Noise ThreshoM Voltage
Typical Signal Line Impedance
tp(ns)
Vt(V )
R O (ohms)
Typical Noise Energy Immunity* Logic State
VDD
CD4001UB
CD4001B
CD4011UB
CD4049UB
CD4049UB
5 10 15 5 10 15 5 10 15 5 10 15 5 10 15
(V)
Low
High
Low
High
Low
High
ROL
ROH
ENL(rd)
ENH(nJ)
100 60 40 160 80 40 100 40 60 60 40 60 150 60 40
100 40 40 150 40 40 1~40 80 40 120 40 40 150 60 60
2.75 6.3 9.0 2.58 6.2 9.6 3.0 5.0 6.9 2.0 3.7 4.9 2.75 6.4 8.7
2.65 5.1 7.0 2.85 5.6 7.8 2.67 5.45 9.1 2.9 6.7 10.4 2.60 5.2 8.0
700 270 190 700 270 190 700 270 190 700 270 190 700 270 190
700 270 190 700 270 190 700 270 190 700 270 190 700 270 190
1.08 8.82 17.05 1.52 11.40 19.40 1.29 3.70 15.03 0.343 2.03 7.58 1.62 9.10 15.94
1.00 3.85 10.32 1.74 4.65 12.81 1.43 8.80 17.43 1.44 6.65 22.77 1.45 6.01 20.21
* E~ -
Vt2
(~)
Ro 25
Noise i m m u n ~ of CMO$ i n t e g r a t ~ circuits continued from page 25
14-0 ' =2s°c
--i--
r
--
i
/
T
"C'~503-B--
5M'.__.~ 'TA=25"0
-3
>-
ViN
/
i,
/
~: tN:EFFECT~/ / z "' 2C
0
,-
100
VDD=!©VVi~
200
300
t~ lJJ
z
/
..........
400
PULSE WIDTH ~,,p)ns
I
.VDD =
500
/
/
/
VIN=HIG 100 200 300 PULSE WtDTH (tp)ns
400
500
Fig. 24 High- and low-input state noise energy immunity for the CD4001B gate as a function of input pulse width; TA=25°C.
device, and a minimum of approximately 1.3nJ where the noise pulse width (50 to 100ns) approximates the device output transition time. Noise threshold energy increases steadily with greater pulse widths.
6. ConcJusions The noise immunity test data demonstrate the high noise immunity of CMOS digital integrated circuits. Typical ac noise voltage immunity for an unbuffered gate is 2V for a 5V supply, 5V for a 10V supply, and 7 volts for a 15V supply. As expected, the tow level ac noise immunity for the CD4049UB buffer is slightly lower because of the lower effective input threshold of the large N M O S transistor used. Of paramount interest is the good noise energy performance of approximately 1.3nJ for B-series gates, which is comparable to the performance of bipolar TrI. gates at 5V despite their much higher output drive current. For operation above 5V the noise energy immunity of CMOS devices ranges up to 20nJ at 15V, far exceeding the noise energy immunity of TTL. This
26
improved noise immunity makes CMOS logic devices far more economical than TI% for use in high noise automotive and industrial control environments. This noise rejection capability exceeds even that of bipolar high threshold logic, which has only approximately 5nJ of noise energy rejection in the high logic input state. The good inherent noise immunity provided by CMOS devices leads to design economy, and complements the accompanying benefits of CMOS, i.e. low cost, medium to high speed operation, wide operating voltage range, good temperature stability, wide selection of SSI, MS1, and LSI device types. 7. References [1] Funk, R. E., "Understanding Buffered and Unbuffered CMOS Characteristics", RCA Solid State Application Note ICAN-6558. [2] Eaton, S. S., "Noise Immunity of COS,~:[OS Integrated Circuits", RCA Solid State Application Note ICAN-6176. [3] Bosen, Verell, "Designing Logic Circuits for High Noise Immunity", IEEE Spectrum, Jan. 1973. [4] JEDEC Standard for B-series COS/MOS Devices.
Sources of noise in Iog!c circuits are discussed and definitions stated. The good noise performance of CMOS devices is then explained.
1. Introduction The excellent noise immunity of CMOS digital integrated circuits is a paramount reason for their preferred and successful use in high noise automotive, process control, production monitoring, and similar noisy applications. The development of the RCA B-series CMOS devices improves the well known noise immunity advantages of this technology in two important ways: (i) Improved noise energy immunity as a result of balanced low impedance output circuitry. (ii) Standardised (EIA-JEDEC standards) dc noise immunity and noise margin ratings for buffered and unbuffered CMOS-logic types. 2. Logic system noise concepts Successful application of any digital logic IC family requires consideration of the following: (i) Externally or internally generated noise- both radiated and conducted. (ii) The inherent noise immunity capability of the logic family selected. (iii) System noise rejection measures. Without co-ordination of these three points, a system design may perform unfavourably. Consider first the various system or environmental noise generating sources. External system noise may include the noise imposed upon a logic system by electric motors, welders, rf transmitters, X-ray machines, high current solenoids or relays, pulsed lasers, and circuit breakers. All of these emit electromagnetic interference, and many produce power line or ground path noise disturbance. External noise is Characterised by randomly occurring high energy transients which are not easily anticipated. Usually, this noise is coupled electromagnetically or capacitively to signal, supply, tRCA, Sunbury-on-Thames, UK.
and ground lines. Internal logic system noise is usually g e n e r a t e d on logic signal lines by capacitively coupled
crosstalk or by logic switching current surges on supply lines or ground lines. In ultra-high speed logic families such as ECL, reflection noise resulting from an impedance mismatch is also an internal noiseproblem, but because of relatively long output transition times of CMOS devices (more than I0ns), reflection noise can be excluded from further consideration. Since both external and internal noise must be considered, logic systems must be designed to survive in a medium-to-se~,ere noise environment, a fact that leads to the second consideration: selection of an IC logic family having noise rejection characteristics appropriate to the application. No matter how good the noise rejection capability of an IC logic family system design measures to reduce noise entry into logic signal lines, power supply lines, and the ground are usually necessary. The methods most commonly used to minimise noise effects in CMOS logic s y s t e m s are as follows: (i) Power line decoupling. Good practice suggests the use of a small value series resistor and zener diode and a capacitor to ground on each logic
card or for each 50 to 100 integrated circuit packages. High voltage supply transients can usually be rejected by this simple m e a s u r e . Separate lines should be used for logic circuits and power switching circuits. (ii) Ground line noise. In a system involving many high current switching components, such as motors, relays, and SCRs, logic grounds should be separated from high energy component grounds. The logic grounds should be returned to a common point. (iii) AC noise on system signal inputs. 6 0 H z is a commonly used frequency reference. Raw ac power lines should be isolated using a transformer or optical coupler. Zener diode
MICROELECTRONICS JOURNAL Vol. 10 No. 1 © 1979 Mackintosh Publications Ltd., Luton.
1R
Noise Immunity
of CMOSintegrated circuits c o n t i n u e d f r o m p a g e 15
limiters are also effective. 60Hz signals can be shaped by using CMOS Schmitt trigger circuits. 3. Noise specifications CMOS noise immunity is characterised by dc specifications, ac noise immunity performance, and noise energy immunity performance. Each of these characteristics is defined below.
3.1 DC specifications Table I shows the industry standardised (JEDEC) noise immunity and noise margin ratings, Vn. and Vra. Table I
JEDEC Standards for dc Noise Immunity -
Characteris//c.$
Test Conditions
VDD (v)
V0
(v)
Input
Voltage (v)
upsetting the logic or causing any output to exceed the Vo ratings of Table I. Of the two CMOS dc noise definitions, immunity and margin, RCA prefers the noise immunity specification as the more practical definition because CMOS outputs are normally 50mV off the rails. However, designers familiar with TTL may prefer to use the noise margin voltage for system analysis. AC noise immunity CMOS ac noise immunity takes into account both the device switching threshold (de noise immunity) and the noise pulse width. The latter is affected primarily by the CMOS integrated circuit band-width, especially output transition times. Figure 1 shows the usual CMOS noise voltage amplitude, Vt, as a function of noise pulse width, tv. 3.2
' Input lowvoltage VIL max.
B types.
0.5•4.5 1/9 1.5/13.5 0.5/4.5 1/9 1.5/!3.5
UB types
5 10 15 5 10 15
1.5 3 4 1 2 2.5
" Input highvoltage Vm nan. '
0.5/4.5 1/9 1.5/1315 0.5/4.5 1/9 1.5/13.5
5 10 15 5 10 15
3.5 7 11 4 8 12.5
Note that separate specifications have been established for B (buffered) types and UB (unbuffered) types. 1 Two important noise characteristics can be defined by using the V~ and Vm ratings, • (i) N o i s e immuniW..The V I L and Vm limits are the deyice input signal noise immunity ratings which, as defined in Table II, are 30%, 30%, and 27%, respectively, of the 5, 10, and 15V supply voltages. Percentages are lower for unbuffered gates, as shown in Table II. The Vn. and Vm ratings define the maximum permissible additive noise voltages at an input terminal when input signals are 50mV off the supply rails. B-series Noise Immunity and Noise Margin (TA=25°C) Noise lmmuhity (%) Noise Margin Voltage (V)
VDD
B-series
UB-series
B-series •
UB-series
10
30 " 30, 27
20 20 17
1 2 2.5
0.5 1 1
(ii) N o i s e margin. The difference between VrL and Vo or Vm and Vo is the device noise margin voltage for the non-inverting case. Table II designates the B and UB noise margin voltages. Noise margin voltage is defined as that noise voltage which can be impressed upon Vrs at any (or all) logic input/output terminals without 16
~
t"-i it_ 5; <
V t h mif
LIBtypes
15
ILl
Ul
B types
Table II
>
I I I I I tpmin
-J
o> i O9
o Z
POINT usED FOR CALCULATION _..~ENmin' OF FIG.2
"-
NOISE PULSE WIDTH (to)ns Fig. 1 Generic ac noise immunity curve.
Because noise pulses are narrow compared with device output transition time, noise voltage rejection is high. As the pulse widths approach the IC bandwidth, the curve flattens out at the device switching threshold voltage. AC noise voltage immunity curves, such as those in Fig. 1, are applicable to: (i) Positive noise pulses on signal lines in the 0 state. (ii) Negative noise pulses on signal lines in the 1 state. (iii) Positive noise pulses on the ground terminal. (iv) Negative noise pulses on the positive supply terminal. Curves of this type indicate the frequency (as defined by noise pulse characteristics)at which the user has satisfactory de noise performance. The curves are especially useful in calculating typical noise energy performance, a parameter which takes into account the circuit impedance. 3.3 Noise e n e r g y immunity Noise energy immunity takes into account the pulse width and the circuit impedance at the point where the noise is introduced. Noise energy immunity is calculated as follows:
E~
=
~ : Ro
~,
Figs. 3 and 4 and Table I indicates that the values of Vn. and Vm for these devices are well within the standard J E D E C specifications. The Vm and VxHvalues for any typical CMOS device indicate a typical de noise immunity close to 50% of the supply voltage, a paramount advantage of CMOS logic devices over TI'L, ECL, PMOS, and logic devices.
el
A
z
ILl
>(.9
3D4OO1UB IA=23"C
f,/) .,..,
rr uJ
zLM ENmi n
I.IJ
O
15
I I
I
to O z
tpmin NOISE PULSE WIDTH __(tp)ns
D O >
r
(.9 10
Fig. 2 G e n e r i c no~se energy immunity curve. where F_mis noise energy immunity in nanojoules, Vth is the device switching voltage threshold for a given noise pulse width, tv is the noise, voltage pulse• width in nanoseconds, and R0 Is the impedance to ground in ohms at the point of noise entry. Ro is usually the output resistance of the CMOS device. By using values, of V and Iv obtained from the curve of Fig. 1, the noise energy immunity curve of Fig. 2 is generated for a given value of Ro. A comparison of Figs. 1 and 2 shows that the minimum values of noise energy immunity occur ~t an input noise pulse width for which the noise voltage amplitude of Fig. 1 begins to approach the dc noise immunity or threshold voltage of a device. The minimum noise energy immunity is the basis for the calculationsand comparisons involving most IC families. 4. N o i ~ i m m u n i t y t e s t 4.1 De noise immuniW test data CMOS dc noise immunity performance is obtained by plotting the voltage transfer characteristic of a CMOS gate, inverter, or buffer. Figures 3 and 4 show the voltage transfer characteristics of the CD4001B, a buffered qua d 2-input NOR gate, and the CD4001UB, an unbuffered version of the same gate. Comparison of
CD4001B TA=23"C
o~
15 FD
~.-
-d
0 > 12.
F-0
L
0
5
Fig. 4 CD4001UBvoltage transfer characteristic. 4.2 AC noise immuniWtest d a t a Figure 5 shows the test circuit used in the evaluation of the ac noise immunity of B-series CMOS devices. The criterion used is the triggering of a typical CD4013B flip-flop at the clock input. The circuit of Fig. 5 accounts for typical CMOS loading factors and generally reflects the ac noise performance of typical B-series devices. The device types used in the evaluation include the following: (1) CD4001UB unbuffered quad 2-input NOR gate (2) CD4001B buffered quad 2-input 2-input NOR gate (3) CD4011UB unbuffered quad 2-input NAND gate (4) CD4069UB hex inverter (5) CD4049UB hex inverting buffer. The above list includes the most commonly used CMOS gates, inverters, and buffered devices. The ac noise immunity characteristics of the buffered NOR gate (CD4001B) reflect the noise immunity performance of buffered CMOS products of all descriptions. D
'VDD
I I
II
v;s
I' I I I
I-
O.~F
0
5
10
_J-I_
15
-U-
INPUT VOLTAGE (VIN)Volts Fig. 5 Fig. 3
15
I
g
0
10
INPUT VOLTAGE (ViN}Volts
~
' " 10 < i--.J 0 >
\
CD4001B voltage transfer characteristic.
I
I '
~_1_ /
Vss
MONITOR FOR STATE CHANGE
Test circuit used in the evaluation of B-series C O S / M O S devices. 17
N o i s e i m m u n i t y of C M O S i n t e g r a t e d circuits continued from page 17
4.3 Signal line or external noise immuniW The following analysis was used to determine the immunity o f a CMOS gate to noise on the input line at both the 0 (low level) and 1 (high level) logic states. 0-state analysis. The signal line noise immunity of CMOS gates and inverters was evaluated by means of the test circuit shown in Fig. 6. The CMOS units tested were the same as in the previous test. Figure 7 shows the results obtained. The test circuit is designed to measure the voltage required at the input of the unit under test to trigger a CD4013 flip-flop. VDD
ALL UNUSED
,
c
[
oo,
o
,CD IUB: 0.1~E =
1
,, I
_L
CD4069UB CD4049UB
J-L_ Fig. 6 Test circuit used to evaluate signal line noise immunity of CMOS gates and invertors.
During test, a positive going noise pulse is introduced into the signal line of the unit under test. At some voltage level, depending on the width of the pulse and the gate thresholds, this pulse causes the flip-flop to be clocked via the CD4001B gate. This voltage level defines the permissible input range for a logical 0. A de analysis of the transfer characteristics of the components included in the test set-up can also be used to determine the noise level required to clock the flipflop. Figure 8a shows that a signal of 4.15V is required at the input to the CD4001B gate to produce an output of 4.5V at a supply voltage, VDD, of 10V. Figure 8b shows that an input of 5.25V is required to trigger the CD4013 flip-flop at a supply voltage, VDD, of 10V. All measured values shown in Fig. 8 were obtained from measurements on gates that have typical threshold switching characteristics. Careful analysis of the ac noise curves of Fig. 7c (for the CD4049UB) for 0-state signal line noise shows a voltage pedestal effect occurring at noise pulse widths associated with the noise threshold region of the units under test. A comparison of the voltage transfer curves of Fig. 8c with the dynamic input capacitance curves for the CD4049UB (Fig. 9) reveals that this pedestal effect occurs in the same region as the peak Miller input capacitance, where the inverter is in its maximum linear gain region. Most 0- and 1-state noise voltage characteristics curves in this article exhibit this pedestal effect to some degree. 1-state analysis. Figure 10 shows the test
16 I 14 >- 12 ~10 •. 3 8 ~x~x ~. ~g -- 6 i
%_1 ~
~-
52 0
0 z
200 400 PULSE W I D T H - ns CD4001B, CD4OO1UB 100
(a)
-l O- V
I 300
z
> lCt , ~12
•--CD4011UB
500
crcC
21 100
0
(b)
200 300 400 PULSE W I D T H - n s
CD4011UB
TA=25"CI
1
Jr~= IB-V uJ
. . . .
03
I--
- - -
0 Z
0
100
200 PULSE
(c)CD4049UB,
300 400 W I D T H -ns
500
CD4069UB
Fig. 7 Results oflYstate signal line noise immunity tests. 18
'
I
io
'nn=15Vl
-<---
TA=25" q
> 14, 12 10 8
.--CD4~JOIUB cn,~ 3131R
500
20
>o I-
20
CD4OOIB TA=25"C
OD4OI3B TA=2~ C
(/}
VDD=15V 15 F-
O >
>O 10
< t-J o > I13.. IE:) O
1OV "(.9 ' <
VIN
I(
~IN =
-.15~
0> I-
5V
5.25V
0-
I-
I
0
o 10
5
15
O
INPUT VOLTAGE ( V l N ) V o l t s
5
O
15
INPUT VOLTAGE ( V i N ) V o l t s
(a) CD4OO1B
(b) CD4013B 20
CD4049UI TA= 25"C
03
t-
15
O > " ' 101 (.9 < !-V .-
,J
O > f-
PEAIC MILLER NPUT / C A P A C I T A N C [ REGION / ~ _ WHERE PEDE= T A L
~
4~ ' =~ ' ,'uv~/ "
"-EFFECTOC(:URS
5
IO O
10
5
15
INPUT V O L T A G E ( V l N ) V o l t s
(c) CD4049UB Fig. 8 Transfer characteristics of components used in the circuit of Fig. 6. 14_ Q.
.
140 z
CD4049t.W
A L L UNUSED INPUTS TO GND.
120 ,,I.I
T
I
< a.. <
80
Iv ~ v 10v
60
I." z
40 20
,< z>.r',,
O
ev.,,,r406o.1 T
k._ 5
10
5
20
]J
INPUT V O L T A G E {ViN)Volts
Fig. 9 Dynamic input capacitance curves for the CD4049UB; TA--250C,
Fig. 10 Test circuit used to measure noise immunity of CMOS logic gates and inverters when input is high and a negative going pulse is superimposed on the signal line.
Noise immunity of CMOS integrated circuits continued from page 19
1E
•~ C D 4 O O 1 U B C D4001B TA= 25"C
>14 I
,
10\ b-W
Ill
O
i
1OO
CD4OIIUB TA=25"(~
,'DO='15 5 z
>,
/DO=15V ~E IOV m
5V
....._.._
o z
200 300 400 PULSE W I D T H - n s
(a) CD4OO1B
500
O
1OO
5OO
(b) CD4011UB
CD4OO1UB
D
--
! 1
200 300 400 PULSE W I D T H - n s
d
UB
TA= 25"C
.
.
.
.
.
.
! - L~l.,n
,~-
[
Lo_
O O
100
200 PULSE
300 400 WIDTH -ns
(c) CD4049UB, CD4069UB
500
T A = 25°C
Rg. 11 Results of 1-state signal line noise immunity test.
arrangement used and Fig. 11 the results obtained from noise immunity measurements on the CMOS logic gates and inverters identified above when the input is high and a negative going pulse is superimposed on the signal line.
voo I REQU ,,
tll
vd6.
,. -
,
R G.
)VDD1
o
I-..---CD4,O~IB I
[ t:.L__~.
Ill
oFo r _ ~.~ CD4OllUB '1
,,b
-=-
CD404~,CD4069UB t ~ ALL UNUSED INPUTS TO GND. EQUIVALENT RESISTANCE REQU (ohms) 1OO 50 33 25
MINIMUM PULSE WIDTH ~ (nanoseconds)
53.4 55.5 47.5 51.1
4.4 Power supply noise immunity The test configuration shown in Fig. 12 measures the ability of test units to withstand a negative going noise pulse superimposed on the supply line without a change in state. Figure 13 shows results of tests. A pulse of sufficient amplitude causes the output of the gate to decrease so that, at some point, the CD4013B flip-flop is triggered from the rising voltage at the output of the driving inverter stage. It should be noted that two power supplies are used in the arrangement of Fig. 12. An equivalent resistor or inductor for simulating contact resistance and lead length is used in the VDo line of the unit under test. Without this resistance the test unit will not react to the noise pulse. 4.5 Ground noise immunity Noise on the power line may be effectively reduced or eliminated by the use of decoupling capacitors; however, ground line noise cannot be reduced so easily and, therefore, is more objectionable. Figure 14 shows the test circuit used to measure the ground line noise immunity of CMOS gates and inverters. Figure 15 shows curves of the results obtained. Again, the units under test would not react to the noise unless a 25f~ resistor or small inductor simulating lead length or contact resistance were placed to ground.
VARIATION THE RESULT OF WAVE SHAPING
Fig. 12 Test circuit used to measure the ability of test units to withstand a negative going noise pulse on the supply line without a change in state. 20
4.6 Crosstalk noise immunity A test circuit used to evaluate crosstalk is s h o w n in Fig. 16. A noise pulse from a pulse generator is coupled to
16't
,\
>14
>- 12 FEE
16
[A=Z~C
.--~:I.~
~
"
,
TA~'25"Ci • ~CD4OI1UB
12
yDb=~SV I - . -
.
.
.
.
'
8
,
10~
-
0
100
500
300 400 PULSE W I D T H - ns 2O0
0
('a) CD4OO1B, CD4OO1UB !
bY
I
o z
I::;U
.~2 z
IOO
20O 300 400 P.ULS E W I D T H - n s
500
(b) CD4011UB
TA--25-CI
f
z ~ 8 -
6
I
to 4
.....
J___
~2 z
100
0
2O0 300 400 PULSE WIDTH -ns
(c)CD4049UB,
''1
:1
5O0
CD4069UB
Fig. 13 Power line noise immunity.
the signal line of the gate or inverter through a capacitor. The noise voltage necessary to trigger the flip-flop is then measured for different values of capacitance under high and low input conditions. Figure 17 shows the effect of capacitance on the inputs of the units under test. The circuit shown in Fig. 18 more closely approximates crosstalk caused by adjacent signal lines. The response of the test circuit to a noise pulse may be
CD4OOIB
(1)
CD4OO1B CD4OOIUB
I
~D~ RTER I~'
Q~---o
explained by analysis of the response of a high pass RC circuit to a ramp input of Vi=~t, where ctis the coefficient of coupling and t is the rise time, 10 to 90%. The output voltage V0 may be expressed by the following equation: V0=aRC (1-e-vRc) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(1)
The equivalent circuit for the part of the test configuration used in this analysis is shown in Fig. 19. On the basis of this equivalent circuit, equation (1) may be rewritten as follows: V~(max) = :c (ZoI[z~ C[1--et~(zdlzt")Cl . . . . . . . . . . . . .
(2)
If V, is assumed to be ~.t during the period in which the output voltage switches from 10% to 90% of its total value, this change in output voltage can be expressed as follows:
.
_L _vo
jv0o
-r-- v~7~ . . . . ....
.~
~ . v ~ 9 U
.~OR
|
B
•
v,(z41z~)c [1--e-tr2(Z~lzlI 1 . . . . . . . (3)
AL, UNUSEO iNPUTS TO VSS
CO4049UB
~,25a~59p ~ 0.1/.F
~" r,~N _--L. ___-4-
AVo(max) "~
I ~ PULSE ~ __J L-- GENERATOR
Fig. 14 Circuit used to measure ground line noise immunity.
The results of this analysis may be applied to the various crosstalk waveforms obtained. Crosstalk measurements which simulate actual operation are made by means of the test Circuits shown in Figs. 20 and 21. The circuit of Fig. 20 simulates a round cable system and Fig. 21 a ribbon cable system. 91
Noise immunity of C M O S i n t e g r a t e d circuits continued from page 21
16
1E >I 14 >- 17 t-
,:~Cu4u(J]U~ ~- - C.D_4OO1B
,
~D~v
~4 5z 2 0
i100
-r
I
-~ 6
Vnrr=15~
-i or;,
~. 4
i
0v
7° 2I
500
0
(a/ CD4OO1B, CD4OO1UB
100
200 300 400 PULSE W I D T H - n s
500
(b) CD4011UB CD4OllUB
16
VDD=IO~. tp =25 -] 3Ons
> 14 ,,, 12 (.9
o ai > 13'
v,1
0Z 0
'--.CD4011UB '
I
-~ 200 300 4OO PULSE W I D T H - n s
[[A=25"C I
t 14 ~ 12
200
400
(c)CD4049UB,
600
800
1000
CD4069U B
Fig. 15 Ground line noise immunitymeasurements.
~
GATE UNDER
D
TEST
CD4OOIB CD4OO1UB
_L
CD4OllUB
4069UB
--C
49UB
ALL UNUSED INPUTS TO GROUND
Fig. 16 Circuit for measuringnoisevoltageas a functionof couplingcapacitance. 22
Fig. 18 Circuitcloselyapproximatingconditionsforcrosstalk on adjacent signallines.
"1
> 14 ' 12
kkl
~
2C
CD40(~UB CD4OC~B VDD:SV tpff 5 0 - 6 0 n s
't ~
o
I ~
i le i 14 12 IC
-~- ---vtt_
qI
tp=i5-3On~
\~ '~ ...... L~--- - L _ _ _ ! _
8
0
1OO 200 300 400 500 600 COUPLING CAPACITANCE-pF
28 26 >24 t22
,w
viii >
12 ~8
CD4011UB VDD=15V tp : 30-35n., =
'.4
UJ
>o
om
,,,14
~_
c/}
zlO
VIL O
200 4( COUPLING
0
~, 16 t 14 >~ 1 2 ~_~.
)O . IOOO CAPACITANCE- pF
'~CD~O49UB' CD4069UB
16 >14 212
CD4OllUB VDD=5V tp=50-6Ons
06
VIH
N4
2
VIL
0
z
200 3t IOO PULSE WIDTH - ns
~2E UJ 2,4
400
100 2 0 0 300 400 500 600 COUPLING C A P A C I T A N C E - p F
500
2C
CD21049UB CD4069UB VDD = 5V tp=50-6)ns
1-2C -J 0 1E
,,,16 14
1
T-
4 0 0 5OI 1OO 2 0 0 3 0 0 COUPLING CAPACITANCE- p F 28 ~24,-
~
~2C
'
--CD4049UB .CD4069UB
! ~,
voD= lOV
tp=~5-3Ons
\"~-__~ ~V,H \,'-----'~- ' _ ~--i-' . . . . . ,'------~-i";-V,L--!--
'"on 8 I.
O
200 400 600 800 1OOO COUPLING CAPACITANCE-pF
t
__-LS_V
0
VIH
LU
v,L 8 6
. . . .
200 400 600 800 1000 COUPLING C A P A C I T A N C E - p F
0
CD4OOIUB , .CD4OOIB VDD=I5V tp= 30 -35n:
1T;3,, - 7 • IL~
•
6
0 z
'--CD4OOIUB • CD4OO1B VDD =lOV _
O
0
10OO 200 400 600 800 COUPLING C A P A C I T A N C E - p F
-~- CD4049 U B --CD4069UB VDD = 15V tpi30-35n
"~
Ill
~4 0
z
O
200 400 600 800 lOt O COUPLING CAPACITANCE-3F
Fig. 17 Effect of coupling capacitan~:e on the inputs of the unit under test (TA=25°C).
Noise immunity of CMOS integrated circuits continued from page 23
=OUPLING > Zin ~OEF >GATE FICIENT >UNDER TEST
Zo GATE > UNDER > TEST
VIN Fig. 19 Equivalent circuit used in crosstalk analysis of test configuration shown in Fig. 18.
CD4013B B
~_
CD4OllB
CD4OO1B
I
~-J~gUB CD4049UB
L
!LO
0T
~-~ I -
VDD
-•
o
i
I
o
EQUIV. OF 6 FEET OF ROUND CABLE ALL WIRES ONE WIRE 94.7 pF/60 in. 56.1pF/60 in. 18.9pF/ft 11.2p/ft. Fig. 20 Circuit simulating a round cable system.
In Fig. 20, a sense line is placed tightly within five surrounding wires (No. 22 gauge) to form a 6 feet long cable with a capacitance of 18pFper foot (determined by measurement). In Fig. 21, a sense line is placed between two adjacent driving lines (No. 22 gauge) ofa 6 feet long ribbon cable with a capacitance of 16pF per foot (determined by measurement). The results of crosstalk are shown in the photographs of Figs. 22 and 23 for round cable and ribbon cable, respectively. The crosstalk was insufficient to trigger the CD4013B under any conditions of the circuits of Figs. 20 and 21. 24
~ E~IU--W..OF6 FEE RIBBON CABLE
=
90pF/62" 173pF/lft Fig. 21 Circuit simulating a ribbon cable system.
5. Noise energy immunity performance data Table III shows computed values of noise energy immunity for the gate, inverter, and buffer types identified above. Noise pulse width, Iv , and noise threshold voltage, VT, data were obtained directly from the I and 0 signal input ac noise immunity test curves presented earlier in Figs. 7 and 11. Values of Ro are typical output impedances for the CD4001B driving gate used in obtaining the curves. Figure 24 is a plot of high and low input state noise energy immunity for the CD4001B gate as a function of input pulse width. These curves show that noise energy immunity is high for noise bandwidths which exceed the speed capability of the
~--~-JJemgmmll plsmR
=mmmc_-smE:l ~~ mB ml ml mi mn m- mm mm mm
.~mm._.~m~-I
lmillm~immm ~oo.,V i m t l m m m m l m m l m m ,,.,,.,oo, •v,,-:lmilllilmmI , . , . , , I._~_~IN~.~Mmiv,,.,, 'v'*'lmmilummmmmlmmmmmmmm o,,,,.
mmmmmmmmmmm ,v,,. l m m m m m m a m m m m
,v,..iw~mnmr,
voo.,v ',",'~"
i
Voo., v
,v,,.
,,.,,.,o..
"V/N " ""
mmmm
,V.~, . . ", o,,,,,
''"
lmmm,V, t l l l V A i
,v,,. tb)
Io)
eZCS-lt$1T
Nmiilmmmm-iil jmlm iN ., mpmimmammmm voo.,ov mmmmmmammmm ,,.,,.,o.. 4v,,.llllalilmlmmmlmi ,.~,., '" mlmmmmmmmmm , ., ,' ., ., ,- ' mmommm~)qmi v,.. mmimmmmmmmm , - . ,,,,,,, l i i m F t a l l l I H r / I '"'" iir£amiimr~ialJl o,,,,t llml1111iwmi ,v,,. lmmmMmmm~mm ~I
%0.,0 v 4V/cm
lit '11 • I011| | * | MHi VIN'IE 0 STATES
I V/cm
(b)
(el
|ZC5- ZSm!l&t)
(d) HC$- ]e$~e4
mnnnnauummi am|nn|n|nl .,,o ,,,:.,.
aaataaaaHan
Munnmmumini
',",'o" "'~"'
Voo"" If'Ira lobs
;.-mnn;;;mnt,.;l
V,.a,.
E U m l l i R l l i l
p~'.. _ B _ . t . _ m d _ u _ ! i
ll;!ilUP~ialll
VDO'|~' V
,.,...
.v..lllllgllHlllllllllllm
o,,,,,,
4,,~. ~ : ~ ] ~ , ~ l H l l n l ,m q l ~ " ~ ;~"--mTl)lmmlmmi
V|N"
'"'-
|,,.,,.,o., " I MHI~
4V/(;~
v..
o ,,,,t .v...
U m ~ i H a ¢ l l 1¢ I
(e|
~ZCs-Zl315
[f| IlZC$*Z$lSd;5
Fig. 22
C r o s s t a l k in r o u n d - t a b l e system.
T a b l e III
Type
Supply Voltage
Fig. 23
C r o s s t a l k in r i b b o n cable system.
Typical Values of Noise Energy Immunity
Noise Pulse Width
Noise ThreshoM Voltage
Typical Signal Line Impedance
tp(ns)
Vt(V )
R O (ohms)
Typical Noise Energy Immunity* Logic State
VDD
CD4001UB
CD4001B
CD4011UB
CD4049UB
CD4049UB
5 10 15 5 10 15 5 10 15 5 10 15 5 10 15
(V)
Low
High
Low
High
Low
High
ROL
ROH
ENL(rd)
ENH(nJ)
100 60 40 160 80 40 100 40 60 60 40 60 150 60 40
100 40 40 150 40 40 1~40 80 40 120 40 40 150 60 60
2.75 6.3 9.0 2.58 6.2 9.6 3.0 5.0 6.9 2.0 3.7 4.9 2.75 6.4 8.7
2.65 5.1 7.0 2.85 5.6 7.8 2.67 5.45 9.1 2.9 6.7 10.4 2.60 5.2 8.0
700 270 190 700 270 190 700 270 190 700 270 190 700 270 190
700 270 190 700 270 190 700 270 190 700 270 190 700 270 190
1.08 8.82 17.05 1.52 11.40 19.40 1.29 3.70 15.03 0.343 2.03 7.58 1.62 9.10 15.94
1.00 3.85 10.32 1.74 4.65 12.81 1.43 8.80 17.43 1.44 6.65 22.77 1.45 6.01 20.21
* E~ -
Vt2
(~)
Ro 25
Noise i m m u n ~ of CMO$ i n t e g r a t ~ circuits continued from page 25
14-0 ' =2s°c
--i--
r
--
i
/
T
"C'~503-B--
5M'.__.~ 'TA=25"0
-3
>-
ViN
/
i,
/
~: tN:EFFECT~/ / z "' 2C
0
,-
100
VDD=!©VVi~
200
300
t~ lJJ
z
/
..........
400
PULSE WIDTH ~,,p)ns
I
.VDD =
500
/
/
/
VIN=HIG 100 200 300 PULSE WtDTH (tp)ns
400
500
Fig. 24 High- and low-input state noise energy immunity for the CD4001B gate as a function of input pulse width; TA=25°C.
device, and a minimum of approximately 1.3nJ where the noise pulse width (50 to 100ns) approximates the device output transition time. Noise threshold energy increases steadily with greater pulse widths.
6. ConcJusions The noise immunity test data demonstrate the high noise immunity of CMOS digital integrated circuits. Typical ac noise voltage immunity for an unbuffered gate is 2V for a 5V supply, 5V for a 10V supply, and 7 volts for a 15V supply. As expected, the tow level ac noise immunity for the CD4049UB buffer is slightly lower because of the lower effective input threshold of the large N M O S transistor used. Of paramount interest is the good noise energy performance of approximately 1.3nJ for B-series gates, which is comparable to the performance of bipolar TrI. gates at 5V despite their much higher output drive current. For operation above 5V the noise energy immunity of CMOS devices ranges up to 20nJ at 15V, far exceeding the noise energy immunity of TTL. This
26
improved noise immunity makes CMOS logic devices far more economical than TI% for use in high noise automotive and industrial control environments. This noise rejection capability exceeds even that of bipolar high threshold logic, which has only approximately 5nJ of noise energy rejection in the high logic input state. The good inherent noise immunity provided by CMOS devices leads to design economy, and complements the accompanying benefits of CMOS, i.e. low cost, medium to high speed operation, wide operating voltage range, good temperature stability, wide selection of SSI, MS1, and LSI device types. 7. References [1] Funk, R. E., "Understanding Buffered and Unbuffered CMOS Characteristics", RCA Solid State Application Note ICAN-6558. [2] Eaton, S. S., "Noise Immunity of COS,~:[OS Integrated Circuits", RCA Solid State Application Note ICAN-6176. [3] Bosen, Verell, "Designing Logic Circuits for High Noise Immunity", IEEE Spectrum, Jan. 1973. [4] JEDEC Standard for B-series COS/MOS Devices.