Design of integrated reversible fault-tolerant arithmetic and logic unit

Microprocessors and Microsystems 69 (2019) 16–23

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Design of integrated reversible fault-tolerant arithmetic and logic unit Kamaraj. A a,∗, Marichamy. P b a b

Mepco Schlenk Engineering College, Mepco Nagar, Sivakasi 626005, India PSR Engineering College, Sivakasi, India

a r t i c l e

i n f o

Article history: Received 31 December 2018 Revised 6 March 2019 Accepted 23 May 2019 Available online 24 May 2019 Keywords: Reversible arithmetic and logic unit KMD gates Quantum cost Fault-Tolerance

a b s t r a c t In recent years, design of low power high-speed nano computing systems have drawn more attention. Reversible Logic is a technique popularly used to design the computing systems to achive them. In a computer, the arithmetic logic unit (ALU) is the fundamental computing module. In this paper, a novel Reversible Arithmetic and Logic Unit is proposed, where a single module performs both arithmetic and logical operations. The possible arithmetic operation includes transfer, addition with carry, subtract, complement and increment. The possible logical operations are AND, OR, XOR, COPY and CONSTANT. The control signal is a key element which defines and alters the data path in order to produce either arithmetic or logical output. The fault-tolerant KMD gates are utilized to construct the ALU. Here, two approaches are discussed for the construction of ALU. In the first approach, ALU is constructed using KMD gates only, whereas in the second approach, combination of KMD, Toffoli and Fredkin gates are used. The functional realization is performed in Quantum Cellular Automata. Quantum circuit is also derived for the same. The obtained results are evident for the improved Quantum cost up to 69%, Constant input up to 40% and Number of gates up to 21% compared to the existing designs. © 2019 Elsevier B.V. All rights reserved.

1. Introduction The International Technology Roadmap for Semiconductors (ITRS) prediction states that, after Nanometer technology (beyond 2021), it is very hard to shrink the size of the individual transistor. Also, shrinking transistor would cause many second-order effects such as leakage power, heat dissipation, subthreshold and tunneling etc. A new technology must evolve in order to make the Moore’s Law alive in future [1,2]. Landauer proved that, any irreversible or conventional computation will dissipate KTln2 Joules (k is Boltzmann’s constant and T is the temperature) of heat since it loses bit information from input to output transition [3]. Many conservative logic schemes such as non-dissipative computation, billiard ball computation are proposed to overcome the heat dissipation. These computations are reversible in nature to have zero internal power dissipation [4]. Bennett introduced a logically reversible computing machine [5]. Initially researchers found, Feynman, Fredkin, Toffoli and Peres [6–8] reversible gates which are a fundamental building block for reversible logic design. Later HNG, MRG, DKG, RM & RUG [9–12] gates are proposed towards the construction of reversible functional units. All these gates are having reversibility property; some ∗

Corresponding author. E-mail addresses: [email protected] (Kamaraj. A), [email protected] (Marichamy. P). https://doi.org/10.1016/j.micpro.2019.05.009 0141-9331/© 2019 Elsevier B.V. All rights reserved.

of them are having universality property [13]; while very few gates are having fault-tolerance [14]. Fault-tolerance is necessary to have reliable fault-free reversible logic systems. Fault-tolerant gates are having parity preservation between inputs and outputs. So, in order to construct reliable reversible logic systems, their modules must be of Fault-Tolerant Reversible one. Simple arithmetic and logical operations are the basis for any data manipulation. Nearly, all the data manipulations and computations are derivatives of simple arithmetic and logical operations. So, Arithmetic Logic Unit (ALU) is the heart of all computing systems. There are some significant contributions are done in the design of ALU [9,11,12] using RUG, RM, and HNG gates. Though, these designs efficiently do all the necessary operations; they are lagging in fault-tolerance. Moreover, the arithmetic, logical operations are carried out in a distinct module; which degrades their performance factors. Therefore, it is necessary to design an ALU in a single structure with fault-tolerance. In this paper, a Reversible Fault-Tolerant ALU (FTALU) is designed using fault-tolerant KMD Gates. The significant contributions of this work is, • Fault-tolerant gates are introduced. • Designed a single structure which is capable of doing all the necessary arithmetic and logical operations. • Quantum realization of KMD gates and ALU structure; which proves that the proposed design is having better performance.

Kamaraj. A and Marichamy. P / Microprocessors and Microsystems 69 (2019) 16–23

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Table 1 Functionality and characteristics of the various reversible gates. S. No.

Gate

No. of IOs

R, U, FT

Characteristic expression

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

Feynman Fredkin Toffoli Peres HNG MRG DKG TSG MKG RM RUG

2×2 3×3 3×3 3×3 4×4 4×4 4×4 4×4 4×4 3×3 3×3

R, R, R, R, R, R, R, R, R, R, R,

P=A; Q=AB P=A; Q=A’BAC; R=A’CAB P=A; Q=B; R= ABC P=A; Q=AB; R= ABC P=A; Q=B;R= (AB)C; S=(AB)C (ABD) P=A; Q=AB; R=(AB) C; S=(ABD) ((AB) C) P=B; Q=A’C’AD’; R=(AB)(CD) CD; S=BCD P=A; Q=A’C’B’;R= (A’C’B’)D; S=(A’C’B’)D (ABC) P=A; Q=C;R= (A’D’B’)C; S=(A’D’B’) (ABD) P=ABC; Q=A’B+AC; R=A’C+AB P=AB+BC+CA; Q=AB+A’C’; R=BC;

U U U U U U U U U U, FT U, FT

This paper is organized as follows; Section 2 discusses certain preliminaries and basic definitions of reversible logic; Section 3 deals with the previously proposed reversible gates and ALU designs; Section 4 focuses on the design of FTALU and its capable operations; Section 5 spotlights the results obtained and its related discussions and finally concluded the research work.

Fault-tolerance is a method to preserve same parity between input and output vectors over one to one mapping of the reversible circuit [14]. The input and output vectors of any fault-tolerant gates are Iv {In-1 ,In-2 ,…I0 } and Ov {On-1 ,On-2 ,…O0 } where the following Eqs. (1) and (2) must be preserved for them:

Iv ⇔ Ov

(1)

2. Preliminaries and basic reversible logic definitions

In−1  In−2  . . .  I0 = On−1  On−2  . . .  O0

(2)

The reversible logic circuits are measured and validated with the following parameters; • Quantum cost Quantum cost is the cost of the primitive gate and it is calculated as the number of primitive logic gates (1 × 1 or 2 × 2) required to realize the circuit. Every 2 × 2 gate has same quantum cost unity [15]. For a gates greater than 2 × 2, the quantum cost cannot be found directly, so for the bigger gates implementation is done based on the quantum primitives [16]. • Garbage output and constant input The number of outputs added to make an (n, k) function reversible is known as garbage outputs. The word “constant inputs” is used to denote the pre-set value inputs that were added to an (n, k) function to make it reversible. The constant inputs are known as ancilla inputs. The relation between garbage outputs and constant inputs is [17,18]. Input + constant input = output + garbage • Logical calculations Logical calculations refer the total number of XOR (α ), AND (β ) and NOT (γ ) operations required to realize the function [16]. In other words, the hardware complexity of the circuit to generate the output is represented in terms of logical calculations. • Reversibility The function f(x1 , x2 … xn ) of n Boolean variables is called reversible if the number of outputs is equal to the number of inputs and any input pattern maps to a unique output pattern. In other words, the output of a reversible function is a permutation of the set of its input [17,18]. • Universality A reversible gate is said to be satisfying universality property only when it could be able to realize NOT, NAND / AND & NOR / OR functions. For example, NAND operation can be derived from a Toffoli gate by setting its third input as logic ‘1’ [13]. • Fault-tolerance

• Reversible gates Feynman, Fredkin, Toffoli, Peres are the fundamental reversible gates introduced in the earlier days of the reversible era. Later in the last decade, many reversible gates are proposed by the researchers such as HNG, MRG, DKG, TSG, MKG, RM, and RUG [9,11,12]. The summary of functionality and characteristics of various reversible gates are listed in Table 1. 3. Related ALU works Many works are done in the reversible logic field like adders, multiplexers, multipliers, logical units etc. [15,16,19]. The researchers concentrated on the development of arithmetic logic unit (ALU) in the reversible computing systems are presented in the literatures [9,11,12,20–23]. Initially, the reversible ALU designs are presented in [20–23]; which are performing simple arithmetic and logical operations (OR, AND, XOR, ADD & SUB) using basic reversible gates. Moreover, these structures are consuming many number of gates and also capable of producing lesser number of functions (max. of 8 operations) with more number of garbage outputs [12]. A set of reversible gates (HNG, MRG, PAOG, Feynman & Fredkin) are employed to perform 8 ALU operations [9]. In [11] a new reversible gate called reversible multiplexer (RM) is used for the construction of ALU, which performs 16 distinct operations. In a similar way, Reversible Universal Gate (RUG) gate [12] is utilized towards the construction of ALU that could perform 16 distinct operations. In both the cases, the ALU is doing arithmetic operations and logical operations in a separate functional module and also they are not fault-tolerant in nature [11,12]. So, From the Tables 1 and 2, the research of this paper is motivated towards, • The design of an integrated unit performing both arithmetic and logical operation in a single structure. • The ALU design must be Fault-Tolerant 4. Reversible KMD gates A new reversible gate is introduced in two ways, one is, heroic act of the existing reversible gates and another is the creation of new gate to perform the desired operation.

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Kamaraj. A and Marichamy. P / Microprocessors and Microsystems 69 (2019) 16–23 Table 2 Comparison of existing ALU structures. S. No.

ALU

Gates used

No. of operations

Characteristic

1. 2. 3. 4. 5. 6.

[9] [11] [12] [21] [22] [23]

HNG, PAOG, MRG RM RUG HNG, MG, UPG DXOR DPG, YAG

8 16 16 14 4 8

Less functionality; less number of gates More functionality; more number of gates; high quantum cost Less functionality; more number of gates and garbage.

Fig. 1. Block diagram (a) KMD Gate1 (b) KMD Gate2 (c) KMD Gate3 and (d) KMD Gate4.

Fig. 2. Proposed ALU architecture.

Here, we used four reversible gates named as KMD Gate1, KMD Gate2, KMD Gate3 and KMD Gate4 as shown in Fig. 1 (a–d) [25]. These gates satisfy the fundamental requirements (reversibility and universality) of a reversible gate [13]. In addition, they are also Fault-tolerant; i.e. EXOR function of the inputs and outputs are

equal (Parity preservation). The fault-tolerance of these gates is shown in Table 3. The Performance evaluations of KMD Gates for the 13 Standard Functions realization is shown in Table 4. From the table, it is proved that 1.76 numbers of gates on an average required to im-

Kamaraj. A and Marichamy. P / Microprocessors and Microsystems 69 (2019) 16–23 Table 3 Fault-Tolerance KMD Gates.

The ALU is an inherent building block of a computing device in today’s scenario. The expected requirement of an ALU must perform maximum possible operations with minimum hardware complexity. The proposed ALU structure is shown in Fig. 2. The significant signals of this ALU are three inputs (A, B & Cin), Select lines (SA , SB & SOP ) and Control Signals (Constant Inputs). The major functional units are Inverter, AND, OR, XOR gates and a 1-bit adder. The multiplexers are acting as a data router to forward the necessary signals from input to output result. The proposed structure has 3 major modules;

Fault-Tolerant KMD Gate1 Inputs

Outputs

Fault-Tolerant

A

B

C

P

Q

R

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1

0 1 0 1 1 1 0 0

0 0 1 1 1 0 1 0

0 1 1 0 1 0 0 1

• Input module: the 2 × 1 multiplexer selects either True of Complement form of the Input and forwards it to the next computing module. • Data processing module: It does the arithmetic and logical operations on the input data come from the input module. The possible list of arithmetic, logical operations are shown in Tables 5 and 6. • Output module: The data received from various functional modules are available in the output module; the select line of the 4 × 1 multiplexer decides which output has to be forwarded to the final Result.

Fault-Tolerant KMD Gate2 Inputs

Outputs

Fault-Tolerant

A

B

C

P

Q

R

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1

1 1 0 0 0 1 0 1

1 0 1 0 0 0 1 1

19

0 1 1 0 1 0 0 1

The proposed [12,13] which are,

structure

is

having

two

advantages

over

Fault-Tolerant KMD Gate3 Inputs

Outputs

• The same structure is performing both arithmetic and logical operations. • The input signals (A, B & Cin) are functioning as constant inputs also, which in turn reduces the number of constant inputs.

Fault-Tolerant

A

B

C

D

P

Q

R

S

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0

0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

The realization of the ALU architecture in reversible hardware is done in two approaches; Approach 1: All the functional modules (input, data processing and output) are realized only with KMD gates. Approach 2: The functional modules of the ALU are realized using the combination of KMD gates, Fredkin and Toffoli gates. In both approaches, the ALU is performing most popular arithmetic as well as logical operations. The possible list of operations and its related control signals are listed in Tables 5 and 6. The Select lines (SA , SB & SOP ) and the input signal (A, B & Cin) are providing various functionalities like Transfer, Addition, Increment, Subtraction and 1 s complement. Using the proposed reversible ALU architecture, 18 distinct operations (10 Arithmetic & 8 Logical) could be done; whereas in [11,12] only 16 distinct operations are possible and in [26] 12 distinct operations as shown in Table 7. Approach 1: In this approach, the KMD gates are utilized to construct the Reversible Fault-tolerant ALU (FTALU) architecture as

plement the functions and 18.23 is the average quantum cost is for the functions to be implemented using KMD gates. ∗ G—number of gates; ∗ QC— quantum cost V. Proposed reversible fault-tolerant ALU (FTALU) architecture Table 4 Performance evaluation of KMD gates. S. No

Standard functions

Toffoli

Peres

TR

Fredkin

RM

RUG

KMD

G

QC

G

QC

G

QC

G

QC

G

QC

G

QC

G

QC

1 2 3 4 5 6 7 8 9 10 11 12 13

F=ABC F=AB F=ABC+AB’C’ F=ABC+A’B’C’ F=AB+BC F=AB+A’B’C F=ABC+A’BC’+AB’C’ F=A F=AB+BC+AC F=AB+B’C F=AB+BC+A’B’C’ F=AB+A’B’ F=ABC+A’B’C+AB’C’+A’BC’ Average

2 1 3 10 5 8 8 1 9 6 4 2 2 4.69

10 5 15 50 25 40 40 5 45 30 20 10 10 23.4

2 1 3 10 4 6 7 1 9 6 4 2 2 4.38

8 4 12 40 16 24 28 4 36 24 16 8 8 17.5

2 1 2 9 4 7 8 1 6 5 3 2 2 4.23

12 6 12 54 24 42 48 6 36 30 18 12 12 24

4 2 3 4 2 5 6 1 5 1 6 2 3 3.15

20 10 15 20 10 25 30 5 25 5 30 10 15 16.9

2 1 2 3 2 2 3 1 5 1 2 2 2 2.15

70 35 70 105 70 70 105 35 175 35 70 70 70 75.3

2 1 2 3 2 3 3 1 1 1 2 1 2 1.84

62 31 62 93 62 93 93 31 31 31 62 31 62 57.2

2 1 4 3 2 3 5 1 1 1 2 1 1 1.76

18 9 36 27 18 27 45 9 24 9 18 9 24 18.23

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Kamaraj. A and Marichamy. P / Microprocessors and Microsystems 69 (2019) 16–23 Table 5 Reversible arithmetic operations. SA

SB

SOP

0 0 0 0 0 0 1 1 1 1 1

0 0 0 0 1 1 0 0 0 0 1

0 1 1 1 1 1 0 1 1 1 1

0 0 0 1 0 1 0 0 0 1 1

Result

Operation

Constant inputs

Inputs

A A+B A+B+1 A+1 A+B’ A+B B A B C (A.B)+(A+B).C A+B B+1

Transfer A Add Addition with carry Increment A SUB 1 S complement Transfer B SUM Carry 1 S Complement Increment B

B=1 Cin=0 Cin=1 B=1 A=0 Cin=Cin A=0

A=A A=A; A=A; A=A A=A; A=A; B=B A=A; A=A; A=A; B=B

B=B B=B B=B B=B B=B B=B; Cin=Cin B=B

Fig. 3. Proposed reversible fault-tolerant ALU architecture (Approach 1).

Table 6 Reversible logical operations. SA

SB

SOP

0 0 0 0 0 0 1 1

0 0 0 0 1 1 0 1

0 0 1 1 0 1 0 0

0 1 0 1 1 1 1 0

Result

Operation

Constant inputs

Inputs

AB A|B 0 1 A A B B (A.B)’

AND OR Constant Constant COPY EXOR COPY NAND

A = 0; B = 0; A = 1; B = 0; B=1 A=1 -

A=A; A=A; A=A A=A; B=B A=A;

in Fig. 3. The denoted variables in this Fig. 3 are; A, B, Cin—inputs; 1 or 0—constant inputs; G—garbage outputs and Z—final result. The functional modules of the Fig. 3 are derived as follows; the inverter function obtained from KMD gate1 for the inputs A & B, 2 × 1 multiplexer & XOR gate is derived from KMD Gate 3 and the other functions are derived using KMD gate2 & KMD gate4. The Quantum circuit of the above reversible fault-tolerant ALU is obtined in RCViewer simulator [24,25] as shown in Fig. 4a. The ALU structure is realized in quantum cellular automata (QCA) using Bennett clocking [5] as shown in Fig. 4b. Approach 2: Here, the Fredkin, Toffoli and KMD gates are used to construct the reversible ALU as shown in Fig. 5. The Fredkin gate replaces the KMD gate1 in the input module to invert the in-

B=B B=B

B=B B=B

Table 7 Number of operations in proposed reversible ALU. Type of operation

RM [11]

RUG[12]

NHG [26]

Proposed architecture

Arithmetic operation Logical operation Total

7 9 16

7 9 16

5 7 12

10 8 18

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Fig. 4. (a). Quantum circuit of proposed ALU architecture. (b). QCA realization of proposed ALU architecture.

Table 8 Performance measure comparison of proposed and existing ALU. Architecture

Arithmetic

Existing ALU architecture

Proposed ALU architecture

Method

RM [11]

RUG [12]

Logical RM [11]

RUG [12]

RM [11]

RUG [12]

Approach 1

Approach 2

Quantum cost Constant inputs Garbage outputs No. of. gates used Logical calculation

140 2 6 4 2α + 8β + 3γ

67 0 3 3 3α +β

140 2 7 4 α +9β +4γ

94 1 6 4 α +6β +6γ

320 10 15 14 8α +20β +9γ

197 6 11 14 9α +12β +11γ

118 6 21 11 12α +14β +6γ

99 7 22 11 12α +14β +6γ

puts A, B and Toffoli gate replaces the KMD gate2 & KMD gate3 to generate AND & XOR logic function. Here, the positive side of the design is, quantum cost and the number of garbage outputs are reduced. 5. Results and discussion Quantum cost, garbage outputs, number of gates, constant inputs and logical calculations are the parameters considered for comparison of ALU. The quantum cost and other parameters calculation for individual units (Arithmetic, Logic unit) are shown in Table 8. In the proposed ALU, the majority of the functional units are derived from KMD Gate1 and KMD Gate3 reversible gates (Inverters and Multiplexers), hence the quantum cost and number of gates are reduced.

Table 9 Percentage of improvement in proposed ALU. Parameter

Quantum cost Constant input No. of gates used

Improvement w.r.t. RM [11]

Improvement w.r.t. RUG [12]

Approach 1

Approach 2

Approach 1

Approach 2

63% 40% 21%

69% 30% 21%

40% 0% 21%

49% – 21%

From the above Tables 8 and 9, the quantum cost of the proposed ALU system is tremendously reduced up to 99; which is approximately 69% better compared to the existing methodology. Also, the number of gates needed to design the ALU is also less compared to [11,12], which is 21% of improvement. More functionalities could be obtained from the KMD gates by

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Fig. 5. Proposed reversible ALU architecture (Approach 2). Table 10 Performance measure comparison of proposed and existing N-bit ALU. Architecture

Arithmetic

Existing ALU architecture

Proposed ALU architecture

Method

RM [11]

RUG [12]

Logical RM [11]

RUG [12]

RM [11]

RUG [12]

Approach 1

Approach 2

Quantum cost Constant input Garbage output No. of. gates Used Logical calculation

140n 2n 6n

67n 0n 3n

140n 2n 7n

94n 1n 6n

320n 10n 15n

197n 6n 11n

118n 7n 21n

99n 8n 22n

4 2α +8β +3γ

3 3α +β

α +9β +4γ

4

14 8α +20β +9γ

14 9α +12β +11γ

11 12α +14β +6γ

11 12α +14β +6γ

4

α +6β +6γ

in Fig. 6. This n-bit structure can be utilized for big data analysis [27] in cloud based computing environment [28] with high performance.

6. Conclusion

Fig. 6. Comparison of ALU in graph.

changing the constant inputs; which increases the garbage output of the system; that is the reason behind more number of garbage outputs in the proposed method than the available methods. The n-bit ALU, whose performance measures are available in Table 10 and the graphical representation of comparison, is shown

Arithmetic Logic Unit is a heart of the processor for data manipulation. In this paper, a novel arithmetic logic unit is proposed, which is performing both kind of operations on the single structure. This ALU is producing 10 arithmetic and 8 logical operations on the input operands for the different control signals. The proposed ALU is built with KMD, Toffoli and Fredkin gates in two different approaches. These gates are fault-tolerant in nature; thus the proposed ALU structure also fault-tolerant. In addition, the capability of the KMD gates are also validated using the 13 standard Boolean function realizations. The functional simulation performed in Quantum Cellular Automata. Quantum circuit for the ALU also obtained. The simulation results confirm that the proposed ALU performs better in terms of Quantum cost, Constant input and Number of gates by 69%, 40%, and 21% respectively. The comparison is extended for logical calculation (12α +14β +6γ ) also; which is better than the existing (8α +20β +9γ ) design. It is worth noting that, the proposed ALU design requires less quantum cost, constant inputs, and number of gates. Future extension of work will be in

Kamaraj. A and Marichamy. P / Microprocessors and Microsystems 69 (2019) 16–23

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[21] Matthew Arthur Morrison, Design of a reversible ALU based on novel reversible logic structures, 2012. [22] Z. Guan, W. Li, W. Ding, Y. Hang, L. Ni, An Arithmetic logic unit design based on reversible logic gates, in: IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim), Victoria, BC, 2011, pp. 925– 931. [23] Y. Syamala, A.V.N. Tilak, Reversible arithmetic logic unit, in: Third International Conference on Electronics ComputerTechnology (ICECT), 5, 2011, pp. 207–211. [24] https://ceit.aut.ac.ir/QDA/RCV. [25] A. Kamaraj, P. Marichamy, Design of fault-tolerant reversible floating point division, journal of microelectronics, Electron. Components Mater. 48 (3) (2018) 161–171. [26] Armin Naghibzadeh, Monireh Houshmand, Design and simulation of a reversible ALU by using QCA cells with the aim of improving evaluation parameters, J. Comput. Electron. 16 (3) (2017) 883–895. [27] R. Joseph Manoj, M.D. Anto Praveena, K. Vijayakumar, An ACO–ANN based feature selection algorithm for big data, Cluster Comput. (2018) 1–8. https: //doi.org/10.1007/s10586- 018- 2550- z. [28] K. Vijayakumar, C. Arun, Automated risk identification using NLP in cloud based development environments, J. Ambient Intell. Hum. Comput. (2017) 3– 15 DOI, doi:10.1007/s12652- 017- 0503- 7. Kamaraj. A received his B.E. degree in Electronics and Communication Engineering from Bharathiar University, Coimbatore, Tamil Nadu, India in 2003. He completed his Post Graduation from Anna Universiy, Chennai in the field of VLSI Design in 2006. Currently, he is an Assistant Professor (Sr.G) in the Department of Electronics and Communication Engineering, Mepco Schlenk Engineering College, Sivakasi, India. He is pursuing his Ph.D. at Anna University, Chennai. His research interests include Digital circuits and logic design, Reversible logic & synthesis and advanced computing techniques. During his 13 years of a teaching career, He has published 13 papers in International Journals and 23 papers in National & International Conferences. He is a Life Member of IETE and ISTE. Marichamy. P has obtained B.E. degree from PSG College of Technology, Coimbatore, M.E., degree from CEG, Anna University, Chennai, in 1993 and Ph.D, from Indian Institute of Technology, Kharagpur, India, in 2002. He has more than 30 years of service in teaching. He has worked in National Engineering College, Kovilpatti, India, Nizwa College of Technology, Sultanate of Oman. Currently, he is working as Dean in P.S.R. Engineering College, Sivakasi, Tamilnadu, India. He has published more than 30 papers in various International Journals. His areas of interest include cellular mobile communication and green networks. He is a Life Member of ISTE.