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Designing organic and inorganic ambipolar thin-film transistors and inverters: Theory and experiment
Organic Electronics 13 (2012) 2816–2824
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Designing organic and inorganic ambipolar thin-film transistors and inverters: Theory and experiment Anita Risteska a, Kah-Yoong Chan a,b, Thomas D. Anthopoulos c, Aad Gordijn b, Helmut Stiebig b,1, Masakazu Nakamura d, Dietmar Knipp a,⇑ a Research Center for Functional Materials and Nanomolecular Science, Electronic Devices and Nanophotonics Laboratory, Jacobs University Bremen, 28759 Bremen, Germany b Research Center Jülich, Institute of Energy Research-Photovoltaics, 52425 Jülich, Germany c Department of Physics and Centre for Plastic Electronics, Imperial College London, London SW7 2AZ, United Kingdom d Graduate School of Materials Science, Nara Institute of Science and Technology, Ikoma, Nara 630-0192, Japan
a r t i c l e
i n f o
Article history: Received 23 June 2012 Received in revised form 20 August 2012 Accepted 20 August 2012 Available online 8 September 2012 Keywords: Ambipolar transistors Ambipolar inverters Complementary metal-oxide semiconductor inverters Analytical model Static noise margin
a b s t r a c t The design and operation of ambipolar transistors and inverters were studied. In order to gain insights in the operation of ambipolar inverters an analytical model was developed which describes the electrical behavior of ambipolar transistors and inverters. The model was compared to experimentally realized inorganic and organic ambipolar thin-film transistors and inverters. Furthermore, the influence of the transistor parameters on the voltage transfer characteristics and the static noise margin are discussed. The model provides a general description which is applicable to a variety of ambipolar transistor technologies based on different material systems. Ó 2012 Elsevier B.V. All rights reserved.
1. Introduction Thin-film transistors (TFTs) are key element for largearea display applications [1,2]. To date, TFTs based on amorphous silicon (a-Si:H), poly silicon (poly-Si) and organics are commonly used as pixel switches or pixel circuits for display backplanes [3,4]. However, the realization of more complex digital driver circuitry based on a-Si:H or poly-Si is not possible. The realization of complementary thin-film logic on glass is limited by a-Si:H p-type transistors which exhibit insufficient charge carrier mobility [5], or in the case of poly-Si the realization of complementary metal–oxide–semiconductor (CMOS) based circuitry is too expensive [6].
⇑ Corresponding author. 1
E-mail address: [email protected] (D. Knipp). Present address: Malibu GmbH and Co.KG, 33609 Bielefeld, Germany.
1566-1199/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.orgel.2012.08.038
In recent years, novel TFTs technologies based on a variety of materials have been developed. The materials range from organic semiconductors, to microcrystalline silicon, carbon nanotubes and graphene [7–10]. All these materials exhibit ambipolar charge transport. Hence several authors have proposed ambipolar circuitry as alternative to CMOS technology [7,8]. The realization of ambipolar logic circuitry is simple in comparison to the fabrication of logical circuits in CMOS technology. Fewer layers are being deposited and less patterning steps are needed to realize simple digital circuitry. However, due to the ambipolar nature of the charge transport, the transistors cannot be completely switched off and thus the static noise margin is reduced and the power consumption is increased. In this manuscript, the influence of ambipolar transistor properties on the static noise margin will be discussed for organic and inorganic inverters. An introduction to ambipolar transistors is given in Section 2. An analytical model for describing the voltage
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Fig. 1. (a) Electron affinity of an ambipolar material and the drain and source electrodes and (a) schematic cross-section of a top-gate staggered ambipolar TFT. (c) Circuit of an ambipolar inverter and (d) its schematic cross-section.
transfer characteristics (VTCs) of CMOS and ambipolar inverters will be presented in Section 3. Additionally, using the models, the consequences of varying different parameters on the device performance will be analyzed. The mathematical models are very useful for understanding the device operation principles and for designing inverters with high static noise margin. Experimental results for inorganic and organic ambipolar TFTs and inverters are presented in Section 4. In Section 4.1, the experimental results of microcrystalline (lc-Si:H) thin-film CMOS inverters are presented. The CMOS inverters are used as a reference for the further discussion of lc-Si:H ambipolar TFTs, which are presented in Section 4.2. Polymer based organic transistors and ambipolar inverters are presented in Section 4.3. Comparisons of the experimental results with the presented model of ambipolar inverters are discussed in Section 5. Furthermore, strategies to optimize the operation of ambipolar inverters are described. 2. Ambipolar thin-film transistors’ model A schematic cross-section of an ambipolar TFT is shown in Fig. 1b. The current/voltage characteristics of an ambipolar field-effect transistor can be described by a simple charge-sheet model. Such model was proposed for the first time for unipolar transistors by Shockley [11] and later extended by Brews and Van de Wiele [12,13]. Schmechel et al. were the first to use a charge-sheet model to describe the operation of ambipolar field-effect transistors [14]. In this simple model the field-effect transistor is treated as a plate capacitor. All charges are assumed to be immediately at the interface of the dielectric, so that the thickness of the accumulation layer is zero. This assumption implies that no band bending exists across the charge-sheet, which results in an error of this model. Depending on the biasing voltages, we can distinguish an n-type and a p-type ambipolar transistors. The different modes of operation of the ambipolar thin-film
transistor are shown in Fig. 2. An n-type ambipolar transistor exhibits electron transport for small positive drain and positive gate voltages and electron and hole transport for high positive drain voltages and positive gate voltages. A p-type ambipolar transistor exhibits only hole transport for small negative drain voltages and negative gate voltages and electron and hole transport for large negative drain voltages and negative gate voltages. For VD < (VG VTn), the drain current, ID, of the ambipolar transistor operates in the linear region and the charge transport is determined only by electrons, so that:
I D ¼ ln C G
W VD V G V Tn VD L 2
ð1Þ
where L is the channel length, W is the channel width, ln is the electron charge carrier mobility, CG is the normalized gate capacitance, and VG, VD and VTn are the gate, the drain and the threshold (describing the electron transport) voltages, respectively. For (VG VTn) 6 VD 6 (VG VTp), the transistor saturates and the drain current is given by:
I D ¼ ln C G
W ðV G V Tn Þ2 2L
ð2Þ
The voltage, VTp, refers to the threshold voltage describing the holes transport in the channel. For VD P (VG VTp) and (VG VTn) > 0, the transistor exhibits the behavior of an ambipolar TFT. Holes and electrons contribute to the current flow as follows:
W ID ¼ C G 2L h i ln ðV G V Tn Þ2 þ lp ðV D ðV G V TP ÞÞ2
ð3Þ
where lp is the hole charge carrier mobility. Eq. (3) describes the transistor’s behavior for high drain voltages. For VD P (VG VTp) and (VG VTn) < 0, the complete current flow is determined by holes resulting in the following expression:
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Fig. 2. Different operation modes of an ambipolar TFT depending on the applied bias voltages.
ID ¼ C G
W 2L
h
lp ðV D ðV G V TP ÞÞ2
i
ð4Þ
The four operation regions of an n-type ambipolar transistor can be divided in a linear region (electrons, Eq. (1)), a saturation region (electrons, Eq. (2)), an ambipolar region (electrons and holes, Eq. (3)) and a saturation region (holes, Eq. (4)). 3. Modeling of ambipolar Inverters The circuit of an ambipolar inverter along with its schematic cross-section is shown in Fig. 1c and d. The inverter’s circuit consists of p-type ambipolar (larger negative drain and negative gate voltages) load TFT, while the drive transistor is an n-type ambipolar (larger positive drain and positive gate voltages) TFT. The input of the inverter is connected to the gate of the load and the drive transistor. The source of the load transistor is connected to the supply voltage, VDD, while the source of the drive transistor is connected to ground. The gate voltage of the load TFT is given by VG = VDD Vin and the drain voltage is VD = VDD Vout, while for the drive TFT VG = Vin and VD = Vout. In order to
derive analytical expressions for the voltage transfer characteristics (VTC) of an ambipolar inverter, the characteristics have to be divided into five regions. The five regions are summarized for both, CMOS and ambipolar, inverters in Table 1. Sequencing from region A to region E is carried out by starting with the input voltage, Vin, at 0 V and increasing its value until VDD is reached. In region A, both, the n- and the p-type, ambipolar transistors behave as unipolar TFTs, i.e. only one charge carrier type determines the current. The n-type TFT is on, operating in the saturation region and only holes contribute to the current flow. Conversely, the p-type transistor is also on and operating in linear mode with only holes flowing through the channel. Equating the current of both transistors in the respective modes of operation and solving for the output voltage, Vout, will lead to the following equations for the output voltage:
V ambi out ¼ ðV in þ jV TP jÞ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kp þ ðV DD ðV in þ jV TP jÞÞ2 p P p KP þ KN
ð5Þ
Table 1 Different operating regions of the CMOS and the ambipolar inverters, and their corresponding charge carrier types contributing to the current flow. Operating region
A (0 < Vin < VTN) B (VTN < Vin < VDD/2) C (Vin = VDD/2) D (VDD/2 < Vin < VDD |VTP|) E (VDD |VTP|
CMOS
Ambipolar
n-Type
p-Type
Current flow
n-Type
p-Type
Current flow
Off Satur. Satur. Linear Linear
Linear Linear Satur. Satur. Off
/holes Electr./holes Electr./holes Electr./holes Electr./
Satur. Satur. Satur. Linear Linear
Linear Linear Satur. Satur. Satur.
Holes/holes Holes + electr./holes Electr.-/holes Electr./holes + electr. Electr./electr.
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lN C W
lp C W
where K PN ¼ p LGN N and K Pp ¼ P LGP P , with lNp , WN and LN being the hole charge carrier mobility, the channel width and the channel length of the n-type ambipolar TFT, correspondingly, while lPp , WP and LP are the hole charge carrier mobility, the channel width and the channel length of the p-type ambipolar TFT, respectively. For a CMOS inverter operating in region A, the equation for the output voltage can be obtained by setting lNp to zero (NMOS TFT conducts p only electrons – unipolar device), i.e. kN to zero, in Eq. (5) CMOS which will lead to V out ¼ V DD . Next is region B, where the n-type ambipolar transistor operates in the saturation regime exhibiting an ambipolar behavior and both electrons and holes contribute to the current flow, while the p-type transistor still has a unipolar behavior, i.e. only holes flow through the channel and it operates in the linear regime. Since the current flowing through both TFTs should be the same, using the current equations, with the VD and VG written in terms of Vout and Vin as described before, and equating the respective currents of the transistors, the equation for the output voltage is obtained: V ambi out ¼ ðV in þ jV TP jÞ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kp Kn þ ðV DD ðV in þ jV TP jÞÞ2 p P p ðV in V TN Þ2 p N p KP þ KN KP þ KN ð6Þ N C W N n G
l
where K nN ¼ with lNn , WN and LN being the elecLN tron charge carrier mobility, the channel width and the channel length of the n-type TFT, respectively. Similarly, the equation for a CMOS inverter operating in region B p can be obtained by setting again lNp to zero, i.e. kN ¼ 0, in Eq. (6) due to the unipolarity of the employed TFTs. Region C involves the nearly vertical segment of the VTC, where both of the transistors operate in the saturation regime. By equating the currents IDN (sat) = IDP (sat) again, the following equation for the ambipolar inverter is attained:
V ambi in
qffiffiffiffiffiffi qffiffiffiffiffiffi K pP ðV DD jV TP jÞ þ K nN V TN ¼ qffiffiffiffiffiffi qffiffiffiffiffiffi K nN þ K pP
ð7Þ
As can be seen, Vout is not present in Eq. (7) since the gain is, ideally, infinite due to modeling limitations of the current equations. On the Vin axis this region is a single point, however on the Vout axis the C region is either a single point (for VTP = VTN = 0 V) or a line ranging between VDD/2VTP and VDD/2VTN (for nonzero threshold voltages). Further, in this region of the VTC falls the voltage VM at which Vout = Vin. Eq. (7) can be used without modification for CMOS inverters operating in this region, since no ambipolarity is involved in the expression describing the output voltage. In region D, the n-type ambipolar TFT still exhibits a unipolar behavior (only electrons contribute to the current flow) and operates in the linear region, while the p-type TFT has an ambipolar behavior and operates in the saturation regime. Yet again, equating the currents of the TFTs and solving for Vout gives the expression for the output voltage in this region:
V ambi out ¼ ðV in V TN Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kn Kp ðV in V TN Þ2 n N n ðV DD ðV in þ jV TP jÞÞ2 n P n KN þ KP KN þ KP
ð8Þ
Again, the equation a CMOS inverter operating in region n D can be obtained by substituting kP ¼ 0 in Eq. (8). In the last region, E, the ambipolar TFTs have a unipolar behavior. The n-type TFT has only electrons flowing and operates in the linear regime, while the p-type TFT has also only electrons contributing to the current and operates in the saturation regime. If the currents are equated and the equation is solved for Vout, the following expression for the output voltage is obtained:
V ambi out ¼ ðV in V TN Þ
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kn ðV in V TN Þ2 n N n KN þ KP
ð9Þ
For a CMOS inverter, region E is where one of the TFTs is off (the PMOS is switched off, since VG = VDD Vin < |VTP|, i.e. Vin > VDD |VTP|), so there is nearly no current flowing through the TFTs, thus the output voltage is 0 V, which n could be, as before, obtained from Eq. (9) by setting kP ¼ 0. Using the developed models, the VTC of both, CMOS and ambipolar inverters were simulated for different charge carrier mobility ratios and threshold voltages, as shown in Fig. 3. The parameters used for each simulation are given in the respective figure. The VTCs were simulated for symmetrical n- and p-type transistors. The VTC curves of a CMOS inverter, shown in Fig. 3a, are plotted for different charge carrier mobility ratios, and demonstrate the effect of the charge transport on the inverter characteristics. For balanced electron and hole transport properties of the NMOS and the PMOS transistors, respectively, the switching voltage is half the supply voltage, VDD. For unbalanced charge carrier transport properties, the switching voltage shifts to higher Vin when the hole mobility exceeds the electron mobility and vice versa to lower Vin for a superior electron mobility. The effect of the charge carrier mobility ratio on the ambipolar inverters’ VTC is similar to that of CMOS inverters, as illustrated in Fig. 3c – depending on the ratio of the mobilities, the switching voltage is shifted to higher or lower Vin. The effect of increasing the threshold voltage (both VTN and |VTP| are equally and symmetrically increased) can be observed in Fig. 3b (CMOS inverters) and d (ambipolar inverters). Increasing the threshold voltages affects the shape of the VTC characteristic. The shape of the VTC has an effect on the noise margin of the inverters, which is of crucial importance when building more advanced circuits [15]. In order to verify the correctness of the derived model, the VTCs of both, CMOS and ambipolar, inverters were also experimentally measured. 4. Experimental results 4.1. Microcrystalline silicon thin-film transistors and CMOS inverters As a first step towards the realization of silicon thin-film CMOS inverters, p- and n-channel unipolar
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Fig. 3. Simulated VTC of (a and b) a CMOS and (c and d) an ambipolar inverter for different (a and c) charge carrier mobility ratios (VDD = 5 V; VTN = VTH = 0 V; lNn =lPp ¼ lPn =lNp ¼ 0:1; 1; 10) and (b and d) threshold voltages (VDD = 5 V; lNn =lPp ¼ lPn =lNp ¼ 1; VTN = VTH = 0, 1, 2 V). The VTCs were simulated for LN = LP = 2 lm and WN = WP = 1000 lm.
microcrystalline silicon (lc-Si:H) TFTs were fabricated. The drain and the source metal electrodes of the lc-Si:H TFTs were prepared by electron beam evaporation of chromium (Cr) with a thickness of 30 nm on glass substrates. The highly doped n/p-type lc-Si:H layer with thickness of 25 nm was prepared by plasma-enhanced chemical vapor deposition (PECVD) at 180 °C. Next, the channel material with thickness of 100 nm was deposited by a PECVD process at 160 °C [16]. The gate dielectric was realized by silicon oxide (SiO2) with film thickness of 300 nm also by PECVD process at 150 °C. And finally, the gate electrode of the transistors was formed by thermally evaporated aluminum. The measured unipolar lc-Si:H TFTs exhibited electron (n-type unipolar TFT) and hole (p-type unipolar TFT) charge carrier mobilities exceeding 50 and 12 cm2/V s, respectively. The measured transfer characteristics of an n-type unipolar TFT is shown in Fig. 4a. The extracted subthreshold slopes of the TFTs are larger than 0.75 V/decade. To validate the correctness of the developed model, the fabricated p- and n-channel lc-Si:H TFTs were used to realize CMOS inverters. Fig. 4b shows the voltage transfer characteristics of a CMOS inverter using an n-channel TFT (L = 20 lm and W = 200 lm) and a p-channel TFT (L = 20 lm and W = 1000 lm) for supply voltages of 5, 6, and
7 V. The increased channel width of the PMOS TFT compensates its lower hole charge carrier mobility. The experimentally extracted voltage gain, which is defined to be @V out =@V in , ranges from 15 to 22 and a clear and abrupt transition from high- to low-state is observed. The measured voltage gain is high in comparison to other values published in literature [17]. 4.2. Microcrystalline silicon ambipolar thin-film transistors and inverters In the case of the ambipolar lc-Si:H TFTs, the deposition processes and temperatures, the materials’ type, and the thicknesses of all the respective layers are same as for the unipolar lc-Si:H TFTs, except that now the highly doped n- or p-layers were not inserted between the metal contacts and the microcrystalline silicon channel layer, as the doped layer-free lc-Si:H ambipolar transistors have been demonstrated [18]. The fabricated ambipolar lc-Si:H TFTs exhibit charge carrier mobilities of 40 and 10 cm2V s. The transfer characteristics of the n-type ambipolar transistor are shown in Fig. 5a. The transistors exhibit subthreshold slope of around 0.5 V/decade. The lc-Si:H ambipolar TFTs were used to realize ambipolar inverters. The experimentally measured VTC of the
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Fig. 4. (a) Transfer characteristics of an n-type unipolar lc-Si:H TFT (L = 10 lm; W/L = 100). The transfer curves were measured for VD = 0.5, 1, 1.5 V. (b) Experimentally obtained VTCs of a CMOS inverter. The VTCs were measured for VDD = 5, 6, 7 V.
Fig. 5. (a) Transfer characteristics of an n-type ambipolar lc-Si:H TFT (L = 20 lm; W/L = 50). The transfer curves were measured for VD = 0.1, 1, 3 V. (b) Experimentally obtained VTCs of a microcrystalline silicon ambipolar inverter. The VTCs were measured for VDD = 3, 4, 5, 6 V.
lc-Si:H ambipolar inverter are shown in Fig. 5b. The ambipolar inverter was realized using a n-channel ambipolar TFT with a channel length (L) of 20 lm and a channel width (W) of 200 lm, and a p-channel ambipolar TFT with a channel length of 20 lm and a channel width of 1000 lm. The increased channel width of the p-channel transistor compensates for the reduced charge charier mobility of the p-channel transistor. The inverters exhibit voltage gains comparable to that of CMOS inverters. The experimentally extracted voltage gain is equal 5–10. On the other hand, the output voltage of the ambipolar lc-Si:H inverter in the logical low-state increases with increasing input voltage, which can be explained by the high off-current of the constituent p-channel ambipolar lc-Si:H transistor at high VD [19]. 4.3. Organic ambipolar thin-film transistors and inverters Further, another type of ambipolar organic TFTs were prepared with nickel dithiolene as the channel material. The transistors were made using heavily doped p-type Si
wafers as the back gate electrode with a 200 nm thermally oxidized SiO2 layer as the gate dielectric. Using conventional photolithography, gold source and drain electrodes were defined with channel length and width in the ranges of 1.5–40 lm and 1–20 mm, respectively. A 10 nm layer of titanium was used as an adhesion layer for the gold on the SiO2. The SiO2 layer was treated with the primer hexamethyldisilazane prior to semiconductor deposition. Thin films of nickel dithiolene were spin-coated from a 10 mg mL1 solution using chloroform. Spin-coating was performed at 500 rpm for 60 s under ambient conditions. The transfer characteristics of the prepared ambipolar nickel dithiolene TFTs are shown in Fig. 6a. The electron and hole mobilities (calculated in saturation), measured in as-prepared devices under ambient light and air, are on the order of 104 cm2/V s. This value is typical, with the highest measured value being on the order of 103 cm2/V s. We note, however, that in the linear regime holes are more mobile than electrons by approximately a factor of two, with typical electron mobilities in the range of 2 104 to 8 104 cm2/V s. The p-type and n-type
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Fig. 6. (a) Transfer characteristics for an n-type and a p-type amipolar nickel dithiolene TFT, measured for VD = 5, 15 V and VD = 5, 15 V, respectively. (b) Experimentally obtained VTC of a polymer ambipolar inverter. The VTC were measured for VDD = 20 V and the extracted values for the static noise margin were SNML = 3.92 V and SNMH = 4.68 V.
ambipolar transistors exhibit threshold voltages of 10 V and 5 V, respectively. The fabricated nickel dithiolene ambipolar TFTs were used to realize CMOS-like inverters and the measured VTCs are shown in Fig. 6b. The inverter was realized by p-type ambipolar nickel dithiolene TFT with channel length and width of 5 and 100 lm, respectively, and n-type ambipolar nickel dithiolene TFT with channel length and width of 5 and 1000 lm, correspondingly. The inverter exhibit a maximum voltage gain of around 6. 5. Discussion Comparing the measured and the simulated VTC shows that the model correctly describes the characteristics of the CMOS and the ambipolar inverters. Furthermore, the derived model for the CMOS and the ambipolar inverter is in a good agreement with experimental results published in literature [19–22]. The slight difference between the simulated and measured VTCs of both, CMOS and ambipolar, inverters is due to the asymmetry of the prepared transistors used in the experiments. The transistors are described by ideal transistor equations. The influence of non-ideal effects, like contact or output resistances are not considered. Contact effects are responsible for the formation of an S-shape in the linear region of operation. In order to account for the drain voltage dependent modulation of the channel length in the saturation region, often an output resistance is considered [15]. In the case of a CMOS inverter, the contact and the output resistances have an effect on the VTC in region B, C and D. In the case of an ambipolar inverter, the contact and the output resistances affect all five regions (A–D) of the voltage transfer curve. As a consequence, the noise margin and the voltage gain of the inverters are reduced. Furthermore, the influence of the subthreshold characteristics of the transistors on the VTC is not considered. The subthreshold characteristics of organic transistors are very often affected by unintentional doping or environmental effects, which again will lead to a drop of the static noise margin [23].
In the next step, the static noise margin (SNM) [24,25] was determined for the measured and simulated inverters. Several approaches have been suggested in literature to determine the SNM. In our study, we have selected an approach in which the SNM is defined as the largest possible rectangle that is fitted between the measured and its imaged VTC. The sides of the rectangle define the high and the low SNM. For a perfectly symmetric VTC, the fitted shape becomes a square, so that the high and the low SNM margin are identical. Nevertheless, in most of the cases the inverter characteristics are not symmetric, so that we obtain different values for the high and the low noise margin. Other approaches define the SNM as a square that is fitted between the measured and the imaged VTC, which seem better suited to analyze the behavior of inverters since only one value for the SNM is acquired. However, numerical methods are needed to maximize the area of the fitted square. Therefore, no analytical expression of the SNM can be derived. The approach employed in this study uses the -1 slope definition of the VTC to calculate the low and the high SNM. This allows for deriving an analytical expression for the SNM. We will accept the consequence of getting a low and high SNM at the expense of gaining a better insight and a more intuitive understanding of the inverter operation. Further details on the definition of the SNM and its extraction from the VTC can be found elsewhere in literature [24–26]. Fig. 7a and b shows the calculated and the measured noise margin as a function of the supply voltage, for both, CMOS and ambipolar inverters, respectively. The SNM increases with increasing the supply voltage, irrespective of the threshold voltage. Additionally, there is a good agreement between the simulated and the experimentally measured SNM. The trend of the experimentally measured SNM follows the trend of the simulated SNM, for both, CMOS and ambipolar inverters. The difference between the SNML and SNMH arises from the asymmetry of the VTC, which is the consequence of the difference between the threshold voltage and the mobility of the n- and p-type transistors. For identical device parameters, the CMOS inverter exhibits a high SNM, which increases with the threshold
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Fig. 7. Comparison of the static noise margin (SNM) of CMOS and ambipolar inverters with the experimental data. The influence of VDD on the SNM of (a) CMOS and (b) ambipolar inverters for different VT. All the simulation parameters of the constituent TFTs are same for both inverters ðlNn =lPp ¼ lPn =lNp ¼ 1Þ.
voltage and the supply voltage. For CMOS inverters, ideally, the maximum noise margin can reach half the supply voltage, if the threshold voltage reaches half VDD. The SNM of the CMOS inverter with identical threshold voltages and mobilitities can be calculated by:
SNMCMOS ¼
V DD V TH þ 4 2
for 0 < V Th <
V DD 2
ð10Þ
The static noise margin varies between VDD/4 and VDD/2. In order to maximize the SNM, the threshold voltage should be half the supply voltage. If VTH is larger than the half the supply voltage, the transistors operate in the subthreshold region. Such mode of operation is often used in microelectronics. However, the presented model does not take the subthreshold region into account. The SNM of the ambipolar inverter with symmetric threshold voltages and mobilities is given by:
SNMambi ¼
V DD V TH þ3 8 4
for 0 < V Th <
V DD 4
ð11aÞ
The static noise margin varies between VDD/8 and VDD/4. If the equation would be valid for threshold voltages up to VDD/2, the SNM would reach VDD/2. Therefore, the SNM of an ambipolar inverter would be equal to the noise margin of a CMOS inverter. However, this is not the case. The operation of the ambipolar inverter has been divided in two regions. The SNM of the ambipolar inverter is limited by the high off-current of the transistor that is in the off-state. For threshold voltages larger than VDD/4, the static noise margin can be described by:
SNMambi ¼
V DD V TH þ 4 4
for
V DD V DD < V TH < 4 2
ð11bÞ
For threshold voltages equal to half the supply voltage the static noise margin reaches a maximum of 3 VDD/8. In the following the SNMs of the CMOS and the ambipolar inverters are compared. The maximum static noise margin of a CMOS inverter for a threshold voltage of 0 V is equal to VDD/4, whereas the maximum static noise margin for an ambipolar inverter is equal to VDD/8. Therefore, the SNM of an ambipolar inverter reaches only 50% of the SNM of a CMOS inverter. With
increasing threshold voltage the difference of the noise margin between the CMOS and the ambipolar inverter becomes smaller. Increasing the VTH of the ambipolar transistors up to VDD/4 leads to a distinct increase of the static noise margin. For a threshold voltage of VDD/4, the SNM of the CMOS inverter reaches 3 VDD/8, while the ambipolar inverter reaches 5 VDD/16. Therefore, the SNM of the ambipolar inverter reaches 5/6 or 83.3% of the SNM of the CMOS inverter. For threshold voltages of VDD/4 the difference between the two types of inverters is minimized. For maximum threshold voltages of VDD/2, the SNM of the CMOS inverter reaches VDD/2, while the SNM of the ambipolar inverter reaches 3 VDD/8. As a consequence the ambipolar inverter reaches only 75% of the SNM of the CMOS inverter. In order to maximize the static noise margin and minimize the power consumption, the threshold voltage of an inverter should be equal to VDD/2. Under such conditions the SNM of the ambipolar inverter reaches 75% of the performance of a CMOS inverter. Though, the application of ambipolar inverters is limited by the noise margin, as discussed above, they are still an interesting addition to the existing CMOS inverter technology, since they provide a simple route in realization of large area integrated circuits at low cost using simple fabrication processes. Nevertheless, the power consumption of ambipolar inverters is significantly higher than the power consumption of CMOS inverters. As a solution to this problem interesting novel device structures using transistors with double gates have been suggested. One of the two gates (programmable gate) of the transistor is used to control the injection of charges in the semiconductor. By using the programmable gate the high off-current of the ambipolar transistors can be suppressed. Such device have been demonstrated for carbon nanotube FETs (CNFETs) [27– 30] and Si FETs [31]. However, further investigations are needed to study transistors with a double gate geometry.
6. Summary Simple analytical models were presented, that allow for describing the voltage transfer characteristics of both,
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CMOS and ambipolar inverters. The presented models provide insights into the electrical characteristics of both inverter technologies. They were used to investigate the effect of different transistor parameters on the static noise margin. Further, the correctness of the models was validated with experimental measurements. A good agreement between the models and the experimental data was observed. A comparison of the model for CMOS and ambipolar inverters shows that the SNM of ambipolar inverters can reach 75% of the CMOS inverter’s static noise margin. Acknowledgement The authors like to acknowledge S. Bunte and Y. Mohr (IBN-PT) for preparation of the PECVD SiO2, M. Hülsbeck, J. Kirchhoff, T. Melle, S. Michel, and R. Schmitz (all IEFPV) for technical assistances in preparing the lc-Si:H TFTs and E. Bunte, R. Carius, D. Hrunski, and V. Smirnov (all IEFPV) for helpful discussions. Furthermore, the authors would like to thank M. Marinkovic, and E. Hashem (all JUB) for electrical measurements and V. Wagner (JUB) for discussion. References [1] H. Klauk, Organic Electronics: Materials, Manufacturing, and Applications, Wiley, 2006. [2] W.S. Wong, A. Salleo, Flexible Electronics: Materials and Applications, Springer, Heidelberg, 2009. [3] R.A. Street, Thin-film transistors, Adv. Mater. 21 (2009) 2007–2022. [4] G. Gelinck, P. Heremans, K. Nomoto, T.D. Anthopoulos, Organic transistors in optical displays and microelectronic applications, Adv. Mater. 22 (2010) 3778–3798. [5] B. Stannowski, R.E.I. Schropp, R.B. Wehrspohn, M.J. Powell, Amorphous-silicon thin-film transistors deposited by VHF-PECVD and hot-wire CVD, J. Non-Cryst. Solids 299–302 (2002) 1340–1344. [6] S.D. Brotherton, Polycrystalline silicon thin film transistors, Semicond. Sci. Technol. 10 (1995) 721–738. [7] K.-Y. Chan, J. Kirchhoff, A. Gordijn, H. Stiebig, D. Knipp, Ambipolar microcrystalline silicon transistors and inverters, Solid-State Electron. 53 (2009) 635. [8] E.J. Meijer, D.M. de Leeuw, S. Setayesh, E. Van Veenendaal, B.-H. Huisman, P.W.M. Blom, J.C. Hummelen, U. Scherf, T.M. Klapwijk, Solution-processed ambipolar organic field-effect transistors and inverters, Nat. Mater. 2 (2003) p. 678. [9] Y. Zhou, A. Gaur, S.-H. Hur, C. Kocabas, M.A. Meitl, M. Shim, J.A. Rogers, p-Channel, n-Channel thin-film trasistors and p-n diodes based on single wall carbon nanotube networks, Nano Lett. 4 (2004) 2031–2035. [10] F. Xia, D.B. Farmer, Y.-M. Lin, P. Avouris, Graphene field-effect transistors with high on/off current ratio and large transport band gap at room temperature, Nano Lett. 10 (2010) 715–718.
[11] W. Shockley, A unipolar ‘‘Field-Effect’’ transistor, Proc. IRE 40 (1952) 1365. [12] J.R. Brews, A charge-sheet model of the MOSFET, Solid-State Electron. 21 (1978) 345. [13] F. Van de Wiele, A long-channel MOSFET model, Solid-State Electron. 22 (1979) 991. [14] R. Schmechel, M. Ahles, H. Seggern, A pentacene ambipolar tranistor: experiment and theory, J. Appl. Phys. 98 (2005) 084511. [15] D. Bode, C. Rolin, S. Schols, M. Debucquoy, S. Steudel, G. Gelinck, J. Genoe, P. Heremans, Noise-margin analysis for organic thin-film complementary technology, IEEE Trans. Electron. Dev. 57 (2010) 201–208. [16] L. Guo, M. Kondo, M. Fukawa, K. Saitoh, A. Matsuda, High rate deposition of microcrystalline silicon using conventional plasmaenhanced chemical vapor deposition, Jpn. J. Appl. Phys. 37 (1998) L1116–L1118. [17] Y. Chen, S. Wagner, Inverter made of complementary p and n channel transistors using a single directly deposited microcrystalline silicon film, Appl. Phys. Lett 75 (1999) 1125–1127. [18] C.-H. Lee, A. Sazonov, A. Nathan, J. Robertson, Directly deposited nanocrystalline silicon thin-film transistors with ultra high mobilities, Appl. Phys. Lett. 89 (2006) 252101. [19] C.-H. Lee, A. Sazonov, M. R. E. Rad, G. R. Chaji, A. Nathan, Ambipolar thin-film transistors fabricated by PECVD nanocrystalline silicon, in: Mater. Res. Soc. Symp. Proc. 910, 2006 (0910 A22-05). [20] C. Melzer, H. von Seggern, Organic field-effect transistors for CMOS devices, Adv. Polym. Sci. 223 (2010) 213–257. [21] W. Chen, M. Wang, Y. Zhou, M. Wong, Degradation of static behaviour of poly-Si CMOS inverters under high frequency operation, in: 18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2011. [22] K. Nomura, T. Kamiya, H. Hosono, Ambipolar oxide thin-film transistors, Adv. Mater. 23 (2011) 3431–3434. [23] D. Knipp, J.E. Northrup, Electric field induced gap states in pentacene, Adv. Mater. 21 (2009) 2511–2515. [24] C.F. HiII, Noise margin and noise immunity of logic cicuits, Microelectron. 1 (1968) 16–21. [25] J.R. Hauser, Noise margin criteria for digital logic circuits, IEEE Trans. Educ. 36 (1993) 363–368. [26] D.A. Hodges, H.G. Jackson, R.A. Saleh, Analysis and Design of Digital Integrated Circuits: In Deep Submicron Technology, third ed., McGraw-Hill, Higher Education, Boston, 2003. [27] M. Pourfath, E. Ungersboeck, A. Gehring, B.H. Cheong, W. Park, H. Kosina, S. Sberherr, Improving the ambipolar behavior of schottky barrier carbon nanotube field effect transistors, in: Proceeding of the 34th European Solid-State Device Research conference, 2004, pp. 429–432. [28] M. Pourfath, E. Ungersboeck, A. Gehring, H. Kosina, S. Selberherr, Separated carrier injection control in carbon nanotube field-effect transistors, J. Appl. Phys. 97 (2005) 106103. [29] Y.-M. Lin, J. Appenzeller, P. Avouris, Ambipolar-to-unipolar conversion of carbon nanotube transistors by gate structure engineering, Nano Lett. 4 (2004) 947–950. [30] Y.-M. Lin, J. Appenzeller, J. Knoch, P. Avouris, High-performance carbon nanotube field-effect transistor with tunable polarities, IEEE Trans. Nanotechnol. 4 (2005) 481–489. [31] Haraziia, A. Vladimirescu, A. Amara, C. Anghel, An analysis on the ambipolar current in Si double-gate tunnel FETs, Solid-State Electron. 70 (2012) 67–72.
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Organic Electronics journal homepage: www.elsevier.com/locate/orgel
Designing organic and inorganic ambipolar thin-film transistors and inverters: Theory and experiment Anita Risteska a, Kah-Yoong Chan a,b, Thomas D. Anthopoulos c, Aad Gordijn b, Helmut Stiebig b,1, Masakazu Nakamura d, Dietmar Knipp a,⇑ a Research Center for Functional Materials and Nanomolecular Science, Electronic Devices and Nanophotonics Laboratory, Jacobs University Bremen, 28759 Bremen, Germany b Research Center Jülich, Institute of Energy Research-Photovoltaics, 52425 Jülich, Germany c Department of Physics and Centre for Plastic Electronics, Imperial College London, London SW7 2AZ, United Kingdom d Graduate School of Materials Science, Nara Institute of Science and Technology, Ikoma, Nara 630-0192, Japan
a r t i c l e
i n f o
Article history: Received 23 June 2012 Received in revised form 20 August 2012 Accepted 20 August 2012 Available online 8 September 2012 Keywords: Ambipolar transistors Ambipolar inverters Complementary metal-oxide semiconductor inverters Analytical model Static noise margin
a b s t r a c t The design and operation of ambipolar transistors and inverters were studied. In order to gain insights in the operation of ambipolar inverters an analytical model was developed which describes the electrical behavior of ambipolar transistors and inverters. The model was compared to experimentally realized inorganic and organic ambipolar thin-film transistors and inverters. Furthermore, the influence of the transistor parameters on the voltage transfer characteristics and the static noise margin are discussed. The model provides a general description which is applicable to a variety of ambipolar transistor technologies based on different material systems. Ó 2012 Elsevier B.V. All rights reserved.
1. Introduction Thin-film transistors (TFTs) are key element for largearea display applications [1,2]. To date, TFTs based on amorphous silicon (a-Si:H), poly silicon (poly-Si) and organics are commonly used as pixel switches or pixel circuits for display backplanes [3,4]. However, the realization of more complex digital driver circuitry based on a-Si:H or poly-Si is not possible. The realization of complementary thin-film logic on glass is limited by a-Si:H p-type transistors which exhibit insufficient charge carrier mobility [5], or in the case of poly-Si the realization of complementary metal–oxide–semiconductor (CMOS) based circuitry is too expensive [6].
⇑ Corresponding author. 1
E-mail address: [email protected] (D. Knipp). Present address: Malibu GmbH and Co.KG, 33609 Bielefeld, Germany.
1566-1199/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.orgel.2012.08.038
In recent years, novel TFTs technologies based on a variety of materials have been developed. The materials range from organic semiconductors, to microcrystalline silicon, carbon nanotubes and graphene [7–10]. All these materials exhibit ambipolar charge transport. Hence several authors have proposed ambipolar circuitry as alternative to CMOS technology [7,8]. The realization of ambipolar logic circuitry is simple in comparison to the fabrication of logical circuits in CMOS technology. Fewer layers are being deposited and less patterning steps are needed to realize simple digital circuitry. However, due to the ambipolar nature of the charge transport, the transistors cannot be completely switched off and thus the static noise margin is reduced and the power consumption is increased. In this manuscript, the influence of ambipolar transistor properties on the static noise margin will be discussed for organic and inorganic inverters. An introduction to ambipolar transistors is given in Section 2. An analytical model for describing the voltage
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Fig. 1. (a) Electron affinity of an ambipolar material and the drain and source electrodes and (a) schematic cross-section of a top-gate staggered ambipolar TFT. (c) Circuit of an ambipolar inverter and (d) its schematic cross-section.
transfer characteristics (VTCs) of CMOS and ambipolar inverters will be presented in Section 3. Additionally, using the models, the consequences of varying different parameters on the device performance will be analyzed. The mathematical models are very useful for understanding the device operation principles and for designing inverters with high static noise margin. Experimental results for inorganic and organic ambipolar TFTs and inverters are presented in Section 4. In Section 4.1, the experimental results of microcrystalline (lc-Si:H) thin-film CMOS inverters are presented. The CMOS inverters are used as a reference for the further discussion of lc-Si:H ambipolar TFTs, which are presented in Section 4.2. Polymer based organic transistors and ambipolar inverters are presented in Section 4.3. Comparisons of the experimental results with the presented model of ambipolar inverters are discussed in Section 5. Furthermore, strategies to optimize the operation of ambipolar inverters are described. 2. Ambipolar thin-film transistors’ model A schematic cross-section of an ambipolar TFT is shown in Fig. 1b. The current/voltage characteristics of an ambipolar field-effect transistor can be described by a simple charge-sheet model. Such model was proposed for the first time for unipolar transistors by Shockley [11] and later extended by Brews and Van de Wiele [12,13]. Schmechel et al. were the first to use a charge-sheet model to describe the operation of ambipolar field-effect transistors [14]. In this simple model the field-effect transistor is treated as a plate capacitor. All charges are assumed to be immediately at the interface of the dielectric, so that the thickness of the accumulation layer is zero. This assumption implies that no band bending exists across the charge-sheet, which results in an error of this model. Depending on the biasing voltages, we can distinguish an n-type and a p-type ambipolar transistors. The different modes of operation of the ambipolar thin-film
transistor are shown in Fig. 2. An n-type ambipolar transistor exhibits electron transport for small positive drain and positive gate voltages and electron and hole transport for high positive drain voltages and positive gate voltages. A p-type ambipolar transistor exhibits only hole transport for small negative drain voltages and negative gate voltages and electron and hole transport for large negative drain voltages and negative gate voltages. For VD < (VG VTn), the drain current, ID, of the ambipolar transistor operates in the linear region and the charge transport is determined only by electrons, so that:
I D ¼ ln C G
W VD V G V Tn VD L 2
ð1Þ
where L is the channel length, W is the channel width, ln is the electron charge carrier mobility, CG is the normalized gate capacitance, and VG, VD and VTn are the gate, the drain and the threshold (describing the electron transport) voltages, respectively. For (VG VTn) 6 VD 6 (VG VTp), the transistor saturates and the drain current is given by:
I D ¼ ln C G
W ðV G V Tn Þ2 2L
ð2Þ
The voltage, VTp, refers to the threshold voltage describing the holes transport in the channel. For VD P (VG VTp) and (VG VTn) > 0, the transistor exhibits the behavior of an ambipolar TFT. Holes and electrons contribute to the current flow as follows:
W ID ¼ C G 2L h i ln ðV G V Tn Þ2 þ lp ðV D ðV G V TP ÞÞ2
ð3Þ
where lp is the hole charge carrier mobility. Eq. (3) describes the transistor’s behavior for high drain voltages. For VD P (VG VTp) and (VG VTn) < 0, the complete current flow is determined by holes resulting in the following expression:
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Fig. 2. Different operation modes of an ambipolar TFT depending on the applied bias voltages.
ID ¼ C G
W 2L
h
lp ðV D ðV G V TP ÞÞ2
i
ð4Þ
The four operation regions of an n-type ambipolar transistor can be divided in a linear region (electrons, Eq. (1)), a saturation region (electrons, Eq. (2)), an ambipolar region (electrons and holes, Eq. (3)) and a saturation region (holes, Eq. (4)). 3. Modeling of ambipolar Inverters The circuit of an ambipolar inverter along with its schematic cross-section is shown in Fig. 1c and d. The inverter’s circuit consists of p-type ambipolar (larger negative drain and negative gate voltages) load TFT, while the drive transistor is an n-type ambipolar (larger positive drain and positive gate voltages) TFT. The input of the inverter is connected to the gate of the load and the drive transistor. The source of the load transistor is connected to the supply voltage, VDD, while the source of the drive transistor is connected to ground. The gate voltage of the load TFT is given by VG = VDD Vin and the drain voltage is VD = VDD Vout, while for the drive TFT VG = Vin and VD = Vout. In order to
derive analytical expressions for the voltage transfer characteristics (VTC) of an ambipolar inverter, the characteristics have to be divided into five regions. The five regions are summarized for both, CMOS and ambipolar, inverters in Table 1. Sequencing from region A to region E is carried out by starting with the input voltage, Vin, at 0 V and increasing its value until VDD is reached. In region A, both, the n- and the p-type, ambipolar transistors behave as unipolar TFTs, i.e. only one charge carrier type determines the current. The n-type TFT is on, operating in the saturation region and only holes contribute to the current flow. Conversely, the p-type transistor is also on and operating in linear mode with only holes flowing through the channel. Equating the current of both transistors in the respective modes of operation and solving for the output voltage, Vout, will lead to the following equations for the output voltage:
V ambi out ¼ ðV in þ jV TP jÞ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kp þ ðV DD ðV in þ jV TP jÞÞ2 p P p KP þ KN
ð5Þ
Table 1 Different operating regions of the CMOS and the ambipolar inverters, and their corresponding charge carrier types contributing to the current flow. Operating region
A (0 < Vin < VTN) B (VTN < Vin < VDD/2) C (Vin = VDD/2) D (VDD/2 < Vin < VDD |VTP|) E (VDD |VTP|
CMOS
Ambipolar
n-Type
p-Type
Current flow
n-Type
p-Type
Current flow
Off Satur. Satur. Linear Linear
Linear Linear Satur. Satur. Off
/holes Electr./holes Electr./holes Electr./holes Electr./
Satur. Satur. Satur. Linear Linear
Linear Linear Satur. Satur. Satur.
Holes/holes Holes + electr./holes Electr.-/holes Electr./holes + electr. Electr./electr.
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lN C W
lp C W
where K PN ¼ p LGN N and K Pp ¼ P LGP P , with lNp , WN and LN being the hole charge carrier mobility, the channel width and the channel length of the n-type ambipolar TFT, correspondingly, while lPp , WP and LP are the hole charge carrier mobility, the channel width and the channel length of the p-type ambipolar TFT, respectively. For a CMOS inverter operating in region A, the equation for the output voltage can be obtained by setting lNp to zero (NMOS TFT conducts p only electrons – unipolar device), i.e. kN to zero, in Eq. (5) CMOS which will lead to V out ¼ V DD . Next is region B, where the n-type ambipolar transistor operates in the saturation regime exhibiting an ambipolar behavior and both electrons and holes contribute to the current flow, while the p-type transistor still has a unipolar behavior, i.e. only holes flow through the channel and it operates in the linear regime. Since the current flowing through both TFTs should be the same, using the current equations, with the VD and VG written in terms of Vout and Vin as described before, and equating the respective currents of the transistors, the equation for the output voltage is obtained: V ambi out ¼ ðV in þ jV TP jÞ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kp Kn þ ðV DD ðV in þ jV TP jÞÞ2 p P p ðV in V TN Þ2 p N p KP þ KN KP þ KN ð6Þ N C W N n G
l
where K nN ¼ with lNn , WN and LN being the elecLN tron charge carrier mobility, the channel width and the channel length of the n-type TFT, respectively. Similarly, the equation for a CMOS inverter operating in region B p can be obtained by setting again lNp to zero, i.e. kN ¼ 0, in Eq. (6) due to the unipolarity of the employed TFTs. Region C involves the nearly vertical segment of the VTC, where both of the transistors operate in the saturation regime. By equating the currents IDN (sat) = IDP (sat) again, the following equation for the ambipolar inverter is attained:
V ambi in
qffiffiffiffiffiffi qffiffiffiffiffiffi K pP ðV DD jV TP jÞ þ K nN V TN ¼ qffiffiffiffiffiffi qffiffiffiffiffiffi K nN þ K pP
ð7Þ
As can be seen, Vout is not present in Eq. (7) since the gain is, ideally, infinite due to modeling limitations of the current equations. On the Vin axis this region is a single point, however on the Vout axis the C region is either a single point (for VTP = VTN = 0 V) or a line ranging between VDD/2VTP and VDD/2VTN (for nonzero threshold voltages). Further, in this region of the VTC falls the voltage VM at which Vout = Vin. Eq. (7) can be used without modification for CMOS inverters operating in this region, since no ambipolarity is involved in the expression describing the output voltage. In region D, the n-type ambipolar TFT still exhibits a unipolar behavior (only electrons contribute to the current flow) and operates in the linear region, while the p-type TFT has an ambipolar behavior and operates in the saturation regime. Yet again, equating the currents of the TFTs and solving for Vout gives the expression for the output voltage in this region:
V ambi out ¼ ðV in V TN Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kn Kp ðV in V TN Þ2 n N n ðV DD ðV in þ jV TP jÞÞ2 n P n KN þ KP KN þ KP
ð8Þ
Again, the equation a CMOS inverter operating in region n D can be obtained by substituting kP ¼ 0 in Eq. (8). In the last region, E, the ambipolar TFTs have a unipolar behavior. The n-type TFT has only electrons flowing and operates in the linear regime, while the p-type TFT has also only electrons contributing to the current and operates in the saturation regime. If the currents are equated and the equation is solved for Vout, the following expression for the output voltage is obtained:
V ambi out ¼ ðV in V TN Þ
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Kn ðV in V TN Þ2 n N n KN þ KP
ð9Þ
For a CMOS inverter, region E is where one of the TFTs is off (the PMOS is switched off, since VG = VDD Vin < |VTP|, i.e. Vin > VDD |VTP|), so there is nearly no current flowing through the TFTs, thus the output voltage is 0 V, which n could be, as before, obtained from Eq. (9) by setting kP ¼ 0. Using the developed models, the VTC of both, CMOS and ambipolar inverters were simulated for different charge carrier mobility ratios and threshold voltages, as shown in Fig. 3. The parameters used for each simulation are given in the respective figure. The VTCs were simulated for symmetrical n- and p-type transistors. The VTC curves of a CMOS inverter, shown in Fig. 3a, are plotted for different charge carrier mobility ratios, and demonstrate the effect of the charge transport on the inverter characteristics. For balanced electron and hole transport properties of the NMOS and the PMOS transistors, respectively, the switching voltage is half the supply voltage, VDD. For unbalanced charge carrier transport properties, the switching voltage shifts to higher Vin when the hole mobility exceeds the electron mobility and vice versa to lower Vin for a superior electron mobility. The effect of the charge carrier mobility ratio on the ambipolar inverters’ VTC is similar to that of CMOS inverters, as illustrated in Fig. 3c – depending on the ratio of the mobilities, the switching voltage is shifted to higher or lower Vin. The effect of increasing the threshold voltage (both VTN and |VTP| are equally and symmetrically increased) can be observed in Fig. 3b (CMOS inverters) and d (ambipolar inverters). Increasing the threshold voltages affects the shape of the VTC characteristic. The shape of the VTC has an effect on the noise margin of the inverters, which is of crucial importance when building more advanced circuits [15]. In order to verify the correctness of the derived model, the VTCs of both, CMOS and ambipolar, inverters were also experimentally measured. 4. Experimental results 4.1. Microcrystalline silicon thin-film transistors and CMOS inverters As a first step towards the realization of silicon thin-film CMOS inverters, p- and n-channel unipolar
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Fig. 3. Simulated VTC of (a and b) a CMOS and (c and d) an ambipolar inverter for different (a and c) charge carrier mobility ratios (VDD = 5 V; VTN = VTH = 0 V; lNn =lPp ¼ lPn =lNp ¼ 0:1; 1; 10) and (b and d) threshold voltages (VDD = 5 V; lNn =lPp ¼ lPn =lNp ¼ 1; VTN = VTH = 0, 1, 2 V). The VTCs were simulated for LN = LP = 2 lm and WN = WP = 1000 lm.
microcrystalline silicon (lc-Si:H) TFTs were fabricated. The drain and the source metal electrodes of the lc-Si:H TFTs were prepared by electron beam evaporation of chromium (Cr) with a thickness of 30 nm on glass substrates. The highly doped n/p-type lc-Si:H layer with thickness of 25 nm was prepared by plasma-enhanced chemical vapor deposition (PECVD) at 180 °C. Next, the channel material with thickness of 100 nm was deposited by a PECVD process at 160 °C [16]. The gate dielectric was realized by silicon oxide (SiO2) with film thickness of 300 nm also by PECVD process at 150 °C. And finally, the gate electrode of the transistors was formed by thermally evaporated aluminum. The measured unipolar lc-Si:H TFTs exhibited electron (n-type unipolar TFT) and hole (p-type unipolar TFT) charge carrier mobilities exceeding 50 and 12 cm2/V s, respectively. The measured transfer characteristics of an n-type unipolar TFT is shown in Fig. 4a. The extracted subthreshold slopes of the TFTs are larger than 0.75 V/decade. To validate the correctness of the developed model, the fabricated p- and n-channel lc-Si:H TFTs were used to realize CMOS inverters. Fig. 4b shows the voltage transfer characteristics of a CMOS inverter using an n-channel TFT (L = 20 lm and W = 200 lm) and a p-channel TFT (L = 20 lm and W = 1000 lm) for supply voltages of 5, 6, and
7 V. The increased channel width of the PMOS TFT compensates its lower hole charge carrier mobility. The experimentally extracted voltage gain, which is defined to be @V out =@V in , ranges from 15 to 22 and a clear and abrupt transition from high- to low-state is observed. The measured voltage gain is high in comparison to other values published in literature [17]. 4.2. Microcrystalline silicon ambipolar thin-film transistors and inverters In the case of the ambipolar lc-Si:H TFTs, the deposition processes and temperatures, the materials’ type, and the thicknesses of all the respective layers are same as for the unipolar lc-Si:H TFTs, except that now the highly doped n- or p-layers were not inserted between the metal contacts and the microcrystalline silicon channel layer, as the doped layer-free lc-Si:H ambipolar transistors have been demonstrated [18]. The fabricated ambipolar lc-Si:H TFTs exhibit charge carrier mobilities of 40 and 10 cm2V s. The transfer characteristics of the n-type ambipolar transistor are shown in Fig. 5a. The transistors exhibit subthreshold slope of around 0.5 V/decade. The lc-Si:H ambipolar TFTs were used to realize ambipolar inverters. The experimentally measured VTC of the
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Fig. 4. (a) Transfer characteristics of an n-type unipolar lc-Si:H TFT (L = 10 lm; W/L = 100). The transfer curves were measured for VD = 0.5, 1, 1.5 V. (b) Experimentally obtained VTCs of a CMOS inverter. The VTCs were measured for VDD = 5, 6, 7 V.
Fig. 5. (a) Transfer characteristics of an n-type ambipolar lc-Si:H TFT (L = 20 lm; W/L = 50). The transfer curves were measured for VD = 0.1, 1, 3 V. (b) Experimentally obtained VTCs of a microcrystalline silicon ambipolar inverter. The VTCs were measured for VDD = 3, 4, 5, 6 V.
lc-Si:H ambipolar inverter are shown in Fig. 5b. The ambipolar inverter was realized using a n-channel ambipolar TFT with a channel length (L) of 20 lm and a channel width (W) of 200 lm, and a p-channel ambipolar TFT with a channel length of 20 lm and a channel width of 1000 lm. The increased channel width of the p-channel transistor compensates for the reduced charge charier mobility of the p-channel transistor. The inverters exhibit voltage gains comparable to that of CMOS inverters. The experimentally extracted voltage gain is equal 5–10. On the other hand, the output voltage of the ambipolar lc-Si:H inverter in the logical low-state increases with increasing input voltage, which can be explained by the high off-current of the constituent p-channel ambipolar lc-Si:H transistor at high VD [19]. 4.3. Organic ambipolar thin-film transistors and inverters Further, another type of ambipolar organic TFTs were prepared with nickel dithiolene as the channel material. The transistors were made using heavily doped p-type Si
wafers as the back gate electrode with a 200 nm thermally oxidized SiO2 layer as the gate dielectric. Using conventional photolithography, gold source and drain electrodes were defined with channel length and width in the ranges of 1.5–40 lm and 1–20 mm, respectively. A 10 nm layer of titanium was used as an adhesion layer for the gold on the SiO2. The SiO2 layer was treated with the primer hexamethyldisilazane prior to semiconductor deposition. Thin films of nickel dithiolene were spin-coated from a 10 mg mL1 solution using chloroform. Spin-coating was performed at 500 rpm for 60 s under ambient conditions. The transfer characteristics of the prepared ambipolar nickel dithiolene TFTs are shown in Fig. 6a. The electron and hole mobilities (calculated in saturation), measured in as-prepared devices under ambient light and air, are on the order of 104 cm2/V s. This value is typical, with the highest measured value being on the order of 103 cm2/V s. We note, however, that in the linear regime holes are more mobile than electrons by approximately a factor of two, with typical electron mobilities in the range of 2 104 to 8 104 cm2/V s. The p-type and n-type
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Fig. 6. (a) Transfer characteristics for an n-type and a p-type amipolar nickel dithiolene TFT, measured for VD = 5, 15 V and VD = 5, 15 V, respectively. (b) Experimentally obtained VTC of a polymer ambipolar inverter. The VTC were measured for VDD = 20 V and the extracted values for the static noise margin were SNML = 3.92 V and SNMH = 4.68 V.
ambipolar transistors exhibit threshold voltages of 10 V and 5 V, respectively. The fabricated nickel dithiolene ambipolar TFTs were used to realize CMOS-like inverters and the measured VTCs are shown in Fig. 6b. The inverter was realized by p-type ambipolar nickel dithiolene TFT with channel length and width of 5 and 100 lm, respectively, and n-type ambipolar nickel dithiolene TFT with channel length and width of 5 and 1000 lm, correspondingly. The inverter exhibit a maximum voltage gain of around 6. 5. Discussion Comparing the measured and the simulated VTC shows that the model correctly describes the characteristics of the CMOS and the ambipolar inverters. Furthermore, the derived model for the CMOS and the ambipolar inverter is in a good agreement with experimental results published in literature [19–22]. The slight difference between the simulated and measured VTCs of both, CMOS and ambipolar, inverters is due to the asymmetry of the prepared transistors used in the experiments. The transistors are described by ideal transistor equations. The influence of non-ideal effects, like contact or output resistances are not considered. Contact effects are responsible for the formation of an S-shape in the linear region of operation. In order to account for the drain voltage dependent modulation of the channel length in the saturation region, often an output resistance is considered [15]. In the case of a CMOS inverter, the contact and the output resistances have an effect on the VTC in region B, C and D. In the case of an ambipolar inverter, the contact and the output resistances affect all five regions (A–D) of the voltage transfer curve. As a consequence, the noise margin and the voltage gain of the inverters are reduced. Furthermore, the influence of the subthreshold characteristics of the transistors on the VTC is not considered. The subthreshold characteristics of organic transistors are very often affected by unintentional doping or environmental effects, which again will lead to a drop of the static noise margin [23].
In the next step, the static noise margin (SNM) [24,25] was determined for the measured and simulated inverters. Several approaches have been suggested in literature to determine the SNM. In our study, we have selected an approach in which the SNM is defined as the largest possible rectangle that is fitted between the measured and its imaged VTC. The sides of the rectangle define the high and the low SNM. For a perfectly symmetric VTC, the fitted shape becomes a square, so that the high and the low SNM margin are identical. Nevertheless, in most of the cases the inverter characteristics are not symmetric, so that we obtain different values for the high and the low noise margin. Other approaches define the SNM as a square that is fitted between the measured and the imaged VTC, which seem better suited to analyze the behavior of inverters since only one value for the SNM is acquired. However, numerical methods are needed to maximize the area of the fitted square. Therefore, no analytical expression of the SNM can be derived. The approach employed in this study uses the -1 slope definition of the VTC to calculate the low and the high SNM. This allows for deriving an analytical expression for the SNM. We will accept the consequence of getting a low and high SNM at the expense of gaining a better insight and a more intuitive understanding of the inverter operation. Further details on the definition of the SNM and its extraction from the VTC can be found elsewhere in literature [24–26]. Fig. 7a and b shows the calculated and the measured noise margin as a function of the supply voltage, for both, CMOS and ambipolar inverters, respectively. The SNM increases with increasing the supply voltage, irrespective of the threshold voltage. Additionally, there is a good agreement between the simulated and the experimentally measured SNM. The trend of the experimentally measured SNM follows the trend of the simulated SNM, for both, CMOS and ambipolar inverters. The difference between the SNML and SNMH arises from the asymmetry of the VTC, which is the consequence of the difference between the threshold voltage and the mobility of the n- and p-type transistors. For identical device parameters, the CMOS inverter exhibits a high SNM, which increases with the threshold
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Fig. 7. Comparison of the static noise margin (SNM) of CMOS and ambipolar inverters with the experimental data. The influence of VDD on the SNM of (a) CMOS and (b) ambipolar inverters for different VT. All the simulation parameters of the constituent TFTs are same for both inverters ðlNn =lPp ¼ lPn =lNp ¼ 1Þ.
voltage and the supply voltage. For CMOS inverters, ideally, the maximum noise margin can reach half the supply voltage, if the threshold voltage reaches half VDD. The SNM of the CMOS inverter with identical threshold voltages and mobilitities can be calculated by:
SNMCMOS ¼
V DD V TH þ 4 2
for 0 < V Th <
V DD 2
ð10Þ
The static noise margin varies between VDD/4 and VDD/2. In order to maximize the SNM, the threshold voltage should be half the supply voltage. If VTH is larger than the half the supply voltage, the transistors operate in the subthreshold region. Such mode of operation is often used in microelectronics. However, the presented model does not take the subthreshold region into account. The SNM of the ambipolar inverter with symmetric threshold voltages and mobilities is given by:
SNMambi ¼
V DD V TH þ3 8 4
for 0 < V Th <
V DD 4
ð11aÞ
The static noise margin varies between VDD/8 and VDD/4. If the equation would be valid for threshold voltages up to VDD/2, the SNM would reach VDD/2. Therefore, the SNM of an ambipolar inverter would be equal to the noise margin of a CMOS inverter. However, this is not the case. The operation of the ambipolar inverter has been divided in two regions. The SNM of the ambipolar inverter is limited by the high off-current of the transistor that is in the off-state. For threshold voltages larger than VDD/4, the static noise margin can be described by:
SNMambi ¼
V DD V TH þ 4 4
for
V DD V DD < V TH < 4 2
ð11bÞ
For threshold voltages equal to half the supply voltage the static noise margin reaches a maximum of 3 VDD/8. In the following the SNMs of the CMOS and the ambipolar inverters are compared. The maximum static noise margin of a CMOS inverter for a threshold voltage of 0 V is equal to VDD/4, whereas the maximum static noise margin for an ambipolar inverter is equal to VDD/8. Therefore, the SNM of an ambipolar inverter reaches only 50% of the SNM of a CMOS inverter. With
increasing threshold voltage the difference of the noise margin between the CMOS and the ambipolar inverter becomes smaller. Increasing the VTH of the ambipolar transistors up to VDD/4 leads to a distinct increase of the static noise margin. For a threshold voltage of VDD/4, the SNM of the CMOS inverter reaches 3 VDD/8, while the ambipolar inverter reaches 5 VDD/16. Therefore, the SNM of the ambipolar inverter reaches 5/6 or 83.3% of the SNM of the CMOS inverter. For threshold voltages of VDD/4 the difference between the two types of inverters is minimized. For maximum threshold voltages of VDD/2, the SNM of the CMOS inverter reaches VDD/2, while the SNM of the ambipolar inverter reaches 3 VDD/8. As a consequence the ambipolar inverter reaches only 75% of the SNM of the CMOS inverter. In order to maximize the static noise margin and minimize the power consumption, the threshold voltage of an inverter should be equal to VDD/2. Under such conditions the SNM of the ambipolar inverter reaches 75% of the performance of a CMOS inverter. Though, the application of ambipolar inverters is limited by the noise margin, as discussed above, they are still an interesting addition to the existing CMOS inverter technology, since they provide a simple route in realization of large area integrated circuits at low cost using simple fabrication processes. Nevertheless, the power consumption of ambipolar inverters is significantly higher than the power consumption of CMOS inverters. As a solution to this problem interesting novel device structures using transistors with double gates have been suggested. One of the two gates (programmable gate) of the transistor is used to control the injection of charges in the semiconductor. By using the programmable gate the high off-current of the ambipolar transistors can be suppressed. Such device have been demonstrated for carbon nanotube FETs (CNFETs) [27– 30] and Si FETs [31]. However, further investigations are needed to study transistors with a double gate geometry.
6. Summary Simple analytical models were presented, that allow for describing the voltage transfer characteristics of both,
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CMOS and ambipolar inverters. The presented models provide insights into the electrical characteristics of both inverter technologies. They were used to investigate the effect of different transistor parameters on the static noise margin. Further, the correctness of the models was validated with experimental measurements. A good agreement between the models and the experimental data was observed. A comparison of the model for CMOS and ambipolar inverters shows that the SNM of ambipolar inverters can reach 75% of the CMOS inverter’s static noise margin. Acknowledgement The authors like to acknowledge S. Bunte and Y. Mohr (IBN-PT) for preparation of the PECVD SiO2, M. Hülsbeck, J. Kirchhoff, T. Melle, S. Michel, and R. Schmitz (all IEFPV) for technical assistances in preparing the lc-Si:H TFTs and E. Bunte, R. Carius, D. Hrunski, and V. Smirnov (all IEFPV) for helpful discussions. Furthermore, the authors would like to thank M. Marinkovic, and E. Hashem (all JUB) for electrical measurements and V. Wagner (JUB) for discussion. References [1] H. Klauk, Organic Electronics: Materials, Manufacturing, and Applications, Wiley, 2006. [2] W.S. Wong, A. Salleo, Flexible Electronics: Materials and Applications, Springer, Heidelberg, 2009. [3] R.A. Street, Thin-film transistors, Adv. Mater. 21 (2009) 2007–2022. [4] G. Gelinck, P. Heremans, K. Nomoto, T.D. Anthopoulos, Organic transistors in optical displays and microelectronic applications, Adv. Mater. 22 (2010) 3778–3798. [5] B. Stannowski, R.E.I. Schropp, R.B. Wehrspohn, M.J. Powell, Amorphous-silicon thin-film transistors deposited by VHF-PECVD and hot-wire CVD, J. Non-Cryst. Solids 299–302 (2002) 1340–1344. [6] S.D. Brotherton, Polycrystalline silicon thin film transistors, Semicond. Sci. Technol. 10 (1995) 721–738. [7] K.-Y. Chan, J. Kirchhoff, A. Gordijn, H. Stiebig, D. Knipp, Ambipolar microcrystalline silicon transistors and inverters, Solid-State Electron. 53 (2009) 635. [8] E.J. Meijer, D.M. de Leeuw, S. Setayesh, E. Van Veenendaal, B.-H. Huisman, P.W.M. Blom, J.C. Hummelen, U. Scherf, T.M. Klapwijk, Solution-processed ambipolar organic field-effect transistors and inverters, Nat. Mater. 2 (2003) p. 678. [9] Y. Zhou, A. Gaur, S.-H. Hur, C. Kocabas, M.A. Meitl, M. Shim, J.A. Rogers, p-Channel, n-Channel thin-film trasistors and p-n diodes based on single wall carbon nanotube networks, Nano Lett. 4 (2004) 2031–2035. [10] F. Xia, D.B. Farmer, Y.-M. Lin, P. Avouris, Graphene field-effect transistors with high on/off current ratio and large transport band gap at room temperature, Nano Lett. 10 (2010) 715–718.
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