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Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device
Microelectronic Engineering 84 (2007) 161–164 www.elsevier.com/locate/mee
Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device Yong-Jin Seo a
a,*
, Kil-Ho Kim
b
Department of Electrical Engineering, Daebul University, 72, Youngam, Chonanm-do 526-702, Republic of Korea b Korea Design Center, Leadis Technology Inc., Kyungki-do 463-954, Republic of Korea Received 17 May 2006; received in revised form 20 September 2006; accepted 25 September 2006 Available online 23 October 2006
Abstract In this study, the effects of background doping concentration (BDC) of a high voltage operating extended drain N-type MOSFET (EDNMOS) device on electrostatic discharge (ESD) protection performances were evaluated. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC. 2006 Elsevier B.V. All rights reserved. Keywords: Background doping concentration (BDC); Electrostatic discharge (ESD); Extended drain N-type MOSFET (EDNMOS); Double snapback
1. Introduction Electrostatic discharge (ESD) protection performance is a major concern in the high voltage operating microchips. Stable ESD protection is hardly achieved in terms of high voltage operating N-type MOSFET devices. Their weakness to the ESD stress is attributed to the extremely strong snapback, which results in current crowding and melting damage, non-uniform multi-finger triggering, and high latchup risk [1–3]. Extensive works have been devoted to achieve stable ESD protection performance, however ended with only limited successes [4–7]. In order to realize stable ESD protection performance in the high voltage operating N-type MOSFET devices, their mechanisms in high current region should be understood first. Recently, the high voltage operating double N-type MOSFET devices are shown to have double snapback phenomenon, where the 2nd on-state is characterized by extre*
Corresponding author. Tel./fax: +82 61 469 1260. E-mail address: [email protected] (Y.-J. Seo).
0167-9317/$ - see front matter 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.09.030
mely low snapback holding voltage [8]. Related mechanism is known to be the high electron injection induced base push-out [9,10]. Since the base push-out happens when the injected electron density overwhelms the background carrier densities, the background doping concentration (BDC) may be a critical factor to the occurrence of the double snapback phenomenon. Thus, the effects of the BDC on the current–voltage (I–V) characteristics of the high voltage operating N-type MOSFETs need to be investigated. This paper, focusing optimization methodology for ESD protection, shows the effects of BDC in the extended drain N-type MOSFET (EDNMOS) device, which is one specific type of the DDDNMOS device. 2. Device structure and simulation methodology The high voltage operating EDNMOS device is characterized by double diffused drain structure and non-adjacency of the gate to the drain N+ diffusion as shown in Fig. 1. The background of the EDNMOS device consists
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Y.-J. Seo, K.-H. Kim / Microelectronic Engineering 84 (2007) 161–164
Fig. 1. Schematic diagram of an extended drain N-type MOSFET (EDNMOS) device.
of the HP-Well region and the N-Drift region. When the EDNMOS device is used for the ESD protection application, the drain N+ diffusion is connected to Vdd power pad (or to each I/O pad) while the gate, the source, and the well-pickup are all tied together and connected to Vss ground pad. The high current characteristics of the EDNMOS devices are investigated using thermal incorporated 2-dimensional simulations. The devices were fabricated using TSUPREM4 (Synopsys Co.) process simulator following a typical high voltage technology, and their characteristics were analyzed using DESSIS (ISE Inc.) device simulator. In order to simulate human body model (HBM) ESD stress, the mixed mode transient (MMT) simulations were performed adopting ladder type current pulses with rise time 10 ns and duration 100 ns. A transmission line pulse (TLP) test system was used to monitor the high current response of the EDNMOS devices experimentally [11]. During the measurement, the pulse rise time and the duration were also kept to 10 ns and 100 ns, respectively. 3. Results and discussion Fig. 2a and b shows I–V characteristics of the 1-finger structure EDNMOS devices with two different BDC conditions as shown in Table 1. The graphs in Fig. 2 clearly show that the BDC is a critical factor in the high current behavior of the EDNMOS device. Both the simulation results and the TLP (transmission line pulse) data show a characteristic double snapback phenomenon in the EDNMOS with low BDC. (low BDC : HP-Well implant dose = 7.5 · 1012 cm 2 and N-Drift implant dose = 1.1 · 1013 cm 2). The 2nd onstate is characterized in terms of low snapback holding voltage (Vh1), low thermal breakdown current, and also low thermal breakdown voltage (Vav) which is much smaller than the triggering voltage (Vtr). Once the EDNMOS device enters 2nd on-state with such characteristics, current localization and subsequent melting damage may easily occur to result in high vulnerability to the ESD stress. Non-uniform multi-finger triggering and high latchup risk are other problems which result from the strong snapback characteristics of the EDNMOS device [2,3].
Fig. 2. (a) Simulation results on I–V relations of 1-finger structure EDNMOS devices with different background doping concentrations (low BDC (j): HP-Well implant dose = 7.5 · 1012 cm 2 and N-Drift implant dose = 1.1 · 1013 cm 2, high BDC (s): with HP-Well implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 10 13 cm 2), (b) TLP measurement data of two BDCs.
Table 1 Implant conditions of background region Background
HP-Well implant dose
N-Drift implant dose
Low BDC High BDC
7.5 · 1012 cm 1.7 · 1013 cm
1.1 · 1013 cm 4.0 · 1013 cm
2 2
2 2
Upon increasing the BDC over certain critical limit, (high BDC: HP-Well implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 1013 cm 2), the EDNMOS device seem to escape from the problematic double snapback phenomenon. Instead, it just remains within the 1st on-state with moderate snapback holding voltage. High thermal breakdown current and high thermal breakdown voltage are another aspects of the EDNMOS device with high BDC. The high thermal breakdown voltage, comparable to or larger than its triggering voltage, implies uniform multi-finger triggering, which subsequently results in the linearity of the current immunity level for the finger number of the EDNMOS device. Both the high thermal breakdown current level and the linearity of the current immunity level for the finger number guarantee stable ESD protection performance. Moreover, the moderate snapback holding voltage compared to its triggering volt-
Y.-J. Seo, K.-H. Kim / Microelectronic Engineering 84 (2007) 161–164
age implies low latchup risk for the given operation voltage applicable with the EDNMOS device with high BDC. The simulation data (Fig. 2a) and corresponding TLP test data (Fig. 2b) show qualitatively consistent results for the effects of BDC, even though there are quantitative mismatches due to poor calibration. It should be noted that the practical usage of this methodology, controlling of BDC for ESD protection performances, is very limited because the junction breakdown voltage and the consequential operation voltage is strongly dependent on the BDC. That is to say, the high BDC over certain critical limit may guarantee the stable ESD protection performance in the EDNMOS device. However, the EDNMOS device with enhanced BDC can be adopted only in the limited range of the operation voltage because of its lowered junction breakdown voltage. Related mechanisms for the effects of the BDC can be clearly understood in terms the contour data of current density, electric field, and maximum temperature region as shown in Fig. 3. Upon the triggering of parasitic bipolar junction transistor (BJT) operation, a vertical directional U-shaped current path is formed between the drain N+ diffusion and the source N+ diffusion region. This is the situation in the 1st on-state, both in the EDNMOS with low BDC and in the EDNMOS with high BDC, before the characteristic double snapback occurs [8]. When higher current is applied to the EDNMOS with low BDC, the high electron injection induced base pushout occurs and a lateral directional deep electron channel is formed right under the gate to result in a low resistive and short current path between the source and the drain. The high electric field region, which designates the boundary of the base region, is shifted from the original HP-Well/ N-Drift boundary to the N-drift/N+ diffusion boundary.
163
As a result, high localized maximum temperature region appears at the surface of N-drift/N+ diffusion boundary. Exact matching between the site of high electric field and that of maximum temperature is clearly seen. The low resistive and short current path following the deep electron channel can explain the occurrence of the 2nd on-state with such a low on-resistance. The high electron injection induced base push-out and the consequential double snapback has been addressed in several publications [8–10]. The EDNMOS with high BDC never exhibits the base push-out even in the high current region. Thus, the initially formed U-shaped current conduction path is maintained until the thermal breakdown occurs. High electric region is stuck to the HP-Well/N-Drift boundary. The non-localized maximum temperature region is formed along the bottom directional HP-Well/N-Drift boundary. The nonlocalized property of maximum temperature region guarantees higher current immunity level under ESD stress. The TLP measurement data in Fig. 4 shows the I–V relations of the high BDC EDNMOS devices for various finger numbers. The non-uniformity of multi-finger triggering has been a critical problem to hinder the EDNMOS device from being adopted as ESD protection devices. It is generally accepted that uniform multi-finger triggering is guaranteed when the thermal breakdown voltage is larger than the BJT triggering voltage. Data in Fig. 2 shows that this uniformity condition is largely violated in the EDNMOS with low BDC. However, the EDNMOS with high BDC appears to satisfy the required uniformity condition. Thus, uniform multi-finger triggering is rather expected in the EDNMOS with high BDC. The TLP data in Fig. 4 shows that the thermal breakdown current (It2) of the EDNMOS device with high BDC generally increases when its finger number increases. The linearity of the thermal breakdown current upon increasing the finger number from 1 to 2 is relatively poor. This is because the drain site of the EDNMOS is commonly used upon increasing the finger number from 1 to 2. However, almost linear depen2.5 1x50um It2=460mA
Drain Current (A)
2.0
2x50um It2=610mA 4x50um It2=1210mA 6x50um It2=1650mA
1.5
8x50um It2=2230mA
1.0 0.5
Fig. 3. (a) Contours of current density, electric field, and local temperature for EDNMOS device with low BDC (HP-Well implant dose = 7.5 · 1012 cm 2 and N-Drift implant dose = 1.1 · 1013 cm 2). The contour data are obtained at the drain current level 4 mA/um. (b) for EDNMOS device with high BDC (HP-Well implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 1013 cm 2) at the drain current level 8 mA/um.
0.0 0
10 20 30 Drain Voltage (V)
40
Fig. 4. TLP measurement data on I–V relations of the high BDC (HPWell implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 1013 cm 2) EDNMOS devices for various finger numbers. The thermal breakdown current levels (It2) for each finger number are shown in the inset.
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Y.-J. Seo, K.-H. Kim / Microelectronic Engineering 84 (2007) 161–164
dence of the current immunity level on the finger number is clearly seen upon increasing the finger number from 2 to 4, 6, or 8 ( Note that the 8-finger trigger efficiency against to 2-finger trigger efficiency is 91%). This suggests that the poor scaling behavior of the EDNMOS devices can also be cured by properly controlling their BDCs. The thermal breakdown current levels according to its finger numbers are listed in the inset of Fig. 4. 4. Conclusion The problematic strong snapback phenomenon and poor ESD protection performance of the EDNMOS device can be cured by properly controlling its background doping concentration (BDC). The EDNMOS with high BDC does not show the double snapback and remains within the 1st on-state. This implies that both the stable ESD protection performance and the low risk for the latchup problem can be realized in terms of the EDNMOS device by keeping its BDC sufficiently high. However, It should be noted that controlling its BDC for ESD protection application is practically of limited usage because the junction breakdown voltage is dependent on the BDC. Further achievements to overcome this limit are expected in the future works.
Acknowledgment This work was supported by Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2005-041-D00311). References [1] G. Bosselli, S. Meeuwsen, T. Mouthaan, F. Kuper, Proc. EOS/ESD Symp. (1999) 11–18. [2] M.P.J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker, W. Fichtner, IEEE Trans. Electron Dev. 47 (2000) 2128–2137. [3] B. Keppens, M.P.J. Mergens, C.S. Trinh, C.C. Russ, B.V. Camp, K.G. Verhaege, Proc. EOS/ESD Symp. (2004) 289–298. [4] C. Duvvury, F. Carvajal, C. Jones, D. Briggs, IEDM Tech. Dig. (1997) 375–378. [5] K. Kawamoto, S. Takahashi, S. Fujino, I. Shirakawa, IEEE Trans. Electron Dev. 49 (2002) 2047–2053. [6] V. Parthasarathy, V. Khemka, R. Zhu, J. Whitfield, R. Ida, A. Bose, IEEE Electron Dev. Lett. 23 (2002) 212–214. [7] B.C. Jeon, S.C. Lee, J.K. Oh, S.S. Kim, M.K. Han, Y.I. Jung, H.T. So, J.S. Shim, K.H. Kim, Proc. EOS/ESD Symp. (2002) 362–372. [8] M.D. Ker, K.H. Lin, IEEE Electron Dev. Lett. 25 (2004) 640–642. [9] S.M. Sze, Physics of Semiconductor Devices, second ed., Wiley, New York, 1981. [10] M. Streibl, K. Esmark, A. Sieck, W. Stadler, M. Wendel, J. Szatkowski, H. Goßner, Proc. EOS/ESD Symp. (2002) 73–82. [11] J.E. Barth, K. Verhaege, L.G. Henry, J. Richner, IEEE Trans. Electron. Packaging Manufact. 24 (2001) 99.
Effects of background doping concentration on electrostatic discharge protection of high voltage operating extended drain N-type MOS device Yong-Jin Seo a
a,*
, Kil-Ho Kim
b
Department of Electrical Engineering, Daebul University, 72, Youngam, Chonanm-do 526-702, Republic of Korea b Korea Design Center, Leadis Technology Inc., Kyungki-do 463-954, Republic of Korea Received 17 May 2006; received in revised form 20 September 2006; accepted 25 September 2006 Available online 23 October 2006
Abstract In this study, the effects of background doping concentration (BDC) of a high voltage operating extended drain N-type MOSFET (EDNMOS) device on electrostatic discharge (ESD) protection performances were evaluated. The EDNMOS device with low BDC suffers from strong snapback in the high current region, which results in poor ESD protection performance and high latchup risk. However, the strong snapback can be avoided in the EDNMOS device with high BDC. This implies that both the good ESD protection performance and the latchup immunity can be realized in terms of the EDNMOS by properly controlling its BDC. 2006 Elsevier B.V. All rights reserved. Keywords: Background doping concentration (BDC); Electrostatic discharge (ESD); Extended drain N-type MOSFET (EDNMOS); Double snapback
1. Introduction Electrostatic discharge (ESD) protection performance is a major concern in the high voltage operating microchips. Stable ESD protection is hardly achieved in terms of high voltage operating N-type MOSFET devices. Their weakness to the ESD stress is attributed to the extremely strong snapback, which results in current crowding and melting damage, non-uniform multi-finger triggering, and high latchup risk [1–3]. Extensive works have been devoted to achieve stable ESD protection performance, however ended with only limited successes [4–7]. In order to realize stable ESD protection performance in the high voltage operating N-type MOSFET devices, their mechanisms in high current region should be understood first. Recently, the high voltage operating double N-type MOSFET devices are shown to have double snapback phenomenon, where the 2nd on-state is characterized by extre*
Corresponding author. Tel./fax: +82 61 469 1260. E-mail address: [email protected] (Y.-J. Seo).
0167-9317/$ - see front matter 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2006.09.030
mely low snapback holding voltage [8]. Related mechanism is known to be the high electron injection induced base push-out [9,10]. Since the base push-out happens when the injected electron density overwhelms the background carrier densities, the background doping concentration (BDC) may be a critical factor to the occurrence of the double snapback phenomenon. Thus, the effects of the BDC on the current–voltage (I–V) characteristics of the high voltage operating N-type MOSFETs need to be investigated. This paper, focusing optimization methodology for ESD protection, shows the effects of BDC in the extended drain N-type MOSFET (EDNMOS) device, which is one specific type of the DDDNMOS device. 2. Device structure and simulation methodology The high voltage operating EDNMOS device is characterized by double diffused drain structure and non-adjacency of the gate to the drain N+ diffusion as shown in Fig. 1. The background of the EDNMOS device consists
162
Y.-J. Seo, K.-H. Kim / Microelectronic Engineering 84 (2007) 161–164
Fig. 1. Schematic diagram of an extended drain N-type MOSFET (EDNMOS) device.
of the HP-Well region and the N-Drift region. When the EDNMOS device is used for the ESD protection application, the drain N+ diffusion is connected to Vdd power pad (or to each I/O pad) while the gate, the source, and the well-pickup are all tied together and connected to Vss ground pad. The high current characteristics of the EDNMOS devices are investigated using thermal incorporated 2-dimensional simulations. The devices were fabricated using TSUPREM4 (Synopsys Co.) process simulator following a typical high voltage technology, and their characteristics were analyzed using DESSIS (ISE Inc.) device simulator. In order to simulate human body model (HBM) ESD stress, the mixed mode transient (MMT) simulations were performed adopting ladder type current pulses with rise time 10 ns and duration 100 ns. A transmission line pulse (TLP) test system was used to monitor the high current response of the EDNMOS devices experimentally [11]. During the measurement, the pulse rise time and the duration were also kept to 10 ns and 100 ns, respectively. 3. Results and discussion Fig. 2a and b shows I–V characteristics of the 1-finger structure EDNMOS devices with two different BDC conditions as shown in Table 1. The graphs in Fig. 2 clearly show that the BDC is a critical factor in the high current behavior of the EDNMOS device. Both the simulation results and the TLP (transmission line pulse) data show a characteristic double snapback phenomenon in the EDNMOS with low BDC. (low BDC : HP-Well implant dose = 7.5 · 1012 cm 2 and N-Drift implant dose = 1.1 · 1013 cm 2). The 2nd onstate is characterized in terms of low snapback holding voltage (Vh1), low thermal breakdown current, and also low thermal breakdown voltage (Vav) which is much smaller than the triggering voltage (Vtr). Once the EDNMOS device enters 2nd on-state with such characteristics, current localization and subsequent melting damage may easily occur to result in high vulnerability to the ESD stress. Non-uniform multi-finger triggering and high latchup risk are other problems which result from the strong snapback characteristics of the EDNMOS device [2,3].
Fig. 2. (a) Simulation results on I–V relations of 1-finger structure EDNMOS devices with different background doping concentrations (low BDC (j): HP-Well implant dose = 7.5 · 1012 cm 2 and N-Drift implant dose = 1.1 · 1013 cm 2, high BDC (s): with HP-Well implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 10 13 cm 2), (b) TLP measurement data of two BDCs.
Table 1 Implant conditions of background region Background
HP-Well implant dose
N-Drift implant dose
Low BDC High BDC
7.5 · 1012 cm 1.7 · 1013 cm
1.1 · 1013 cm 4.0 · 1013 cm
2 2
2 2
Upon increasing the BDC over certain critical limit, (high BDC: HP-Well implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 1013 cm 2), the EDNMOS device seem to escape from the problematic double snapback phenomenon. Instead, it just remains within the 1st on-state with moderate snapback holding voltage. High thermal breakdown current and high thermal breakdown voltage are another aspects of the EDNMOS device with high BDC. The high thermal breakdown voltage, comparable to or larger than its triggering voltage, implies uniform multi-finger triggering, which subsequently results in the linearity of the current immunity level for the finger number of the EDNMOS device. Both the high thermal breakdown current level and the linearity of the current immunity level for the finger number guarantee stable ESD protection performance. Moreover, the moderate snapback holding voltage compared to its triggering volt-
Y.-J. Seo, K.-H. Kim / Microelectronic Engineering 84 (2007) 161–164
age implies low latchup risk for the given operation voltage applicable with the EDNMOS device with high BDC. The simulation data (Fig. 2a) and corresponding TLP test data (Fig. 2b) show qualitatively consistent results for the effects of BDC, even though there are quantitative mismatches due to poor calibration. It should be noted that the practical usage of this methodology, controlling of BDC for ESD protection performances, is very limited because the junction breakdown voltage and the consequential operation voltage is strongly dependent on the BDC. That is to say, the high BDC over certain critical limit may guarantee the stable ESD protection performance in the EDNMOS device. However, the EDNMOS device with enhanced BDC can be adopted only in the limited range of the operation voltage because of its lowered junction breakdown voltage. Related mechanisms for the effects of the BDC can be clearly understood in terms the contour data of current density, electric field, and maximum temperature region as shown in Fig. 3. Upon the triggering of parasitic bipolar junction transistor (BJT) operation, a vertical directional U-shaped current path is formed between the drain N+ diffusion and the source N+ diffusion region. This is the situation in the 1st on-state, both in the EDNMOS with low BDC and in the EDNMOS with high BDC, before the characteristic double snapback occurs [8]. When higher current is applied to the EDNMOS with low BDC, the high electron injection induced base pushout occurs and a lateral directional deep electron channel is formed right under the gate to result in a low resistive and short current path between the source and the drain. The high electric field region, which designates the boundary of the base region, is shifted from the original HP-Well/ N-Drift boundary to the N-drift/N+ diffusion boundary.
163
As a result, high localized maximum temperature region appears at the surface of N-drift/N+ diffusion boundary. Exact matching between the site of high electric field and that of maximum temperature is clearly seen. The low resistive and short current path following the deep electron channel can explain the occurrence of the 2nd on-state with such a low on-resistance. The high electron injection induced base push-out and the consequential double snapback has been addressed in several publications [8–10]. The EDNMOS with high BDC never exhibits the base push-out even in the high current region. Thus, the initially formed U-shaped current conduction path is maintained until the thermal breakdown occurs. High electric region is stuck to the HP-Well/N-Drift boundary. The non-localized maximum temperature region is formed along the bottom directional HP-Well/N-Drift boundary. The nonlocalized property of maximum temperature region guarantees higher current immunity level under ESD stress. The TLP measurement data in Fig. 4 shows the I–V relations of the high BDC EDNMOS devices for various finger numbers. The non-uniformity of multi-finger triggering has been a critical problem to hinder the EDNMOS device from being adopted as ESD protection devices. It is generally accepted that uniform multi-finger triggering is guaranteed when the thermal breakdown voltage is larger than the BJT triggering voltage. Data in Fig. 2 shows that this uniformity condition is largely violated in the EDNMOS with low BDC. However, the EDNMOS with high BDC appears to satisfy the required uniformity condition. Thus, uniform multi-finger triggering is rather expected in the EDNMOS with high BDC. The TLP data in Fig. 4 shows that the thermal breakdown current (It2) of the EDNMOS device with high BDC generally increases when its finger number increases. The linearity of the thermal breakdown current upon increasing the finger number from 1 to 2 is relatively poor. This is because the drain site of the EDNMOS is commonly used upon increasing the finger number from 1 to 2. However, almost linear depen2.5 1x50um It2=460mA
Drain Current (A)
2.0
2x50um It2=610mA 4x50um It2=1210mA 6x50um It2=1650mA
1.5
8x50um It2=2230mA
1.0 0.5
Fig. 3. (a) Contours of current density, electric field, and local temperature for EDNMOS device with low BDC (HP-Well implant dose = 7.5 · 1012 cm 2 and N-Drift implant dose = 1.1 · 1013 cm 2). The contour data are obtained at the drain current level 4 mA/um. (b) for EDNMOS device with high BDC (HP-Well implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 1013 cm 2) at the drain current level 8 mA/um.
0.0 0
10 20 30 Drain Voltage (V)
40
Fig. 4. TLP measurement data on I–V relations of the high BDC (HPWell implant dose = 1.7 · 1013 cm 2 and N-Drift implant dose = 4.0 · 1013 cm 2) EDNMOS devices for various finger numbers. The thermal breakdown current levels (It2) for each finger number are shown in the inset.
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Y.-J. Seo, K.-H. Kim / Microelectronic Engineering 84 (2007) 161–164
dence of the current immunity level on the finger number is clearly seen upon increasing the finger number from 2 to 4, 6, or 8 ( Note that the 8-finger trigger efficiency against to 2-finger trigger efficiency is 91%). This suggests that the poor scaling behavior of the EDNMOS devices can also be cured by properly controlling their BDCs. The thermal breakdown current levels according to its finger numbers are listed in the inset of Fig. 4. 4. Conclusion The problematic strong snapback phenomenon and poor ESD protection performance of the EDNMOS device can be cured by properly controlling its background doping concentration (BDC). The EDNMOS with high BDC does not show the double snapback and remains within the 1st on-state. This implies that both the stable ESD protection performance and the low risk for the latchup problem can be realized in terms of the EDNMOS device by keeping its BDC sufficiently high. However, It should be noted that controlling its BDC for ESD protection application is practically of limited usage because the junction breakdown voltage is dependent on the BDC. Further achievements to overcome this limit are expected in the future works.
Acknowledgment This work was supported by Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2005-041-D00311). References [1] G. Bosselli, S. Meeuwsen, T. Mouthaan, F. Kuper, Proc. EOS/ESD Symp. (1999) 11–18. [2] M.P.J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker, W. Fichtner, IEEE Trans. Electron Dev. 47 (2000) 2128–2137. [3] B. Keppens, M.P.J. Mergens, C.S. Trinh, C.C. Russ, B.V. Camp, K.G. Verhaege, Proc. EOS/ESD Symp. (2004) 289–298. [4] C. Duvvury, F. Carvajal, C. Jones, D. Briggs, IEDM Tech. Dig. (1997) 375–378. [5] K. Kawamoto, S. Takahashi, S. Fujino, I. Shirakawa, IEEE Trans. Electron Dev. 49 (2002) 2047–2053. [6] V. Parthasarathy, V. Khemka, R. Zhu, J. Whitfield, R. Ida, A. Bose, IEEE Electron Dev. Lett. 23 (2002) 212–214. [7] B.C. Jeon, S.C. Lee, J.K. Oh, S.S. Kim, M.K. Han, Y.I. Jung, H.T. So, J.S. Shim, K.H. Kim, Proc. EOS/ESD Symp. (2002) 362–372. [8] M.D. Ker, K.H. Lin, IEEE Electron Dev. Lett. 25 (2004) 640–642. [9] S.M. Sze, Physics of Semiconductor Devices, second ed., Wiley, New York, 1981. [10] M. Streibl, K. Esmark, A. Sieck, W. Stadler, M. Wendel, J. Szatkowski, H. Goßner, Proc. EOS/ESD Symp. (2002) 73–82. [11] J.E. Barth, K. Verhaege, L.G. Henry, J. Richner, IEEE Trans. Electron. Packaging Manufact. 24 (2001) 99.