Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Microelectronics Journal 45 (2014) 239–248

Contents lists available at ScienceDirect

Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing Bibhash Sen a,n, Manojit Dutta a, Biplab K. Sikdar b a b

Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India Department of Computer Science and Technology, Bengal Engineering and Science University, Shibpur, India

art ic l e i nf o

a b s t r a c t

Article history: Received 25 May 2013 Received in revised form 8 November 2013 Accepted 14 November 2013 Available online 8 December 2013

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design. & 2013 Elsevier Ltd. All rights reserved.

Keywords: Quantum-dot cellular automata (QCA) Conservative logic Parity preserving logic Testability Nanotechnology

1. Introduction CMOS technology is reaching its limit beyond which further downscaling in feature size is impossible. High leakage current, high power density levels and high lithography cost crop up with further dimension scaling. One of the emerging nanotechnologies, the Quantum-dot Cellular Automata (QCA), is considered as a viable alternative to meet the energy efficient design target beyond the limit of existing CMOS technology [1,2]. The major advantages such as low power consumption, zero power dissipation in signal propagation, high speed and high compaction density of QCA based design have attracted researchers to investigate its visibility and implementation constraints. In VLSI circuits, parity checking techniques reduce the complexity of testing. The parity preserving logic gate, for which the parity of outputs matches with that of the inputs, when used with an arbitrary synthesis strategy for logic circuits, ensures detection of a fault at the primary outputs [3]. The testability feature provided by the existing parity preserving designs often takes the center stage, and the logical depth of a gate is ignored. Further, for testing such logic gate, an additional test logic circuit is considered without utilizing self testable feature. n

Corresponding author. Tel.: þ 91 3432754237. E-mail addresses: [email protected], [email protected] (B. Sen), [email protected] (M. Dutta), [email protected] (B.K. Sikdar). 0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.11.008

In QCA paradigm, wire-crossings are a major overhead [4,5]. Gates that are highly programmable ensure that the larger circuits can be synthesized with fewer number of gates, and thus also reduce the number of wire-crossings. Since majority gate (QCA primitive) itself is not functionally complete, various QCA logic gates such as majority with inverter (MI), CMVMIN (coupled majority minority) [6], UQCLG (universal QCA) [7], NNI (nandnor-inverter) [8], and AOI (and-or-inverter) [9] are conventionally used for realizing different QCA designs. The design and the fault tolerant capability of CMVMIN gate, reported in [10,11], are found to be acceptable. However, these gates do not have inherent fault detection or testing features. All these above factors motivate us to design a new logic gate that can find a trade off between the QCA design costs for test logic and programmability of primary outputs. Also, to continue with the present days' VLSI progress, we move forward for emerging nanotechnology which is desirable to overcome the challenges of feature size reduction and reliability. The major contribution of this work, around parity preserving QCA architecture, can be summarized as follows: (i) This work introduces a design methodology/framework in Quantum-dot cellular automata based on parity preserving logic. A new universal testable QCA logic gate termed as testable-QCA (t-QCA) is proposed. It is a 3
3 gate that realizes minority (min), majority (maj) and XNOR logic at its three primary outputs.

240

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

(ii) The flexibility of this multi-purpose logic gate enables synthesis of different logic circuits such as benchmark functions as well as arithmetic logic unit. Experimental results establish the effectiveness of the proposed logic and it outperforms the existing technologies in terms of design cost as well as testing overhead. (iii) Reliability issue in nano-circuit, the utmost necessity to overcome the high error rate, is addressed with the achievement of 100% fault coverage. (iv) The parity preserving property enables a t-QCA for concurrent detection of permanent and transient faults by comparing the parity of its inputs and outputs. A simple augmented testing circuit is also proposed, using QCA primitives, that functions as the cost effective comparator. (v) Finally, the flexibility and testability of parity preserving logic are revisited for nano-circuits. The paper is organized as follows. Section 2 deals with the basics of QCA. Section 3 provides related work on parity preserving circuits. Section 4 introduces the proposed design and evaluates the performance of t-QCA. High level logic synthesis with t-QCA is

reported in Section 5. Test evaluation of the t-QCA, subjected to all possible defects, is summarized in Section 6. Section 7 concludes the paper.

2. Preliminaries In QCA based design, a single device (QCA-cell) is used for construction of all the components of a circuit (computational elements and wires). The schematic diagram of a four-dot QCA cell is shown in Fig. 1(a). It contains four quantum dots positioned at the corners of a square and two free electron [2]. A quantum dot is a region where an electron is quantum-mechanically confined (Fig. 1(a)). The coulombic repulsion causes the classical model of electrons to occupy only the four corners of QCA cell, resulting either polarization P ¼ 1 (logic 0) or in P¼ þ1 (logic 1) as shown in Fig. 1(b). The basic structure realized in QCA is the 3-input majority gate, MV (A, B, C) ¼Maj (A, B, C) ¼AB þ BC þ CA (Fig. 1(c)). The majority gate can also function as a 2-input AND or a 2-input OR by fixing one of the three input cells to P¼  1 or P¼ þ1 respectively.

Fig. 1. (a) QCA cell, (b) QCA cell with two different polarizations, (c) majority voter, (d) inverter, (e) co-planar wire-crossing, (f) multilayer wire-crossing and (g) clocking.

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

Inversion can be done within the QCA wire by slightly offcentering the wire. It is realized in two different orientations as shown in Fig. 1(d). In QCA, two kinds of QCA wire-crossing are possible, the coplanar (Fig. 1(e)) and multilayer (Fig. 1(f)). The coplanar wire crossing in QCA requires cells in two different orientations, a 901 (
-cell) and a 451 (þ-cell) whereas multilayer wire crossing can be realized with the cells of single orientation. Timing/synchronization in QCA is accomplished by the cascaded clocking of four distinct and periodic phases (Fig. 1(g)). The clock provides the power required for functioning of the QCA [12]. In the first (switch) phase of clocking, the tunneling barrier between two dots of a QCA cell starts to rise. This is the phase during which computation takes place. The second (hold) phase is reached when the tunneling barriers are high enough to prevent electrons from tunneling. In the third (release) phase, barrier falls from high to low. The final phase (relax) of clocking ensures there is no inter dot barrier and the cell remains unpolarized.

3. Related work Ensuring reliability of devices via parity checking is very much desirable due to its low overhead for storage as well as interconnect. In [13], a novel fault tolerant architecture of majority logic around QCA is proposed. It is effective for high performance logic component design. Design capability/flexibility of QCA design structure is further extended by proposing a 5-input majority gate in [14]. Recently, a QCA circuit with high capability of reconfigurability is presented in [15] to design various boolean logic required for instruction set architecture. On the other hand, most of the research work with the target to design testable logic around QCA employ conservative logic such as Fredkin [16], CQCA [17] and MX-qca [18] gate. A conservative logic gate has equal number of 1 s in its output and the input and, therefore, parity preserving [19]. A Fredkin gate (Fig. 2(a)) has two-level majority voter (MV) implementation and it requires 6 MVs and four clocking zones. Although the Fredkin gate is a universal gate, it is very difficult to build a large circuit solely with the Fredkin gates [19]. Further, its fault coverage under single missing cell and additional cell deposition defect is also very poor [17]. In [20], concurrently testable FPGA design for molecular QCA is proposed around Fredkin gate. In [21], the conservative reversible logic based on Fredkin gate is used to design concurrently testable sequential circuits. It enables concurrent detection of single missing/additional cell defects model or the unidirectional faults. However, it is not suitable for detection of the bidirectional multiple faults. In [22], a methodology for the concurrent error detection in reversible logic circuits is reported. It can result in multi-bit error at the outputs. This methodology is based on the inverse property of reversible logic and garbage-less but it incurs the cost for inversion and compare logic. The CQCA (Fig. 2(b)) and MX-qca (Fig. 2(c)) are better than the Fredkin gate in terms of complexity (number of majority voter), speed and area. The CQCA [23] can be implemented with single level MV and requires only two MVs. In order to check the parity mismatch in CQCA, a majority voter (D) for input vector and a minority voter (S) for the output vector are needed. A 2-pair 2-rail

241

checker is required for testing the D and S. It makes the testing logic more complex. The MX-qca gate requires four clocking zones and five majority gates [18]. The above discussion points to the fact that the cost effective design of a parity preserving gate, satisfying the design capability as well as the testability (like DFT, BIST) requires proper investigation.

4. Universal testable QCA (t-QCA) logic gate Coupling majority and minority (CMVMIN) function together enables area saving implementation of complex logic [10]. Fault tolerant capability of CMVMIN architecture is also investigated in [11]. In this section, we explore the parity preserving logic in the majority–minority architecture and introduce the self testable logic gate (named t-QCA). The input-to-output mapping of t-QCA is: P¼AB þBC þCA, Q ¼ A′B′ þ B′C′ þ C′A′, R ¼ ðA  B  CÞ, where A, B, C are inputs and P, Q, R are the outputs (Fig. 3). The truth table of t-QCA is shown in Table 1. It shows the parity preserving nature of t-QCA i.e., the input–output parity is preserved (A  B  C ¼ P  Q  R). Two possible coplanar QCA implementations of the proposed t-QCA gate are shown in Fig. 4(a) and (b). The first implementation is single-layered coplanar implementation using three 3-input Majority gates and three NOT gates. The second one is the single layered coplanar implementation using one 5-input Majority gate proposed in [24], one 3-input Majority gate and three NOT gates. We also present a multilayered representation of the same in Fig. 4(c). The multilayered design is highly efficient as it utilizes lesser area compared to that of single layered designs. It requires one 5-input majority gate, one 3-input majority gate and three NOT gates. The simulation results of the proposed implementation of t-QCA are shown in Fig. 5. Since the majority logic is quite susceptible to missing cell deposition (when the cells are placed in substrate) [9], non-fully populated (NFP) tile based logic primitives are used in designing QCA circuits [25]. Also, enlarging the central section (logic device cells) of the majority tiles, robustness of such circuit can be

Fig. 3. Testable-QCA gate.

Table 1 Truth table. A

B

C

P

Q

R

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

1 1 1 0 1 0 0 0

1 0 0 1 0 1 1 0

Fig. 2. Different conservative gates.

242

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

Fig. 4. QCA implementation of t-QCA gate. (a) Coplanar QCA implementation of t-QCA-I, (b) coplanar QCA implementation of t-QCA-II, (c) multilayer QCA implementation of t-QCA-III.

improved [24]. On the other hand, simple arrangement in the clocking zones makes tiles a viable design technique for QCA. The robustness of the proposed t-QCA is achieved by applying proper clocking mechanism to all the majority gate. All the inputs to 3-input majority gate are placed in clock-zone 1, the middle or device cell is placed in clock-zone 2 and the final output is in clockzone 3 (Fig. 4(a) and (b)). A comparative study on the proposed t-QCA gate and the existing conservative gates in terms of gate count, cell count, area and clock delay is reported in Table 2. The analysis of the results reported in the table depicts that the multilayer implementation

of t-QCA is the most efficient one in terms of QCA design metrics. It requires 44 QCA cells as compared to the 116 cells needed in coplanar structure. The multilayer t-QCA gate covers a minimal area of 0:04 μm2 . Further, delay is reduced to two clock zones in the proposed multilayer structure. It is to be noted that, at present CQCA gate is considered to be the most efficient QCA-implementation among all the existing conservative gates. It requires two clock zones. In small scale, two or four clock zones will not make much difference in performance. The gain induced by reducing a number of clock zones is meaningful for larger circuits. The t-QCA (multilayer) is as efficient as

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

0

1000

2000

3000

243

4000

5000

6000

max: 1.00e+00 A min: −1.00e+00 max: 1.00e+00 B min: −1.00e+00 max: 1.00e+00 C min: −1.00e+00 max: 9.33e− 01 P min: −9.33e−01 max: 9.35e−00 Q min: −9.35e−01 max: 9.51e−01 R min: −9.51e−01 Fig. 5. Simulation of t-QCA.

Table 2 Comparison of t-QCA and existing conservative gates. Conservative gates

#MVs

Table 4 Performance of t-QCA gate in programmability.

Cell count

3-ip

Clock zones

Area (μm2)

5-ip

Fredkin [16] 6 MX-qca [18] 5 CQCA[17] 2 t-QCA-I 3 t-QCA-II 1 t-QCA-III 1 3-ip ¼3 input, 5-ip¼ 5 input

0 0 0 0 1 1

246 218 117 113 116 44

5 4 2 4 4 2

0.37 0.35 0.11 0.12 0.11 0.04

Control bit -

C¼0

Circuit ↓

P

CQCA A Fredkin A MX-qca AB Proposed t-QCA AB 6 Functions: AND, OR,

Parameter Fredkin

Standard functions ↓

# Gate

1.F¼ ABC 2.F ¼ AB 3.F ¼ ABCþ AB′C′ 4.F ¼ ABCþ A′B′C′ 5.F ¼ ABþ BC 6.F ¼ ABþ A′B′C 7.F¼ ABC þA′BC′þ AB′C′ 8.F ¼ A 9.F ¼ ABþ BC þCA 10.F ¼AB þB′C 11.F¼ ABþ BC þ A′B′C′ 12.F¼ ABþ A′B′ 13.F ¼ABC þ A′B′Cþ AB′C′ þA′BC′ Total Improvement (%)

2 1 3 4 2 5 6 1 5 1 6 2 3 41 7.3

CQCA # Clk. 8 4 12 12 8 16 16 4 16 4 16 8 12 136 57.35

# Gate 2 1 3 6 2 5 6 1 1 3 6 4 3 43 11.62

Q

R

P

# Primitive functions Q

R

AB A′B A A þB A′þB A′B AB A A þB A′þB AB′ B AB A þB 1 A′þB′ ðA  BÞ′ A þB A′B′ AB NOR, NAND, XOR, XNOR; Improvement ¼

2 2 2 6 66.66%

Table 5 Performance of parity preserving gates implementing full adder.

Table 3 Performance of t-QCA in realizing standard functions. Logic gate -

C¼ 1

Fredkin

MX-qca

CQCA

t-QCA

3 7 66 71.4

1 2 – –

t-QCA # Clk. 4 2 4 8 4 8 6 2 2 4 8 6 4 62 6.89

# Gate

# Clk.

2 1 2 8 2 6 6 1 1 4 2 1 2

4 2 4 8 4 8 8 2 2 6 4 2 4

38 –

58 –

# Gate 5 3 Clock delay 22 14 # Gate Impv. % 80 66 # Clock Impv. % 90.90 85.7 Impv.¼ Improvement No inverter is considered during gate count

CQCA gate. The effectiveness of t-QCA is further established in realizing the standard benchmark functions. Benchmark function implementation: Any 3-input boolean functions can be converted into one of the 13 standard functions [9,26]. Table 3 reports the gate count and the number of clock zones required to realize the standard function with t-QCA, Fredkin and CQCA gate. To realize the 13 standard functions, in total, the t-QCA requires 13.16% less number of gates and 6.89% less clock zones than the CQCA.

5. Logic synthesis with t-QCA that of CQCA while considering delays (clock zones). However, it is evident from Table 2 that multilayer t-QCA is more efficient as it requires almost 63% less QCA cells and 64% less area than the

Evaluation of the performance of a logic device also includes the analysis of programmability, that is, the number of logical

244

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

Fig. 6. (a) Implementation of ALU with t-QCA, (b) ALU block, (c) different ALU function.

calculations that can be produced as primary outputs. Although the main objective of this work is to develop a logic device with better testability, we simultaneously try to ensure realization of maximum number of logical functions around it. The proposed t-QCA can be utilized as a programmable logic gate with one select input (C). It then realizes six logical functions AND, OR, XOR, NAND, NOR and Ex-NOR. Thus evaluates 66.66% improvement in programmability (Table 4). It can be observed that the existing conservative gates provide much fewer logical calculations/functions (each can be programmed to produce only two logical calculations at their primary outputs) than the t-QCA (Table 4). The feature significantly reduces the design cost. This is established by designing a simple full adder. The t-QCA realizes full adder at its primary outputs by inverting its third output. Whereas a CQCA-based full adder requires three times more gates and two times more clock zones than that of the t-QCA-based adder (Table 5). The capability of logic synthesis of t-QCA is further extended through implementation of ALU. It consists of different combinational circuits such as adder and multiplexer (Fig. 6(a)). All the basic operations of ALU are realized with the three control variables (S0 ; S1 ; S2 ). A comparative study is shown in Table 6. It is evident that the t-QCA-based ALU requires 25% lesser number of gates and overall 16.67% lesser clock-delay than the CQCA based ALU. Moreover, as the t-QCA requires 62.39% less cell count and covers 63.63% lesser area than the CQCA, in logic level (Table 2), the t-QCA based ALU has much lesser cell-count and area-coverage than the CQCA-based ALU design.

Table 6 t-QCA based ALU design cost. Design

# Gate

Clock delay

CQCA þNOT t-QCAþ NOT Improvement (%)

16 12 25

12 10 16.67

6. Testing and fault coverage High fault coverage of a design is desirable during manufacturing test. The techniques such as design for test (DFT) and automatic test pattern generation target to improve the fault efficiency/coverage of a logic design. 6.1. Stuck-at fault coverage In this section, the testability of proposed t-QCA gate is evaluated for stuck-at faults. The test vectors, all 0 s {000} (Fig. 7 (b)) and all 1 s {111} (Fig. 7(a)) generate the output at P, Q, R as {011} and {100} in a fault free design having hamming weight difference of 1, where P and Q are always complementary 〈0; 1〉 and 〈1; 0〉 respectively, and R is complement of input C (See Fig. 7). Faults at primary inputs: The outputs corresponding to test vector 000 and 111 are 011 and 100 respectively (Table 7). If any input(s) is stuck-at 1, the output corresponding to the test vector 000 yields an output different from 011. For e.g., consider input

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

245

Fig. 7. (a) Stuck-at 0 fault detection and (b) Stuck-at 1 fault detection.

Table 7 Test mode. A

B

C

P

Q

R

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 1 1 1

1 1 1 0 1 0 0 0

1 0 0 1 0 1 1 0

Table 8 Stuck-at fault characterization. I/O

Fault type

Test vector ABC

E-output PQR

F-output PQR

111 000 111 000 111 000 111 000 111 000 000 111

100 011 100 011 100 011 100 011 011 100 011 100

101 010 101 010 101 010 000 111 001 110 010 101

stuck-at faults s-a-0 010 s-a-1 010 s-a-0 010 s-a-1 010 s-a-0 110 s-a-1 110 s-a-0 111 s-a-1 000 s-a-0 000 s-a-1 000 s-a-0 110 s-a-1 110 s-a-0 000 s-a-1 000 s-a-0 111 s-a-1 000

010 010 010 010 101 101 100 011 011 011 101 101 011 011 100 011

011 101 011 101 010 010 011 100 001 111 100 111 010 111 000 111

Single stuck-at faults A s-a-0 A s-a-1 B s-a-0 B s-a-1 C s-a-0 C s-a-1 P s-a-0 P s-a-1 Q s-a-0 Q s-a-1 R s-a-0 R s-a-1 Multiple AB AB BC BC AC AC ABC ABC PQ PQ QR QR PR PR PQR PQR

Fault coverage of 〈000, 111〉 ¼ 71.42%. Fault coverage of 〈010, 110〉 ¼28.57%. Fault coverage of 〈000,111,010, 110〉 ¼ 100%. E-Output ¼ Expected Output. F-Output ¼Faulty Output.

A is stuck-at 1. The output corresponding to test vector 000 is now 010, and not 011, and thus the fault is detectable. Again, if all three inputs are stuck-at 1, the output corresponding to the test vector

Fig. 8. Modeling QCA layout of proposed t-QCA.

000 yields an output different from 011. Thus any single input stuck-at 1 fault and 1 multiple faults are detectable using test vector 000 (see Table 8). A similarly, for stuck-at 0 at the input lines is found to be detectable with the test vector 111. Faults at primary outputs: The outputs P, Q, and R (011/100) each have complimentary values for the two test cases (0/1 for P, 1/0 for Q, and 1/0 for R, corresponding to 000/111, respectively). A stuck-at fault at any of the outputs would result in the same value to appear at the output for both the test cases, rendering the fault detectable. Further investigation, as shown in Table 8, proves that all the single output stuck-at faults can also be detected using the two test vectors {000, 111} by observing the parity mismatch between the test-vector and the faulty output pattern. The above discussion points to the fact that the test-vector set {000, 111} can detect all the single stuck-at faults with 100% fault coverage and few multiple stuck-at faults at inputs and outputs resulting an overall 71.41% fault coverage for all type of stuck-at faults. For 100% stuck-at fault coverage, we need two additional test vectors {010, 110}. It is evident from Table 8 that the four test vectors {000, 010, 110, 111} can detect all the multiple stuck-at faults at both inputs and outputs. For example, in the case of stuck-at-0 at the inputs A and B the test vector 000 results in a faulty output pattern of 011 which is same as that of a fault free case and cannot detectable by 000. But, in such a faulty case the test vector 010 results in an output 011 (in this case it is faulty), the fault becomes detectable.

246

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

Table 8 reports the test vectors and the corresponding faulty output patterns that result in parity mismatch. It shows that every multiple stuck-at fault at the inputs and outputs becomes detectable by the test-vector set {000, 010, 110, 111}. 6.2. Cell deposition defect coverage of coplanar t-QCA In QCA manufacturing, defects can occur during the synthesis and deposition phases, although defects are most likely to take place during the deposition phase [27]. Researchers have shown that QCA cells are more susceptible to missing and additional QCA cell defects. To investigate the cell deposition defects coverage, the QCA layout of the t-QCA gate is represented with hardware description language notations, using the HDLQ Verilog library [28]. The HDLQ design tool, verilog counterpart for QCA, consists of a Verilog HDL

library of QCA devices, i.e., MV, INV, fan-out, crosswire (CW), L-shape wire with fault injection capability. The HDLQ modeled design of the t-QCA gate is shown in Fig. 8. An exhaustive testing of the HDLQ model is conducted with the eight input patterns in the presence of all possible single missing/ additional cell defect in majority voters (MJs), INVs, FOs, CWs, and L-shape wires (LSs). The design is simulated using the Verilog HDL simulator. This generates 19 unique fault patterns at the outputs (Table 9). In Table 9, ai is the 3-bit pattern with an equivalent decimal value of i. For example, a1 represents 001 (decimal 1). From the fault simulation results, we note that six of the fault patterns (1, 2, 3, 17, 18, 19) make the proposed t-QCA gate untestable when the test vector a0, a7 is applied. These fault patterns correspond to the modules FO1, FO2, FO3, CW1, CW2, CW3, MJ1, MJ2, MJ3 in the HDLQ layout (Fig. 8) of the t-QCA

Table 9 Fault pattern in t-QCA gate (1 to 19). Values

Fault pattern

IV

EV

1

2

3

4

5

6

7

8

9

10

11

12

13

a0 a1 a2 a3 a4 a5 a6 a7

a3 a2 a2 a5 a2 a5 a5 a4

a3 a5 a5 a5 a2 a2 a2 a4

a3 a5 a2 a2 a5 a5 a2 a4

a3 a2 a5 a2 a5 a2 a5 a4

a7 a7 a7 a0 a7 a0 a0 a0

a2 a2 a2 a4 a3 a5 a5 a5

a2 a2 a3 a5 a2 a4 a5 a5

a2 a3 a5 a2 a5 a2 a4 a5

a2 a3 a2 a5 a2 a5 a4 a5

a2 a2 a2 a2 a1 a7 a2 a5 a3 a2 a2 a2 a2 a1 a7 a2 a5 a3 a3 a2 a5 a2 a0 a6 a3 a5 a5 a4 a5 a5 a2 a7 a1 a4 a5 a5 a3 a2 a2 a5 a0 a6 a3 a2 a2 a4 a5 a2 a5 a7 a1 a4 a2 a2 a5 a2 a5 a5 a7 a1 a4 a5 a5 a5 a5 a5 a5 a6 a0 a5 a2 a4 IV¼ Input, EV ¼ Expected output, FC¼ Fault coverage; Average fault

Fig. 9. Three different layers of multilayered t-QCA.

14

15

16

17

18

19

a3 a3 a3 a3 a2 a3 a4 a4 a3 a3 a5 a4 a5 a5 a4 a4 coverage is

FC% 68.42 57.89 68.42 63.16 63.16 68.42 47.37 68.42 63.15

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

circuit. Therefore, to make the design testable using only these two test vectors (a0, a7) we can replace these modules with their faulttolerant counterparts. Such fault-tolerant counterparts of Fan-outs, Cross-wires, Majority-voters and L-Shaped wires are reported in the literature [11,29], and found to be effective for the current device to achieve 100% fault coverage using the proposed vectors. The shaded boxes in Fig. 8 represent the modules that are to be Table 10 Missing cell fault characterization. Missing cell position

Layer 1 B4 B8 C4 C7 C8 D4 D7 E2 E3 E4 E5 E6 E7 F4 F6 G4 G7 G8 H8 Layer 2 B4 E2 D6 G4 Layer 3 B3 B4 B5 C5 D1 D2 D3 D4 D5 D6 E1 E5 E7 F5 G3 G4 G5

Output

247

replaced by their fault-tolerant counterparts for achieving 100% fault coverage with all 0 s and all 1 s vectors for all single missing/ additional cell defects of conservative logic based QCA circuits design around the proposed t-QCA gate, using all 0 s and 1 s test vectors. Therefore, conservative logic based QCA circuits, toward the QCA layout of t-QCA gate shown in Fig. 8, can be tested by all 0 s and all 1 s test vectors while considering the single missing/ additional cell defects. 6.3. Cell deposition defect coverage of multilayer t-QCA

Test vector ABC

Expected o/p PQR

Faulty o/p PQR

010

P

Q

R

MV MV B MIN MV B MV C C X MV MV MIN B MV B MIN MV MIN

MIN MIN B′ MIN MIN B′ MIN C′ C′ X MIN MIN MIN B′ MV B′ MIN MV MIN

A (S)′ X (S)′ (S)′ X (S)′ X X X (S)′ (S)′ (S)′ X (S)′ X (S)′ (S)′ (S)′

000

000 010 111 010 000 111 000

011 Faultfree 010 011 Faultfree 010 Faultfree 011 010 010 Faultfree Faultfree 011 010 100 010 011 100 011

MV MV MV MV

MIN MIN MIN MIN

A B MIN MV

000 000 001 000

011 011 010 011

010 010 011 010

MV MIN MIN MIN MV MV MV MV MV MV MV MV MV MV MV MV MV

MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN MIN

A (S)′ X X B (S)′ X X X C B X (S)′ X′ C MV C

000 000 000 000 000

011 011 011 011 011 Faultfree 010 010 011 011 011 010 Faultfree 010 011 011 011

010 111 111 111 010

010 000 010 000 001 010

010 010 000 000 000 010 010 000 000 000

101 111 101 010 101 101

111 101 110 101 111 110 111

011 011 010 010 010 011 011 010 010 010

MV¼ ABþ BC þ CA, MIN¼A′B′þB′C′þ A′C’, S ¼ A  B  C, X¼ MV-like function, X’¼ MIN-like function.

In this section, we investigate the single missing cell defect coverage in the proposed multilayered t-QCA gate. Different layers of the multilayered t-QCA (Fig. 4(c)) are shown in Fig. 9. To identify the possible missing cell defect, all the cells in a layer are marked as their grid position, e.g. the cell present just below the input cell A in layer 1 is marked as grid position B4 (Bth row and 4th Column). All the cell positions are noted in Table 10. We choose the QCADesigner [30] platform for simulation as no such HDLQ tool for multilayer QCA architecture is available. The defective function for the structure is characterized in Table 10. The possible 40 missing cell defects are identified. Here, we only consider the single missing-cell defect. In Table 10, first two columns present the missing cell position and its corresponding faulty output, whereas the rest three columns specify the test vector to detect the fault. For example, the missing cell at position B4 results the MV, MIN and A as its three primary outputs. To detect this fault, a test vector 000 is applied. It finds parity mismatch between the expected (011) and faulty outputs (010) and, therefore, the fault is detectable. Similarly, all the induced faults, due to missing cells can be detected considering suitable test vectors. These are reported in Table 10. Synthesis of test logic circuit: The careful analysis of the results of Table 10 indicates that, for missing cells at positions C7, E7, F6, G7, G8, H8, B4, B5 and C5, the fault-induced outputs at P, Q are the same. However, these are expected to be complementary in a fault-free state. A test logic circuit (Fig. 10(a)) is built to detect all these faults. In the test logic, two intermediate logic values, S and Ti, are generated. If a circuit is faulty (P, Q are same) Ti becomes 1 otherwise, Ti ¼ 0. Thus, the faults due to the missing cells at these positions can be detected at the output Ti ¼ PQ and the fault can be propagated to the final output terminal of the test circuit by setting T ¼1 (faulty). In all the other positions where the outputs P and Q are complementary to each other (even in the presence of faults), such faults cannot be detected at Ti (¼0). So, output at PQ is not sufficient to detect such faults. To detect all such faults, we need to compare the faulty output R with S ¼ A  B  C (output of xor1 logic). In the test mode, a fault free circuit sets S ¼R and that leads to output of xor2 as 0. The fault-free and the fault-induced output patterns are shown in Table 11 for the missing cell at position B4. It is evident from Table 11 that the faulty R and S become complementary to each other. It results in xor2 output as

Fig. 10. (a) Test logic, (b) equivalent QCA test circuit.

248

B. sen et al. / Microelectronics Journal 45 (2014) 239–248

Table 11 Fault pattern and its corresponding test vector for missing cell at i position B4. IP ABC

OP PQR

FOP PQR

Fault-free R

Faulty R

S

TV

000 001 010 011 100 101 110 111

011 010 010 101 010 101 101 100

010 010 010 100 011 101 101 101

1 0 0 1 0 1 1 0

0 0 0 0 1 1 1 1

1 0 0 1 0 1 1 0

000

011 100

111

IP¼ Input pattern, OP¼ Expected output pattern, FOP ¼Faulty output pattern, S ¼ A  B  C.

Table 12 Design specifications and simulation settings of QCADesigner. Specifications

Coplanar Arch.-I

Coplanar Arch.-II

Multilayer Arch.

Gate used Area Cell count Cell size Dot diameter Cell separation Simulation engine Radius of effect Layer separation

3-Input MV 0.12 μm2 114

3&5 Input MV 3&5 Input MV 0.11 μm2 0.04 μm2 116 44 18 nm
18 nm 5 nm 2 nm Bistable approximation 65 nm 11.5 nm

1 and sets T ¼1. It can be further observed that in test mode four test vectors: {000, 001, 010, 111} are required to detect all the missing cell defects in t-QCA. The test logic for t-QCA is shown in Fig. 10(a). Fig. 10(b) is the QCA implementation of the test logic. In a fault free case, the output T¼ 0 and T ¼1 signifies the presence of fault. Fig. 10(a) describes the functions of the test block under missing cell at position B4. The test-vector 111 is applied at the inputs A, B, C. The expected outputs at P, Q, R are 1, 0, 0 but the faulty outputs 1, 0, 1. It is evident that such fault can easily be detected by the proposed test logic. Due to the faulty output 101, S becomes 0 which is different from R and the T becomes 1. The design specifications and simulation set up of the QCADesigner for the current design and experimentation are given in Table 12.

7. Conclusion This paper proposes a QCA logic gate (t-QCA) based on parity preserving logic that is highly programmable (66.66% improvement) as well as testable. The t-QCA gate outperforms the most popular logic gates in terms of high level logic synthesis and fault coverage. The number of test vectors to detect all possible stuckat-faults (only four vectors) as well as single missing/additional cell defects (only two test vectors, all 0 s and all 1 s) for coplanar t-QCA is reduced. For single missing cell defect in complex multilayer QCA architecture (not explored earlier), the number of test vectors is also four. A simple augmented testing circuit is then proposed, using QCA primitives (majority voters), as a simple parity checker to extend the testing domain in nanotechnology.

References [1] ISCAS, IEEE International Symposium on Circuit and Systems, QCA: A Promising Research Area for CAS Society, 2004. [2] C.S. Lent, P.D. Tougaw, W. Porod, G.H. Bernstein, Quantum cellular automata, Nanotechnology 4 (1993) 49–57. [3] B. Parhami, Fault-tolerant reversible circuits, in: Fortieth Asilomar Conference on Signals, Systems and Computers, 2006. ACSSC'06, 2006, pp. 1726–1729. http://dx.doi.org/10.1109/ACSSC.2006.355056. [4] W. Chung, B. Smith, S.-K. Lim, QCA physical design with crossing minimization, in: 5th IEEE Conference on Nanotechnology, 2005, vol. 1, 2005, pp. 108–111. http://dx.doi.org/10.1109/NANO.2005.1500704. [5] S.-H. Shin, J.-C. Jeon, K.-Y. Yoo, Wire-crossing technique on quantum-dot cellular automata, in: NGCIT2013, the 2nd International Conference on Next Generation Computer and Information Technology, vol. 27, September 22–24, 2013, pp. 52–57. [6] S. Ditti, P. Bhattacharya, P. Mitra, B. Sikdar, Logic realization with coupled QCA majority-minority gate, in: Proceedings of 12th IEEE VLSI Design and Test Symposium, 2008. [7] B. Sen, M. Mohapatra, M. Dalui, B. K. Sikder, Introducing universal QCA logic gate for synthesizing symmetric functions with minimum wire-crossings, in: Proceedings of ACM ICWET, Mumbai, India, February 2010. [8] B. Sen, B. K. Sikder, Characterization of universal NAND-NOR-inverter QCA gate, in: Proceedings of 11th IEEE VLSI Design and Test Symposium, Kolkata, India, August, 2007, pp. 433–442. [9] M. Tahoori, J. Huang, M. Momenzadeh, F. Lombardi, Characterization, test and logic synthesis of AND-OR-inverter AOI gate design for QCA implementation, IEEE TCAD 24 (2005) 1881–1893. [10] S. Ditti, K. Mahata, P. Mitra, B.K. Sikdar, Defect characterization in coupled majority-minority qca gate, in: 4th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2009. DTIS '09, 2009, pp. 293–298. [11] M. Dalui, B. Sen, B.K. Sikdar, Fault tolerant QCA logic design with coupled majority-minority gate, Int. J. Comput. Appl. 1 (2010) 81–87. [12] V. Vankamamidi, M. Ottavi, F. Lombardi, Clocking and cell placement for QCA, in: Sixth IEEE Conference on Nanotechnology, 2006, vol. 1, 2006, pp. 343–346. [13] R. Farazkish, S. Sayedsalehi, K. Navi, Novel design for quantum dots cellular automata to obtain fault-tolerant majority gate, J. Nanotechnol. 2012 (2010) 1–8. [14] K. Navi, S. Sayedsalehi, R. Farazkish, M.R. Azghadi, Five-input majority gate, a new device for quantum-dot cellular automata, Int. J. Comput. Theor. Nanosci. 7 (2010) 1–8. [15] K. Navi, A. Roohi, S. Sayedsalehi, Designing reconfigurable quantum dot cellular automata logic circuits, Int. J. Comput. Theor. Nanosci. 10 (2013) 1–10. [16] E. Fredkin, T. Toffoli, Conservative logic, Int. J. Theor. Phys. 21 (1982) 219–253. [17] H. Thapliyal, N. Ranganathan, Conservative QCA gate (CQCA) for designing concurrently testable molecular QCA circuits, in: 22nd International Conference on VLSI Design VLSID '09, 2009, pp. 511–516. URL 〈http://dx.doi.org/10. 1109/VLSI.Design.2009.75〉. [18] H. Thapliyal, N. Ranganathan, S. Kotiyal, Design of testable reversible sequential circuits, in: IEEE Transactions on Very Large Scale Integration Systems (VLSI), 2012. [19] G. Swaminathan, J. Aylor, B. Johnson, Concurrent testing of VLSI circuits using conservative logic, in: Proceeding of the International Conference Computer Design, Cambridge, MA, 1990, pp. 60–65. [20] H. Thapliyal, N. Ranganathan, Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate, in: IEEE International Symposium on Circuits and Systems, 2009, ISCAS 2009, 2009, pp. 1815–1818. http:// dx.doi.org/10.1109/ISCAS.2009.5118130. [21] H. Thapliyal, N. Ranganathan, Reversible logic-based concurrently testable latches for molecular QCA, IEEE Trans. Nanotechnol. 9 (2010) 62–69. [22] H. Thapliyal, N. Ranganathan, Reversible logic based concurrent error detection methodology for emerging nanocircuits, in: 10th IEEE Conference on Nanotechnology (IEEE-NANO), 2010, 2010, pp. 217–222. http://dx.doi.org/10. 1109/NANO.2010.5697743. [23] N. Ranganathan, H. Thapliyal, Conservative logic gate for design of quantum dot cellular automata circuits, US patent 7880496 b1, 2011. [24] R. Akkela, M.D. Wagh, A five-input majority gate in quantum-dot cellular automata, NSTI-Nanotech, 2011, 2011, pp. 13–16. URL 〈http://www.nsti.org〉. [25] J. Huang, M. Momenzadeh, L. Schiano, M. Ottavi, F. Lombardi, Tile-based QCA design using majority-like logic primitives, J. Emerg. Technol. Comput. Syst. 1 (2005) 163–185. [26] R. Zhang, K. Walus, W. Wang, G.A. Jullien, A method of majority logic reduction for quantum cellular automata, Trans. Nanotechnol. 3 (2004) 443–450. [27] M.B. Tahoori, J. Huang, M. Momenzadeh, F. Lombardi, Testing of quantum cellular automata, IEEE Trans. Nanotechnol. 3 (December) (2004) 432–442. [28] M. Ottavi, L. Schiano, F. Lombardi, F. Lombardi, HDLQ: A HDL environment for QCA design, ACM J. Emerg. Technol. 2 (October) (2006) 243–261. [29] A. Fijany, B. Toomarian, New design for quantum dots cellular automata to obtain fault tolerant logic gates, Int. J. Nanopart. Res. 3 (2001) 27–37. [30] K. Walus, T. Dysart, G.A. Jullien, R. Budiman, QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata, Trans. Nanotechnol. 3 (2004) 26–29.