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Failure Analysis enhancement by evaluating the Photoelectric Laser Stimulation impact on mixed-mode ICs
Microelectronics Reliability 48 (2008) 1529–1532
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Failure Analysis enhancement by evaluating the Photoelectric Laser Stimulation impact on mixed-mode ICs M. Sienkiewicz a,b,*, P. Perdu a, A. Firiti b, K. Sanchez a, O. Crepel b, D. Lewis c a
CNES – French Space Agency, 18, Avenue Edouard Belin, 31401 Toulouse, France Freescale Semiconductor France SAS, 134, Avenue Général Eisenhower, 31023 Toulouse, France c IMS, Université de Bordeaux 1, 33405 Talence, France b
a r t i c l e
i n f o
Article history: Received 10 July 2008
a b s t r a c t The mixed-mode ICs (Integrated Circuits), by involving multiple functions (digital, analog, RF, power) inside one device, are becoming more compact and useful. At the same time, their developments and Failure Analysis (FA) are more and more complex: test, diagnostic and defect localization steps are harder and longer in time. Each step needs to be improved as far as defect localization is concerned. Several techniques based on emission microscopy, electron beam, direct probing or laser stimulation have been developed and introduced to follow these ICs evolutions. The most recent evolution in the laser stimulation field has been the introduction of several dynamic laser stimulation techniques aimed to localize defects or weakness regions inside functional but failing ICs (environmental marginalities related to temperature, frequency, voltage, etc.). This paper deals with the use of dynamic photoelectric laser stimulation techniques applied on mixed-mode ICs where the major difficulty is due to their considerable intrinsic sensitivity. Indeed, the analog circuitry is more sensitive than the digital circuitry since a slight change in an electrical parameter can trigger a functionality failure. This property limits the defect localization because of the complex interpretation of the results, the laser stimulation mapping. We propose to help the failure analyst by coupling the dynamic laser stimulation mapping with the photoelectric impact simulations run on a previously analyzed structure. The goal is to predict and interpret the laser sensitivity mapping so to isolate the defective areas in the analog devices. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Laser stimulation techniques are very efficient. They have been commonly used for a long time in failure analysis laboratories, principally for defects localization in ICs. Two wavelengths are generally employed to produce the desired phenomena in silicon-based chips: approximately 1300 nm for Thermal Laser Stimulation (TLS) and 1064 nm for Photoelectric Laser Stimulation (PLS). TLS, by locally heating the ICs structures, introduces resistivity changes and Seebeck effect. The change in the electric properties allows an investigation of the resistive anomalies [1]. PLS, by locally inducing a photocurrent into the active area of the device allows the localization of junction related issues [2–4]. Using these two wavelengths it is possible to localize the defect from the front side or from the backside of the integrated circuits. Being the silicon relatively transparent to these wavelengths in the near infrared, IC’s active regions can be stimulated thought the silicon substrate after a short substrate preparation (thinning by polish* Corresponding author. Address: CNES – French Space Agency, 18, Avenue Edouard Belin, 31401 Toulouse, France. E-mail address: [email protected] (M. Sienkiewicz). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.060
ing) [5]. Those methodologies have been initially applied with grate success on failed ICs with ‘‘hard” defects. The devices with this kind of failures are electrically activated in static mode (i.e. OBIRCh, OBIC, TIVA, LIVA, etc.). Dynamic Laser Stimulation techniques (e.g. DLS [6,7], LADA [8], RIL [9], SDL [10]) are an evolution of the static laser stimulation techniques. They have been introduced to improve the analysis of the devices with abnormal functionality or with marginality (commonly called soft defect). Indeed, this kind of methodologies allows defect localization on dynamically activated digital circuits: the laser stimulation is used to switch the functionality from pass to fail or from fail to pass (Fig. 1). The energy delivered through thermal or photoelectric laser stimulation alters the IC behavior and functionality. Fine control and selection of environmental parameters (e.g. electric, temperature) and laser stimulation source allows the localization of the areas responsible for the anomalies on the functionality. Those methodologies are now commonly used on digital circuits with soft defects. However, the analog circuits are much more sensitive to the laser stimulation. The laser stimulation applied on ICs with or without defects results in a complex mapping image (Fig. 2). Hence, the use of dynamic laser stimulation techniques is generally limited or,
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M. Sienkiewicz et al. / Microelectronics Reliability 48 (2008) 1529–1532
Fig. 3. Principle of delay variation mapping technique.
Fig. 1. Dynamic laser stimulation setup. The functional test result is synchronized with the laser scanning.
variable time shift appears between the trigger signal, which is synchronized with the laser beam position (x, y), and one of the output signals. This delay is converted into a voltage signal with a time to amplitude converter (TAC) module and then sent to the imaging system. This parametric technique allows precise measurements of the signal delay and so it is better suited for analog or mixed-mode circuits analysis. 3. D-PLS simulation 3.1. Photocurrent effect in MOSFET transistors
Fig. 2. Example of dynamic thermal laser stimulation mapping on the mixed-mode device. Only one sensitive area is related to the defect while the others are not defective.
if possible, avoided by the analyst. This is particularly true for PLS. Nevertheless, the photoelectric laser stimulation analysis through pass/fail approach or through parametric approach [11,12] can be advantageously used to localize design weakness or junction related anomalies in digital and analog structures. To face the critical challenge of analog chips failure analysis, we propose to use the simulation and modeling of PLS phenomena coupled with the D-PLS mapping. The demonstration will be done through the signatures analysis of the 1064 nm laser source impact on elementary structures commonly used in mixed-mode devices. The goal is to highlight the circuitry sensitivity through PLS mapping and to better understand the electrical behavior of the complex mixed-mode ICs. This will be done through the study of elementary structures. This paper explains our analysis approach through the correlation of electrical simulation on elementary structures and dynamic laser stimulation performed through timing analysis [11].
In the Fig. 4 we can see the model of a NMOS transistor implanted on a p-type silicon substrate. There are two P–N junctions: one between the source and the substrate and another between the drain and the substrate. Hence, there are two space charge regions (SCR). When the PLS technique is applied we can observe the generation of free carriers in the silicon substrate. Some of the free carriers will be separated and collected into the SCR, so that the photocurrents injection will take place. The intensity and the repartition of these photocurrents depend on the transistor biasing and its characteristics (material, doping, structure geometry, etc.). Indeed, when the transistor is activated, the drain voltage increases together with the space charge zone near the drain, as its junction is reverse biased. In consequence the drain photocurrent intensity is modulated by the drain potential when the source photocurrent collected is constant. Therefore, the additional current in the drain will increase, the substrate current will decrease and the source current will stay stable. Fig. 5 shows a first degree model of the NMOS transistor submitted to PLS. The activation time and duration of the two presented current sources are linked to the laser excitation parameters. In Fig. 6 it is shown a PMOS transistor. It is implanted in a Ndoped well on the P silicon substrate. There is an additional contact named bulk to bias the well. The transistor is biased as follows: the
2. Dynamic photoelectric laser stimulation setup We decided to study the delay of the output signal introduced by a 1064 nm wavelength laser scanning our analog structure. The appropriated technique used for the simulations and measurements was Dynamic Variation Mapping (DVM) [11]. The DVM technique setup is represented in Fig. 3. When the device, in functional conditions, is scanned by 1064 nm wavelength laser, a slight
Fig. 4. NMOS transistor cross section with additional current flows due to PLS.
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M. Sienkiewicz et al. / Microelectronics Reliability 48 (2008) 1529–1532
nected to the 0 V potential. Due to the current flow, there will be two natural major P–N junctions: the first between the base and the collector, the second between the substrate and the base. Therefore, the additional current sources modeling the PLS impact are I1, and I2. 4. Current mirror analysis 4.1. Simulation Fig. 5. First degree model of the NMOS transistor submitted to PLS.
Fig. 6. PMOS transistor cross section with additional current flow due to PLS.
substrate is at 0 V, the bulk is connected to the source and has a positive potential (4 V), the gate and the drain potentials vary between a positive potential (4 V) and 0 V. There is an important P–N junction of well due to the natural reverse bias. During the normal functioning there is a voltage difference between substrate and bulk. Hence, there is a big SCR which surrounds the transistor. The separation and collection of the free carriers will take place there. Therefore, under PLS we will observe a high current flowing between the bulk and substrate contacts. This current will be much higher than the one flowing in the drain or in the source contacts. The main current will modify the bulk potential by reducing it. An electrical model of this behavior is shown in Fig. 7. We have to specify that this behavior is limited at ICs technology based on P substrate. Fig. 8 shows a physical model of a PNP bipolar transistor taking account of an additional photocurrent injected when it is scanned with 1064 nm laser source. The collector and the substrate are con-
Fig. 7. First degree model of the PMOS transistor submitted to PLS.
Base
Collector
The current mirror is one of the basic analog structures which are frequently used in analog or mixed-mode devices. By basing the study on PNP transistors working principles, the structure presented in Fig. 9 was simulated. The emitter lengths of both the transistors Q1 and Q2 were fixed at 3.5 lm. R0 and R1 resistors value were fixed at 1 kX. In this type of structure the key parameters are the input and output currents. However, these currents strongly depend on the OUT node voltage which is much easier to measure. Hence, we will focus on this voltage for measurements and simulations. Fig. 10 shows a physical model of the bipolar transistor Q1, extracted from the previous schematic, and taking into account an additional photocurrent injected into the device under test (DUT). The same current sources will be present in Q0 when this transistor is scanned with the 1064 nm laser source. When the simulations were ran, only three current sources were activated for both the transistor Q1 and for the transistor Q0 when they were scanned. The electrical setup was chosen such that the bipolar transistors operated in their linear zone. We assumed that the highest current source is I1, followed by I2 and finally by I3, whose impact is the weaker. The current values were based on experimental results. The voltage supply Vsup equals 2 V for static analysis. For dynamic analysis a square wave signal of 2 V and 25 kHz was applied on the Vsup node. All simulations were ran at room temperature. Regarding the current flows previously shown in Fig. 10, the following results were obtained. When the transistor Q1 was under PLS, the total current consumption was IVsup = 51.29 lA. At the same time the voltage level on the OUT node changed so to have a variation: DVout = jVout Vout0 j = 12.2 mV, where Vout0 is the voltage on
Fig. 9. Electrical schematic of the PNP based current mirror.
Base
Emitter
Collector
Emitter
+
N I1
I2
P
P
P Substrate Fig. 8. Model of the PNP bipolar transistor under PLS.
R0
N
P
I2 I1
P I2
P Substrate Fig. 10. Model of the Q1 PNP bipolar transistor under PLS.
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M. Sienkiewicz et al. / Microelectronics Reliability 48 (2008) 1529–1532
REF
No PLS
Q0
When the voltage level is higher, the PLS mapping is clearer. Similarly, when the voltage level is lower, the PLS mapping is darker. In Fig. 13 the white colour corresponds to the transistor Q0. Regarding the transistor Q1, the simulated delay was shorter and in Fig. 13 this transistor is described by the black colour.
Q1 5. Conclusions Fig. 11. Simulation results in time domain for the current mirror structure under PLS.
Uncovered Base fragment Q1 Q0
Fig. 12. PLS results by using DVM technique.
No PLS Q0
Δt [ps]
Δt ~ V V↑ white V↓ black
Q1 Fig. 13. DVM results correlation with the simulation.
the OUT node when the selected device is under PLS (here Q1). Similarly, when the transistor Q0 was under PLS, the total current consumption was IVsup = 51.27 lA and the voltage level on the OUT node changed so to have a variation: DVout = 12.19 mV. By increasing the laser power, we expect more higher variations on IVsup and DVout. However, for a fixed laser power the variation on the Vsup voltage level will induce different repartition of additional current flows (I1, I2, I3). The results of the dynamic analysis are represented in Fig. 11. The transistor Q0 is more sensitive to PLS than Q1. Moreover, for both the bipolar transistors Q0 and Q1, the rising edge is more sensitive to PLS then the falling edge. 4.2. Experimental results The PLS was applied from the front side of the analyzed structure. The setup was chosen as for the electrical simulation. Fig. 12 represents the DVM results where a rising edge of the OUT signal was observed. A part of both the transistors was masked by metal layer and so the analysis was handicapped. However, the correlation between the simulation and DVM results can be done. The most sensitive areas from Fig. 12 correspond to the bases of transistors Q0 and Q1, uncovered by the metal layer. We remind that the base current was the higher one when the simulation was run. Fig. 13 shows the correlation between PLS mapping results and the simulation presented before (Figs. 10 and 11). The delay, proportional to the voltage level, is longer for the transistor Q0.
The purpose of the photoelectric laser stimulation in the FA context is the capability to localize junction defects and also soft defects (IC performances limited by environment, temperature, voltage, etc.). In addition to this phenomena, a 1064 nm laser, by introducing additional photocurrent, can changes the device functionality. This effect is especially visible and measurable on the analog or mixed-mode devices where a small variation in current of one device can have an important impact on another device and so on (e.g. current mirror). These elements make PLS mapping results hard to analyze. Considering the above simulations we could see that even if the analog structure does not contain a defect, it can be photoelectricsensitive. The aim of the proposed simulations is to predict the way and the intensity of the variation induced by the Dynamic Photoelectric Laser Stimulation. The accurate values of these variations can be obtained only by the measurement on the selected structures. The D-PLS mapping coupled with simulations is a very good way to predict the laser sensitivity and, finally, to isolate the defective regions related to a defect. As function of the analyzed product and available time it is possible to use a more or less complex illuminated (1064 nm) model for each internal element. A first level model can easily predict the ways of variations (positive or negative), but is not adapted to have a good value of the amplitude or delay variation induced by the laser. The main advantage is that this kind of model is easier and faster to implement and use. On the contrary, it is possible to have a very fine model by using experimental measurements on test structures. The prediction of the laser stimulation will be improved, but the implementation and the use of this model could take a long time. Acknowledgements We would like to thank the following people at Freescale Semiconductor for their valuable input: P. Sandrez, N. Jarrige, P. Besse and A. Boivin for design support, A. Clark for his useful remarks. Special thanks go to F. Infante from CNES for reviewing this paper. References [1] Nikawa K, Inoue S. International symposium for testing and failure analysis, ISTFA; 1996. p. 387–92. [2] Wilson T. Microelectron Eng 1987;7:297–307. [3] Fritz J, Lackman R. Microelectron Eng 1990;12:381–8. [4] Stevens KC, Wilson TJ. Microelectron Eng 1990;12:397–404. [5] Beaudoin F et al. New non-destructive laser ablation based on backside sample preparation method. Microelectron Reliab 2000;40:1425–9. [6] Beaudoin F et al. From static thermal and photoelectric laser stimulation (TLS/ PLS) to dynamic laser testing. Microelectron Reliab 2003;43(9–11):1681–6. [7] Beaudoin F et al. Dynamic laser stimulation case studies. Microelectron Reliab 2005;45:1538–43. [8] Rowlette JA et al. Critical timing analysis in microprocessors using near-IR laser assisted device alteration (LADA). ITC 2003:264–73. [9] Cole Jr EI et al. Resistive interconnection localization. IEEE – International physical and failure analysis of integrated circuits (IPFA) 2002. [10] Bruce Michael R et al. Soft defect localization (SDL) on ICs. ISTFA 2002:21–7. [11] Sanchez K et al. Delay variation mapping induced by dynamic laser stimulation. IEEE 2005:305–11. [12] Falk RA et al. New application of thermal laser signal injection microscopy (TLSIM). ISTFA 2003:25–35.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Failure Analysis enhancement by evaluating the Photoelectric Laser Stimulation impact on mixed-mode ICs M. Sienkiewicz a,b,*, P. Perdu a, A. Firiti b, K. Sanchez a, O. Crepel b, D. Lewis c a
CNES – French Space Agency, 18, Avenue Edouard Belin, 31401 Toulouse, France Freescale Semiconductor France SAS, 134, Avenue Général Eisenhower, 31023 Toulouse, France c IMS, Université de Bordeaux 1, 33405 Talence, France b
a r t i c l e
i n f o
Article history: Received 10 July 2008
a b s t r a c t The mixed-mode ICs (Integrated Circuits), by involving multiple functions (digital, analog, RF, power) inside one device, are becoming more compact and useful. At the same time, their developments and Failure Analysis (FA) are more and more complex: test, diagnostic and defect localization steps are harder and longer in time. Each step needs to be improved as far as defect localization is concerned. Several techniques based on emission microscopy, electron beam, direct probing or laser stimulation have been developed and introduced to follow these ICs evolutions. The most recent evolution in the laser stimulation field has been the introduction of several dynamic laser stimulation techniques aimed to localize defects or weakness regions inside functional but failing ICs (environmental marginalities related to temperature, frequency, voltage, etc.). This paper deals with the use of dynamic photoelectric laser stimulation techniques applied on mixed-mode ICs where the major difficulty is due to their considerable intrinsic sensitivity. Indeed, the analog circuitry is more sensitive than the digital circuitry since a slight change in an electrical parameter can trigger a functionality failure. This property limits the defect localization because of the complex interpretation of the results, the laser stimulation mapping. We propose to help the failure analyst by coupling the dynamic laser stimulation mapping with the photoelectric impact simulations run on a previously analyzed structure. The goal is to predict and interpret the laser sensitivity mapping so to isolate the defective areas in the analog devices. Ó 2008 Elsevier Ltd. All rights reserved.
1. Introduction Laser stimulation techniques are very efficient. They have been commonly used for a long time in failure analysis laboratories, principally for defects localization in ICs. Two wavelengths are generally employed to produce the desired phenomena in silicon-based chips: approximately 1300 nm for Thermal Laser Stimulation (TLS) and 1064 nm for Photoelectric Laser Stimulation (PLS). TLS, by locally heating the ICs structures, introduces resistivity changes and Seebeck effect. The change in the electric properties allows an investigation of the resistive anomalies [1]. PLS, by locally inducing a photocurrent into the active area of the device allows the localization of junction related issues [2–4]. Using these two wavelengths it is possible to localize the defect from the front side or from the backside of the integrated circuits. Being the silicon relatively transparent to these wavelengths in the near infrared, IC’s active regions can be stimulated thought the silicon substrate after a short substrate preparation (thinning by polish* Corresponding author. Address: CNES – French Space Agency, 18, Avenue Edouard Belin, 31401 Toulouse, France. E-mail address: [email protected] (M. Sienkiewicz). 0026-2714/$ - see front matter Ó 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2008.07.060
ing) [5]. Those methodologies have been initially applied with grate success on failed ICs with ‘‘hard” defects. The devices with this kind of failures are electrically activated in static mode (i.e. OBIRCh, OBIC, TIVA, LIVA, etc.). Dynamic Laser Stimulation techniques (e.g. DLS [6,7], LADA [8], RIL [9], SDL [10]) are an evolution of the static laser stimulation techniques. They have been introduced to improve the analysis of the devices with abnormal functionality or with marginality (commonly called soft defect). Indeed, this kind of methodologies allows defect localization on dynamically activated digital circuits: the laser stimulation is used to switch the functionality from pass to fail or from fail to pass (Fig. 1). The energy delivered through thermal or photoelectric laser stimulation alters the IC behavior and functionality. Fine control and selection of environmental parameters (e.g. electric, temperature) and laser stimulation source allows the localization of the areas responsible for the anomalies on the functionality. Those methodologies are now commonly used on digital circuits with soft defects. However, the analog circuits are much more sensitive to the laser stimulation. The laser stimulation applied on ICs with or without defects results in a complex mapping image (Fig. 2). Hence, the use of dynamic laser stimulation techniques is generally limited or,
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M. Sienkiewicz et al. / Microelectronics Reliability 48 (2008) 1529–1532
Fig. 3. Principle of delay variation mapping technique.
Fig. 1. Dynamic laser stimulation setup. The functional test result is synchronized with the laser scanning.
variable time shift appears between the trigger signal, which is synchronized with the laser beam position (x, y), and one of the output signals. This delay is converted into a voltage signal with a time to amplitude converter (TAC) module and then sent to the imaging system. This parametric technique allows precise measurements of the signal delay and so it is better suited for analog or mixed-mode circuits analysis. 3. D-PLS simulation 3.1. Photocurrent effect in MOSFET transistors
Fig. 2. Example of dynamic thermal laser stimulation mapping on the mixed-mode device. Only one sensitive area is related to the defect while the others are not defective.
if possible, avoided by the analyst. This is particularly true for PLS. Nevertheless, the photoelectric laser stimulation analysis through pass/fail approach or through parametric approach [11,12] can be advantageously used to localize design weakness or junction related anomalies in digital and analog structures. To face the critical challenge of analog chips failure analysis, we propose to use the simulation and modeling of PLS phenomena coupled with the D-PLS mapping. The demonstration will be done through the signatures analysis of the 1064 nm laser source impact on elementary structures commonly used in mixed-mode devices. The goal is to highlight the circuitry sensitivity through PLS mapping and to better understand the electrical behavior of the complex mixed-mode ICs. This will be done through the study of elementary structures. This paper explains our analysis approach through the correlation of electrical simulation on elementary structures and dynamic laser stimulation performed through timing analysis [11].
In the Fig. 4 we can see the model of a NMOS transistor implanted on a p-type silicon substrate. There are two P–N junctions: one between the source and the substrate and another between the drain and the substrate. Hence, there are two space charge regions (SCR). When the PLS technique is applied we can observe the generation of free carriers in the silicon substrate. Some of the free carriers will be separated and collected into the SCR, so that the photocurrents injection will take place. The intensity and the repartition of these photocurrents depend on the transistor biasing and its characteristics (material, doping, structure geometry, etc.). Indeed, when the transistor is activated, the drain voltage increases together with the space charge zone near the drain, as its junction is reverse biased. In consequence the drain photocurrent intensity is modulated by the drain potential when the source photocurrent collected is constant. Therefore, the additional current in the drain will increase, the substrate current will decrease and the source current will stay stable. Fig. 5 shows a first degree model of the NMOS transistor submitted to PLS. The activation time and duration of the two presented current sources are linked to the laser excitation parameters. In Fig. 6 it is shown a PMOS transistor. It is implanted in a Ndoped well on the P silicon substrate. There is an additional contact named bulk to bias the well. The transistor is biased as follows: the
2. Dynamic photoelectric laser stimulation setup We decided to study the delay of the output signal introduced by a 1064 nm wavelength laser scanning our analog structure. The appropriated technique used for the simulations and measurements was Dynamic Variation Mapping (DVM) [11]. The DVM technique setup is represented in Fig. 3. When the device, in functional conditions, is scanned by 1064 nm wavelength laser, a slight
Fig. 4. NMOS transistor cross section with additional current flows due to PLS.
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M. Sienkiewicz et al. / Microelectronics Reliability 48 (2008) 1529–1532
nected to the 0 V potential. Due to the current flow, there will be two natural major P–N junctions: the first between the base and the collector, the second between the substrate and the base. Therefore, the additional current sources modeling the PLS impact are I1, and I2. 4. Current mirror analysis 4.1. Simulation Fig. 5. First degree model of the NMOS transistor submitted to PLS.
Fig. 6. PMOS transistor cross section with additional current flow due to PLS.
substrate is at 0 V, the bulk is connected to the source and has a positive potential (4 V), the gate and the drain potentials vary between a positive potential (4 V) and 0 V. There is an important P–N junction of well due to the natural reverse bias. During the normal functioning there is a voltage difference between substrate and bulk. Hence, there is a big SCR which surrounds the transistor. The separation and collection of the free carriers will take place there. Therefore, under PLS we will observe a high current flowing between the bulk and substrate contacts. This current will be much higher than the one flowing in the drain or in the source contacts. The main current will modify the bulk potential by reducing it. An electrical model of this behavior is shown in Fig. 7. We have to specify that this behavior is limited at ICs technology based on P substrate. Fig. 8 shows a physical model of a PNP bipolar transistor taking account of an additional photocurrent injected when it is scanned with 1064 nm laser source. The collector and the substrate are con-
Fig. 7. First degree model of the PMOS transistor submitted to PLS.
Base
Collector
The current mirror is one of the basic analog structures which are frequently used in analog or mixed-mode devices. By basing the study on PNP transistors working principles, the structure presented in Fig. 9 was simulated. The emitter lengths of both the transistors Q1 and Q2 were fixed at 3.5 lm. R0 and R1 resistors value were fixed at 1 kX. In this type of structure the key parameters are the input and output currents. However, these currents strongly depend on the OUT node voltage which is much easier to measure. Hence, we will focus on this voltage for measurements and simulations. Fig. 10 shows a physical model of the bipolar transistor Q1, extracted from the previous schematic, and taking into account an additional photocurrent injected into the device under test (DUT). The same current sources will be present in Q0 when this transistor is scanned with the 1064 nm laser source. When the simulations were ran, only three current sources were activated for both the transistor Q1 and for the transistor Q0 when they were scanned. The electrical setup was chosen such that the bipolar transistors operated in their linear zone. We assumed that the highest current source is I1, followed by I2 and finally by I3, whose impact is the weaker. The current values were based on experimental results. The voltage supply Vsup equals 2 V for static analysis. For dynamic analysis a square wave signal of 2 V and 25 kHz was applied on the Vsup node. All simulations were ran at room temperature. Regarding the current flows previously shown in Fig. 10, the following results were obtained. When the transistor Q1 was under PLS, the total current consumption was IVsup = 51.29 lA. At the same time the voltage level on the OUT node changed so to have a variation: DVout = jVout Vout0 j = 12.2 mV, where Vout0 is the voltage on
Fig. 9. Electrical schematic of the PNP based current mirror.
Base
Emitter
Collector
Emitter
+
N I1
I2
P
P
P Substrate Fig. 8. Model of the PNP bipolar transistor under PLS.
R0
N
P
I2 I1
P I2
P Substrate Fig. 10. Model of the Q1 PNP bipolar transistor under PLS.
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M. Sienkiewicz et al. / Microelectronics Reliability 48 (2008) 1529–1532
REF
No PLS
Q0
When the voltage level is higher, the PLS mapping is clearer. Similarly, when the voltage level is lower, the PLS mapping is darker. In Fig. 13 the white colour corresponds to the transistor Q0. Regarding the transistor Q1, the simulated delay was shorter and in Fig. 13 this transistor is described by the black colour.
Q1 5. Conclusions Fig. 11. Simulation results in time domain for the current mirror structure under PLS.
Uncovered Base fragment Q1 Q0
Fig. 12. PLS results by using DVM technique.
No PLS Q0
Δt [ps]
Δt ~ V V↑ white V↓ black
Q1 Fig. 13. DVM results correlation with the simulation.
the OUT node when the selected device is under PLS (here Q1). Similarly, when the transistor Q0 was under PLS, the total current consumption was IVsup = 51.27 lA and the voltage level on the OUT node changed so to have a variation: DVout = 12.19 mV. By increasing the laser power, we expect more higher variations on IVsup and DVout. However, for a fixed laser power the variation on the Vsup voltage level will induce different repartition of additional current flows (I1, I2, I3). The results of the dynamic analysis are represented in Fig. 11. The transistor Q0 is more sensitive to PLS than Q1. Moreover, for both the bipolar transistors Q0 and Q1, the rising edge is more sensitive to PLS then the falling edge. 4.2. Experimental results The PLS was applied from the front side of the analyzed structure. The setup was chosen as for the electrical simulation. Fig. 12 represents the DVM results where a rising edge of the OUT signal was observed. A part of both the transistors was masked by metal layer and so the analysis was handicapped. However, the correlation between the simulation and DVM results can be done. The most sensitive areas from Fig. 12 correspond to the bases of transistors Q0 and Q1, uncovered by the metal layer. We remind that the base current was the higher one when the simulation was run. Fig. 13 shows the correlation between PLS mapping results and the simulation presented before (Figs. 10 and 11). The delay, proportional to the voltage level, is longer for the transistor Q0.
The purpose of the photoelectric laser stimulation in the FA context is the capability to localize junction defects and also soft defects (IC performances limited by environment, temperature, voltage, etc.). In addition to this phenomena, a 1064 nm laser, by introducing additional photocurrent, can changes the device functionality. This effect is especially visible and measurable on the analog or mixed-mode devices where a small variation in current of one device can have an important impact on another device and so on (e.g. current mirror). These elements make PLS mapping results hard to analyze. Considering the above simulations we could see that even if the analog structure does not contain a defect, it can be photoelectricsensitive. The aim of the proposed simulations is to predict the way and the intensity of the variation induced by the Dynamic Photoelectric Laser Stimulation. The accurate values of these variations can be obtained only by the measurement on the selected structures. The D-PLS mapping coupled with simulations is a very good way to predict the laser sensitivity and, finally, to isolate the defective regions related to a defect. As function of the analyzed product and available time it is possible to use a more or less complex illuminated (1064 nm) model for each internal element. A first level model can easily predict the ways of variations (positive or negative), but is not adapted to have a good value of the amplitude or delay variation induced by the laser. The main advantage is that this kind of model is easier and faster to implement and use. On the contrary, it is possible to have a very fine model by using experimental measurements on test structures. The prediction of the laser stimulation will be improved, but the implementation and the use of this model could take a long time. Acknowledgements We would like to thank the following people at Freescale Semiconductor for their valuable input: P. Sandrez, N. Jarrige, P. Besse and A. Boivin for design support, A. Clark for his useful remarks. Special thanks go to F. Infante from CNES for reviewing this paper. References [1] Nikawa K, Inoue S. International symposium for testing and failure analysis, ISTFA; 1996. p. 387–92. [2] Wilson T. Microelectron Eng 1987;7:297–307. [3] Fritz J, Lackman R. Microelectron Eng 1990;12:381–8. [4] Stevens KC, Wilson TJ. Microelectron Eng 1990;12:397–404. [5] Beaudoin F et al. New non-destructive laser ablation based on backside sample preparation method. Microelectron Reliab 2000;40:1425–9. [6] Beaudoin F et al. From static thermal and photoelectric laser stimulation (TLS/ PLS) to dynamic laser testing. Microelectron Reliab 2003;43(9–11):1681–6. [7] Beaudoin F et al. Dynamic laser stimulation case studies. Microelectron Reliab 2005;45:1538–43. [8] Rowlette JA et al. Critical timing analysis in microprocessors using near-IR laser assisted device alteration (LADA). ITC 2003:264–73. [9] Cole Jr EI et al. Resistive interconnection localization. IEEE – International physical and failure analysis of integrated circuits (IPFA) 2002. [10] Bruce Michael R et al. Soft defect localization (SDL) on ICs. ISTFA 2002:21–7. [11] Sanchez K et al. Delay variation mapping induced by dynamic laser stimulation. IEEE 2005:305–11. [12] Falk RA et al. New application of thermal laser signal injection microscopy (TLSIM). ISTFA 2003:25–35.