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Field plate related reliability improvements in GaN-on-Si HEMTs
Microelectronics Reliability 52 (2012) 2153–2158
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Field plate related reliability improvements in GaN-on-Si HEMTs A. Chini a,⇑, F. Soci a, F. Fantini a, A. Nanni b, A. Pantellini b, C. Lanzieri b, D. Bisi c, G. Meneghesso c, E. Zanoni c a
Department of Information Engineering, University of Modena and Reggio Emilia, 41125 Modena, Italy SELEX Sistemi Integrati S.p.A, 00131 Roma, Italy c Department of Information Engineering, University of Padova, 35131 Padova, Italy b
a r t i c l e
i n f o
Article history: Received 3 June 2012 Received in revised form 18 June 2012 Accepted 18 June 2012 Available online 9 July 2012
a b s t r a c t State of the art GaN on Silicon HEMTs fabricated with and without a field-plate structure have been tested by means of DC and RF reliability tests. The introduction of the field-plate structure greatly improves device reliability both during DC as well as RF testing. Results are thus suggesting that reliability in NOFP and FP devices is mainly limited by the high electric fields within the device structure causing an increase in traps concentration. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction GaN HEMTs devices are of great interest for the development of high RF power applications thanks to their outstanding performance when compared to other semiconductor based solutions. While their superior performances [1] have been repeatedly assessed by several authors, the factors limiting their performance and reliability are still under investigation. Concerning the effects of adding a field-plate structure on the device reliability, Vetury et al. [2] showed how the use of a dualgate (i.e. similar to a field-plate) structure to GaN-on-SiC HEMTs resulted to be effective in improving device reliability suggesting that device degradation is strongly affected by the strength of the peak electric-field in the gate–drain access region. Medjdoub et al. [3] have shown reliability results on field-plated GaN on Silicon HEMT with an excellent stability in their DC characteristics but with a small degradation of their pulsed performance after DC bias stress tests. Similarly, an increase in drain current-collapse after RF stress tests was also observed by Lee et al. [4] on GaNon-SiC HEMTs and was attributed to an increase in electron trapping phenomena. Generally, adding a field-plate structure has thus yielded improvements or state-of-the-art reliability results for GaN HEMTs devices. Nevertheless, to the best of the authors knowledge, a side-by-side comparison between FP and NOFP devices fabricated on the same wafer including RF stress tests, traps characterization and assessment by means of numerical simulations of the physical mechanisms involved in FP and NOFP devices degradation has not yet been presented. In this paper the authors would like to show some experimental and numerical results that are emphasizing the benefits that can be ⇑ Corresponding author. Tel.: +39 059 2056164. E-mail address: [email protected] (A. Chini). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.040
obtained in terms of reliability when a field-plate contact is implemented within the device structure and give some insights in the degradation mechanisms involved. Results obtained both during DC and RF testing are strongly suggesting that the factors limiting devices reliability are related to the increase in material traps concentration due to high electric fields which are known [5] to be mitigated by adopting a fieldplate structure. 2. Device fabrication Coplanar Waveguide (CPW) technology has been adopted to fabricate at SELEX S.I. the active devices reported in this work, employing an AlGaN/GaN hetero-junction grown on a 4 in. HighResistivity Silicon (1 1 1) substrate with q > 7 kX cm and about 525 lm thickness. Ohmic contact resistance value of RC = 0.27 X mm has been obtained with a Ti/Al/Ni/Au metal stack followed by a Rapid Thermal Annealing (RTA) optimized for this substrate. After a Silicon Nitride (SiN) deposition, gate window was opened trough the SiN layer by means of a CF4 based dry-etch. Gate Foot was then fabricated by means of a Ni/Pt metal stack self-aligned evaporation. A thermal treatment has been applied in order to improve device reliability: by annealing the AlGaN surface below the gate contact AlGaN surface damage introduced by dry-etch can be effectively removed. The benefits obtained are appreciable in terms of barrier height and ideality factor values before (UB = 0.9 eV, n = 1.7) and after (UB = 1.16 eV, n = 1.37) the treatment. In order to reduce Gate sheet resistance, a thick Au metallization (Gate Head) has been evaporated as specified below. In particular, two different gate technologies have been applied. On the first half wafer, the same Gate Foot lithography has been replicated to maintain the I-Gate shape; on the other half wafer, an LGHead 3LGFoot has been introduced in order to attain a field-plate with a
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C-Gate shape. This has been aligned with the Gate Foot at the Source side, and bend out about LFP = 2LGFoot toward Drain contact. This wafer partitioning is mandatory to ensure the best comparison between FP and no-FP technologies thanks to the same epistructure and fabrication process. Gate passivation, and electroplating to define interconnect metallization, completed the wafer process for the coplanar technology. Fabricated devices yielded state-of-the-art RF performance for the FP structure reaching power densities of 10.6 W/mm at RT, CW operation at 2.5 GHz and VDS = 60 V. Other typical devices parameters are summarized as follows: 1 mA/mm breakdown voltage was 65 V and 120 V for NOFP and FP devices, respectively; RF power gains and peak PAE at RT under 2.5 GHz CW operation were approximately 13 dB/50% and 12 dB/60% for NOFP and FP devices, respectively. 3. Short Time Stress Test (STST) A preliminary assessment of the devices has been obtained by means of Short Time Stress test (STST) which have been carried out at two different operating conditions. A first experiment was carried out in order to evaluate the effect of reverse-biasing applied to the gate junction. Step-stress experiment was carried out by reverse-biasing the gate terminal with voltage levels starting from VG = 4 V and decreasing VG by 1 V every 100 s. Both source and drain terminal were grounded during the applied stress test. After each step, an ID vs VGS characteristics was measured at VDS = 1 for the evaluation of device VTH. As can be seen in Fig. 1, both FP and NOFP devices are experiencing similar threshold voltage shifts during the applied stress test. Moreover, threshold voltage starts to change appreciably after the step at VG = 6 V, it experiences the maximum variation in the VG = 6 V to 10 V range, and keeps decreasing up to VG = 20 V. The observed threshold voltage shift did not recover even after device storage at RT for more than two weeks, and appeared to be rather stable even when subsequent measurements (i.e. DC or pulsed output characteristics) were carried out. Although further characterization of the observed threshold voltage shift might be needed in order to fully understand the physical phenomena involved, we found it to be very similar to what already observed from Ma et al. [6] on fluorine-implanted enhancement-mode AlGaN/GaN high electron mobility transistors. In [6] a negative threshold voltage shift is observed as a consequence of hot-electrons interaction with fluorine ions implanted in the AlGaN barrier. In our case, although devices were depletion-mode, a fluorine ions incorporation within the AlGaN barrier might happen due to the CF4 based SiN dry-etch used for the gate-window opening. Thus, in our case, the threshold voltage shift might still be promoted by the interac-
Fig. 1. Cumulative device threshold voltage shift induced by reverse-biasing the gate junction. Threshold voltage is extracted from ID vs VGS measurements carried out at VDS = 1 V.
tion of hot-electrons and incorporated fluorine ions given the strong dependence observed of the threshold voltage shift from the reverse bias applied to the gate junction. A second experiment was also carried out in on-state operating condition where a VDS = 40 V, 50 V and 60 V Drain Bias is applied for 1 h at IDS = 30% of saturation current (IDSS) in successive steps. Devices used for this test were preliminary subjected to DC IV characterization which induced an approximately 0.6 V negative shift in devices threshold voltage in order to avoid its effects on the experiment findings. The STST results during the stress on FP and NOFP devices are reported in Fig. 2A and B and their results can be summarized as follows: NOFP devices are showing a slight decrease in both ID and IG values during the applied STST and are failing when biased at VDS = 60 V. On the other hand FP device are showing a very stable behavior during the VDS = 40 and 50 V steps in terms of drain currents while gate currents are not showing a monotonous trend. During the stress at VDS = 60 V drain current is showing a slight decrease in its value while a significant gate current decrease is observed. Results obtained from STST experiments can thus be summarized as follows: (i) a reverse gate-bias applied to a fresh device induces a negative VTH shift for both FP and NOFP devices; (ii) onstate STST experiments show a more stable behavior of FP devices when compared to NOFP ones; (iii) on-state STST experiment at VDS = 60 V for FP device and at VDS = 40 V and, more pronounced, at VDS = 50 V for NOFP devices are showing a slight decrease of DC drain current levels as well as a significant decrease in gate current levels. 4. RF stress tests at 2.5 GHz Finally, 4 50 lm gate periphery devices were also subjected to on-wafer CW RF stress tests carried out at 2.5 GHz. Three NOFP and three FP devices were subjected to the RF stress and the results that follows refers to typical results obtained for a NOFP and a FP devices. Said devices were subjected to a preliminary characterization measurements set which included DC and pulsed IV characterization as well as drain current transient recorded at different temperatures. The investigations are aimed at the analysis of trap-
Fig. 2. Drain and gate current variation during the on-state STST test on NOFP (a) and FP (b) devices.
A. Chini et al. / Microelectronics Reliability 52 (2012) 2153–2158
ping phenomena limiting device performances and/or reliability. The threshold voltage shift was ‘‘induced’’ by repeating several time DC and pulsed-IV characterizations until its variation across repeated measurements vanished. For both FP and No-FP RF stress the following parameters were used: VDS = 30 V and IDS = 5% of IDSS; 90 °C base-plate temperature; input and output matching conditions were US = 0\0° and UL = 0.78\5° respectively. Input available power levels were chosen in order to operate both FP and No-FP at a 3 dB compression point which corresponds to a 4.8 W/mm and 3.5 W/mm output power for the FP and NOFP devices, respectively. For both FP and NOFP devices gate bias currents were always negative during device operation proving that gate diodes were not significantly turned on during device operation. A 98 K/W thermal resistance was also extracted by means of numerical simulations. As a consequence, junction temperatures during the applied RF stress were approximately 135 °C and 125 °C for FP and NOFP devices, respectively. Stress results are depicted in Fig. 3 and the results obtained can be summarized as follows: after 75 h of operation FP devices show a POUT degradation of approximately 0.4 dBm and slight decrease in IG; after 1.5 h of operation NOFP devices show a larger POUT degradation of approximately 0.6 dBm and a slight decrease in IG. The effects of the applied RF stress can also be highlighted by comparing RF power sweeps as well as DC and pulsed I–V characteristics carried out on devices before and after the applied RF stress. As can be seen in Fig. 4, FP devices are experiencing a worsening of their performance both in terms of output power as well as PAE, when driven into saturation. Similar stress effects are experienced from the NOFP devices, see Fig. 5. Further insights on the origin of the performance variations observed when comparing RF power sweeps before and after the RF stress can be obtained by comparing static and pulsed I–V characteristics. As can be seen in Fig. 6, FP devices are experiencing a slight decrease in their DC drain current levels after the applied RF stress. On the other hand pulsed drain current levels are significantly decreasing from 0.85 to 0.75 A/mm at VGS = +1 V and VDS = 5 V. Similarly, NOFP devices are showing a slight decrease in their
Fig. 3. CW RF stress at 2.5 GHz carried out on a typical FP and NOFP devices driven at 3 dB into compression. Base-plate temperature is 90 °C, and devices are biased at VDS = 30 V/5% of IDSS.
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DC drain current levels, see Fig. 7, while they are experiencing a more pronounced decrease in pulsed drain current levels which are decreasing from 0.8 to 0.75 A/mm at VGS = +1 V and VDS = 5 V. Results obtained from RF stress experiments can thus be summarized as follows: (i) FP devices are showing a more stable behavior and after 75 h of operation a 0.4 dBm decrease in output power is observed while a similar decrease (i.e. 0.6 dBm) is experienced by NOFP devices after only 1.5 h of operation; (ii) both FP and NOFP devices are showing a slight reduction in their static characteristics at the end of the stress while dynamic ones are more affected; (iii) even if with different extents, gate bias currents are decreasing during the RF stress for both FP and NOFP devices.
5. Transient analysis and numerical simulations In this section we will describe some additional experimental measurements and numerical simulations that have been carried out in order to gain further insights in the physical mechanisms involved in the degradation of device performances observed in the previous sections. Drain current-collapse for both FP and NOFP devices was analyzed by means of drain current transient measurements [7] aimed at the extraction of the activation energies and the localization of trap within the device structures causing the observed current-collapse. As we will see, having both the FP and the NOFP structure on the same wafer allowed us to localize the defects within the device structure. Drain current transients were measured by sampling the turn-on transient induced by pulsing the gate terminal from VGL = 8 V to VGH = 2 V and 0 V. Results obtained are depicted in Fig. 8. Let us focus at first on the transient obtained with VGH = 0 V. As can be seen in Fig. 8A, the NOFP device shows a low-pass response with two clearly distinct emission processes which can be related to two different traps namely t1 and t2. On the other hand the FP device shows the same emission processes with a reduced signal amplitude, which suggest that the FP terminal is able to reduce the effects of t1 and t2, but two high-pass signatures are also visible. Focusing now on Fig. 8B where VGH = 2 V we can still see the emission and capture processes previously described but with a very important difference: now, the FP and NOFP devices are showing very similar trends in terms of the emission and capture process associated to t2 while only the emission of t1 is showing some significant differences, with the FP device being less affected by it. These results suggest the following interpretation that will then be supported by means of numerical simulations. T1 is likely to be a surface trap which causes drain current-collapse due to the trapping of electrons in the gate–drain access region [8,9]. Its presence is mainly seen when drain current transient are recorded in open-channel conditions (i.e. VGH = 0 V) while its effect is likely to be reduced when drain current transient are recorded with a partially open-channel conditions (i.e. VGH = 2 V). Its reduced effect is expected since at VGH = 2 V drain current is limited by the electron concentration below the gate contact rather than that in the access regions. On the other hand, traps t2 which is showing a strong signal even when transient are recorded in partially openchannel conditions, it is likely to be located beneath the gate terminal where it can effectively change the electron concentration in the channel and thus give rise to the capture and emission process observed Fig. 8B. An important consideration can also be made by taking account the differences and similarity of the transients obtained on the FP and NOFP device. The FP device shows always a reduced signal associated with t1, and since the FP action is to reduce the electric-field in the gate–drain access region, and thus electron-injection, it is expected that if t1 is a surface traps the FP device will show a flatter transient than that the NOFP device does. On the other hand FP device does not show a significant difference
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Fig. 4. Typical RF power sweep at 2.5 GHz before and after the 75 h applied RF stress for a FP device. Temperature is 90 °C, and devices are biased at VDS = 30 V/5% of IDSS.
Fig. 5. Typical RF power sweep at 2.5 GHz before and after the 1.5 h applied RF stress for a NOFP device biased at VDS = 30 V/5% of IDSS. Temperature is 90 °C.
Fig. 6. Typical DC (left) and 200 ns pulsed (right) I–V characteristics for a FP device before (solid lines) and after (dashed lines) the applied 75 h RF stress. VGS is stepped from 5 to 1 V, 1 V/step for DC and pulsed measurements. VGS baseline for pulsed measurements is 5 V.
with respect to the NOFP one concerning the t2 capture and emission processes observed during the VGH = 2 V transient. This suggest that t2 is not located at the surface in the gate–drain access
region since, if this would be the case, a significant difference would be expected between the FP and NOFP devices transient behavior.
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Fig. 7. Typical DC (left) and 200 ns pulsed (right) I–V characteristics for a NOFP device before (solid lines) and after (dashed lines) the applied 1.5 h RF stress. VGS is stepped from 5 to 1 V, 1 V/step for DC and pulsed measurements. VGS baseline for pulsed measurements is 5 V.
Fig. 9. Schematic cross-section of the simulated NOFP device.
Fig. 8. Experimental turn-on drain current transient before the applied RF stress test.
After this preliminary analysis we proceeded with the activation energy extraction of the t1 and t2 emission process which yielded a 0.47 eV and 0.75 eV values, respectively. Numerical simulations were then carried out by using the device structure depicted in Fig. 9 where traps t1 and t2 have been settled as follows. T1 has been located as an acceptor trap on the AlGaN surface 0.47 eV below the conduction band, with a concentration of 3.5 1012 cm 2, while t2 has been located as an acceptor trap 0.75 eV below the conduction band and spatially confined below the gate contact but with a non constant concentration. The 30 nm barrier layer has been split in three regions of 10 nm depth each and the trap concentration has been settled to 1 1019, 3 1018 and
1 1018 cm 3 starting from the gate towards the GaN channel. A detailed analysis of the effects of t2 concentration goes beyond the intentions of this paper, however the proposed t2 distribution allowed us to obtain a reasonably good qualitative match between experimental and simulated transients. As can be seen in Fig. 10 the insertion of only two traps t1 and t2 allows to observe all the capture and emission processes which have been experimentally measured. Moreover it is also possible to see how the introduction of the FP structure is capable of reducing the emission process of t1 and t2 for the VGH = 0 V transient while it leaves the capture and emission processes of t2 during the VGH = 2 V transient almost unaffected. A brief explanation of the capture-emission process involved is now given in the following. When no bias is applied to the structure both t1 and t2 traps close to the gate terminal are emptied since the Schottky contact locks the Fermi level below the trap energy level. T2 traps close to the AlGaN/GaN interface are instead partially filled since the Fermi level crosses the trap energy level. Similarly t1 traps in the access region towards the ohmic contacts are partially filled. When a reverse bias is applied to the gate junction, and if no electron-injection occurs, both t1 and t2 traps would be emptied thanks to the electrostatic effect arising from reversebiasing the gate junction. However, when the gate junction is reverse-biased, electrons are also injected from the gate contact towards the device surface and barrier. As a consequence, traps located in regions were the leakage is significant can be filled instead of being emptied [8]. Since gate leakage is mainly concentrated at the gate edge, the traps distribution under high reverse-
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Fig. 10. Simulated turn-on drain current transient. Fig. 11. Experimental turn-on transient before and after the applied RF stress for a NOFP and a FP devices.
bias condition can be summarized as follows: t1 traps close to the gate contact are filled; t2 traps located at the gate edges are filled; t2 traps located in the center of the gate and close to the GaN channel are emptied. When the device is turned on, and the reverse gate voltage is thus decreased, filled t1 and t2 traps start to emit the trapped electrons giving rise to the t1 and t2 emission process observed both experimentally and by means of numerical simulations. On the other hand, t2 traps below the gate contact and close to the GaN channel will have to start an electron capture process in order to go back to their equilibrium conditions. This capture process is however not instantaneous since the AlGaN barrier is always depleted during measurement condition and thus the electron concentration within it is fairly low. The lack of electrons is thus causing a non instantaneous capture process which, being limited by the low electron concentration, gives rise to the t2 capture signatures observed in the drain current transients. Drain current transients were also recorded before and after the RF stress that has been previously presented. As can be seen in Fig. 11, the NOFP device stressed for 1.5 h is experiencing a clear increase in both t1 and t2 emission signatures when compared to the transient carried out before the RF stress. Particularly there are a 60% increase in the t1 signal and a 200% increase in the t2 signal suggesting that during the RF stress both t1 and t2 concentration have increased. On the other hand, the FP devices stressed for 75 h is showing a significant increase only in t2 emission signature while t1 remains practically unchanged. These results suggest that FP devices are definitely more robust than NOFP ones but they are experiencing a similar degradation process which is caused by an increase in t2 concentration, a trap level which is located beneath the gate contact. On the other hand the degradation associated to t1 is highly mitigated in FP devices thanks to the ability of the FP contact to reduce the electric-field in the gate–drain access region.
6. Conclusions Experimental and numerical simulations results are strongly supporting the hypothesis that the worsening of performance for both FP and NOFP devices can be ascribed to an increase in preexisting traps concentration due to high electric-field within the devices. The adoption of the FP structures greatly improves device reliability, although at least one degradation mechanism, i.e. increase in t2 concentration, is not fully removed. An increase in t2 concentration explains also the variation observed in terms of device static parameters. In fact, an increase in t2 concentration, and thus an increase in trapped electrons within the device AlGaN barrier, can account for the lowering in the drain [8] currents levels observed during DC stress test as well as for the lowering of gate current levels [10] observed both during DC and RF stress tests. Acknowledgments Work partially supported by the EDA project MANGA and the Italian MoD project GARANTE. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
Wu YF et al. In: IEEE DRC; 2006. p. 151–2. Vetury R et al. In: IEEE MTT-S; 2006. p. 714–16. Medjdoub F et al. In: IEEE DRC; 2010. p. 195–6. Lee S et al. In: IEEE IRPS; 2008. p. 446–9. Karmalkar S et al. IEEE Trans Electron Dev 2001;48(8):1515–21. Ma C et al. J App Phys 2011;110:114514. Tˇapajna M et al. IEEE Electron Dev Lett 2010;31(7):662–5. Chini A et al. IEEE Electron Dev Lett 2009;30(10):1021–3. Faqir M et al. IEEE Trans Device Mater Reliab 2008;8(2):247. Rozman D et al. In: IEEE ROCS; 2009. p. 7–18.
Contents lists available at SciVerse ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Field plate related reliability improvements in GaN-on-Si HEMTs A. Chini a,⇑, F. Soci a, F. Fantini a, A. Nanni b, A. Pantellini b, C. Lanzieri b, D. Bisi c, G. Meneghesso c, E. Zanoni c a
Department of Information Engineering, University of Modena and Reggio Emilia, 41125 Modena, Italy SELEX Sistemi Integrati S.p.A, 00131 Roma, Italy c Department of Information Engineering, University of Padova, 35131 Padova, Italy b
a r t i c l e
i n f o
Article history: Received 3 June 2012 Received in revised form 18 June 2012 Accepted 18 June 2012 Available online 9 July 2012
a b s t r a c t State of the art GaN on Silicon HEMTs fabricated with and without a field-plate structure have been tested by means of DC and RF reliability tests. The introduction of the field-plate structure greatly improves device reliability both during DC as well as RF testing. Results are thus suggesting that reliability in NOFP and FP devices is mainly limited by the high electric fields within the device structure causing an increase in traps concentration. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction GaN HEMTs devices are of great interest for the development of high RF power applications thanks to their outstanding performance when compared to other semiconductor based solutions. While their superior performances [1] have been repeatedly assessed by several authors, the factors limiting their performance and reliability are still under investigation. Concerning the effects of adding a field-plate structure on the device reliability, Vetury et al. [2] showed how the use of a dualgate (i.e. similar to a field-plate) structure to GaN-on-SiC HEMTs resulted to be effective in improving device reliability suggesting that device degradation is strongly affected by the strength of the peak electric-field in the gate–drain access region. Medjdoub et al. [3] have shown reliability results on field-plated GaN on Silicon HEMT with an excellent stability in their DC characteristics but with a small degradation of their pulsed performance after DC bias stress tests. Similarly, an increase in drain current-collapse after RF stress tests was also observed by Lee et al. [4] on GaNon-SiC HEMTs and was attributed to an increase in electron trapping phenomena. Generally, adding a field-plate structure has thus yielded improvements or state-of-the-art reliability results for GaN HEMTs devices. Nevertheless, to the best of the authors knowledge, a side-by-side comparison between FP and NOFP devices fabricated on the same wafer including RF stress tests, traps characterization and assessment by means of numerical simulations of the physical mechanisms involved in FP and NOFP devices degradation has not yet been presented. In this paper the authors would like to show some experimental and numerical results that are emphasizing the benefits that can be ⇑ Corresponding author. Tel.: +39 059 2056164. E-mail address: [email protected] (A. Chini). 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.06.040
obtained in terms of reliability when a field-plate contact is implemented within the device structure and give some insights in the degradation mechanisms involved. Results obtained both during DC and RF testing are strongly suggesting that the factors limiting devices reliability are related to the increase in material traps concentration due to high electric fields which are known [5] to be mitigated by adopting a fieldplate structure. 2. Device fabrication Coplanar Waveguide (CPW) technology has been adopted to fabricate at SELEX S.I. the active devices reported in this work, employing an AlGaN/GaN hetero-junction grown on a 4 in. HighResistivity Silicon (1 1 1) substrate with q > 7 kX cm and about 525 lm thickness. Ohmic contact resistance value of RC = 0.27 X mm has been obtained with a Ti/Al/Ni/Au metal stack followed by a Rapid Thermal Annealing (RTA) optimized for this substrate. After a Silicon Nitride (SiN) deposition, gate window was opened trough the SiN layer by means of a CF4 based dry-etch. Gate Foot was then fabricated by means of a Ni/Pt metal stack self-aligned evaporation. A thermal treatment has been applied in order to improve device reliability: by annealing the AlGaN surface below the gate contact AlGaN surface damage introduced by dry-etch can be effectively removed. The benefits obtained are appreciable in terms of barrier height and ideality factor values before (UB = 0.9 eV, n = 1.7) and after (UB = 1.16 eV, n = 1.37) the treatment. In order to reduce Gate sheet resistance, a thick Au metallization (Gate Head) has been evaporated as specified below. In particular, two different gate technologies have been applied. On the first half wafer, the same Gate Foot lithography has been replicated to maintain the I-Gate shape; on the other half wafer, an LGHead 3LGFoot has been introduced in order to attain a field-plate with a
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C-Gate shape. This has been aligned with the Gate Foot at the Source side, and bend out about LFP = 2LGFoot toward Drain contact. This wafer partitioning is mandatory to ensure the best comparison between FP and no-FP technologies thanks to the same epistructure and fabrication process. Gate passivation, and electroplating to define interconnect metallization, completed the wafer process for the coplanar technology. Fabricated devices yielded state-of-the-art RF performance for the FP structure reaching power densities of 10.6 W/mm at RT, CW operation at 2.5 GHz and VDS = 60 V. Other typical devices parameters are summarized as follows: 1 mA/mm breakdown voltage was 65 V and 120 V for NOFP and FP devices, respectively; RF power gains and peak PAE at RT under 2.5 GHz CW operation were approximately 13 dB/50% and 12 dB/60% for NOFP and FP devices, respectively. 3. Short Time Stress Test (STST) A preliminary assessment of the devices has been obtained by means of Short Time Stress test (STST) which have been carried out at two different operating conditions. A first experiment was carried out in order to evaluate the effect of reverse-biasing applied to the gate junction. Step-stress experiment was carried out by reverse-biasing the gate terminal with voltage levels starting from VG = 4 V and decreasing VG by 1 V every 100 s. Both source and drain terminal were grounded during the applied stress test. After each step, an ID vs VGS characteristics was measured at VDS = 1 for the evaluation of device VTH. As can be seen in Fig. 1, both FP and NOFP devices are experiencing similar threshold voltage shifts during the applied stress test. Moreover, threshold voltage starts to change appreciably after the step at VG = 6 V, it experiences the maximum variation in the VG = 6 V to 10 V range, and keeps decreasing up to VG = 20 V. The observed threshold voltage shift did not recover even after device storage at RT for more than two weeks, and appeared to be rather stable even when subsequent measurements (i.e. DC or pulsed output characteristics) were carried out. Although further characterization of the observed threshold voltage shift might be needed in order to fully understand the physical phenomena involved, we found it to be very similar to what already observed from Ma et al. [6] on fluorine-implanted enhancement-mode AlGaN/GaN high electron mobility transistors. In [6] a negative threshold voltage shift is observed as a consequence of hot-electrons interaction with fluorine ions implanted in the AlGaN barrier. In our case, although devices were depletion-mode, a fluorine ions incorporation within the AlGaN barrier might happen due to the CF4 based SiN dry-etch used for the gate-window opening. Thus, in our case, the threshold voltage shift might still be promoted by the interac-
Fig. 1. Cumulative device threshold voltage shift induced by reverse-biasing the gate junction. Threshold voltage is extracted from ID vs VGS measurements carried out at VDS = 1 V.
tion of hot-electrons and incorporated fluorine ions given the strong dependence observed of the threshold voltage shift from the reverse bias applied to the gate junction. A second experiment was also carried out in on-state operating condition where a VDS = 40 V, 50 V and 60 V Drain Bias is applied for 1 h at IDS = 30% of saturation current (IDSS) in successive steps. Devices used for this test were preliminary subjected to DC IV characterization which induced an approximately 0.6 V negative shift in devices threshold voltage in order to avoid its effects on the experiment findings. The STST results during the stress on FP and NOFP devices are reported in Fig. 2A and B and their results can be summarized as follows: NOFP devices are showing a slight decrease in both ID and IG values during the applied STST and are failing when biased at VDS = 60 V. On the other hand FP device are showing a very stable behavior during the VDS = 40 and 50 V steps in terms of drain currents while gate currents are not showing a monotonous trend. During the stress at VDS = 60 V drain current is showing a slight decrease in its value while a significant gate current decrease is observed. Results obtained from STST experiments can thus be summarized as follows: (i) a reverse gate-bias applied to a fresh device induces a negative VTH shift for both FP and NOFP devices; (ii) onstate STST experiments show a more stable behavior of FP devices when compared to NOFP ones; (iii) on-state STST experiment at VDS = 60 V for FP device and at VDS = 40 V and, more pronounced, at VDS = 50 V for NOFP devices are showing a slight decrease of DC drain current levels as well as a significant decrease in gate current levels. 4. RF stress tests at 2.5 GHz Finally, 4 50 lm gate periphery devices were also subjected to on-wafer CW RF stress tests carried out at 2.5 GHz. Three NOFP and three FP devices were subjected to the RF stress and the results that follows refers to typical results obtained for a NOFP and a FP devices. Said devices were subjected to a preliminary characterization measurements set which included DC and pulsed IV characterization as well as drain current transient recorded at different temperatures. The investigations are aimed at the analysis of trap-
Fig. 2. Drain and gate current variation during the on-state STST test on NOFP (a) and FP (b) devices.
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ping phenomena limiting device performances and/or reliability. The threshold voltage shift was ‘‘induced’’ by repeating several time DC and pulsed-IV characterizations until its variation across repeated measurements vanished. For both FP and No-FP RF stress the following parameters were used: VDS = 30 V and IDS = 5% of IDSS; 90 °C base-plate temperature; input and output matching conditions were US = 0\0° and UL = 0.78\5° respectively. Input available power levels were chosen in order to operate both FP and No-FP at a 3 dB compression point which corresponds to a 4.8 W/mm and 3.5 W/mm output power for the FP and NOFP devices, respectively. For both FP and NOFP devices gate bias currents were always negative during device operation proving that gate diodes were not significantly turned on during device operation. A 98 K/W thermal resistance was also extracted by means of numerical simulations. As a consequence, junction temperatures during the applied RF stress were approximately 135 °C and 125 °C for FP and NOFP devices, respectively. Stress results are depicted in Fig. 3 and the results obtained can be summarized as follows: after 75 h of operation FP devices show a POUT degradation of approximately 0.4 dBm and slight decrease in IG; after 1.5 h of operation NOFP devices show a larger POUT degradation of approximately 0.6 dBm and a slight decrease in IG. The effects of the applied RF stress can also be highlighted by comparing RF power sweeps as well as DC and pulsed I–V characteristics carried out on devices before and after the applied RF stress. As can be seen in Fig. 4, FP devices are experiencing a worsening of their performance both in terms of output power as well as PAE, when driven into saturation. Similar stress effects are experienced from the NOFP devices, see Fig. 5. Further insights on the origin of the performance variations observed when comparing RF power sweeps before and after the RF stress can be obtained by comparing static and pulsed I–V characteristics. As can be seen in Fig. 6, FP devices are experiencing a slight decrease in their DC drain current levels after the applied RF stress. On the other hand pulsed drain current levels are significantly decreasing from 0.85 to 0.75 A/mm at VGS = +1 V and VDS = 5 V. Similarly, NOFP devices are showing a slight decrease in their
Fig. 3. CW RF stress at 2.5 GHz carried out on a typical FP and NOFP devices driven at 3 dB into compression. Base-plate temperature is 90 °C, and devices are biased at VDS = 30 V/5% of IDSS.
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DC drain current levels, see Fig. 7, while they are experiencing a more pronounced decrease in pulsed drain current levels which are decreasing from 0.8 to 0.75 A/mm at VGS = +1 V and VDS = 5 V. Results obtained from RF stress experiments can thus be summarized as follows: (i) FP devices are showing a more stable behavior and after 75 h of operation a 0.4 dBm decrease in output power is observed while a similar decrease (i.e. 0.6 dBm) is experienced by NOFP devices after only 1.5 h of operation; (ii) both FP and NOFP devices are showing a slight reduction in their static characteristics at the end of the stress while dynamic ones are more affected; (iii) even if with different extents, gate bias currents are decreasing during the RF stress for both FP and NOFP devices.
5. Transient analysis and numerical simulations In this section we will describe some additional experimental measurements and numerical simulations that have been carried out in order to gain further insights in the physical mechanisms involved in the degradation of device performances observed in the previous sections. Drain current-collapse for both FP and NOFP devices was analyzed by means of drain current transient measurements [7] aimed at the extraction of the activation energies and the localization of trap within the device structures causing the observed current-collapse. As we will see, having both the FP and the NOFP structure on the same wafer allowed us to localize the defects within the device structure. Drain current transients were measured by sampling the turn-on transient induced by pulsing the gate terminal from VGL = 8 V to VGH = 2 V and 0 V. Results obtained are depicted in Fig. 8. Let us focus at first on the transient obtained with VGH = 0 V. As can be seen in Fig. 8A, the NOFP device shows a low-pass response with two clearly distinct emission processes which can be related to two different traps namely t1 and t2. On the other hand the FP device shows the same emission processes with a reduced signal amplitude, which suggest that the FP terminal is able to reduce the effects of t1 and t2, but two high-pass signatures are also visible. Focusing now on Fig. 8B where VGH = 2 V we can still see the emission and capture processes previously described but with a very important difference: now, the FP and NOFP devices are showing very similar trends in terms of the emission and capture process associated to t2 while only the emission of t1 is showing some significant differences, with the FP device being less affected by it. These results suggest the following interpretation that will then be supported by means of numerical simulations. T1 is likely to be a surface trap which causes drain current-collapse due to the trapping of electrons in the gate–drain access region [8,9]. Its presence is mainly seen when drain current transient are recorded in open-channel conditions (i.e. VGH = 0 V) while its effect is likely to be reduced when drain current transient are recorded with a partially open-channel conditions (i.e. VGH = 2 V). Its reduced effect is expected since at VGH = 2 V drain current is limited by the electron concentration below the gate contact rather than that in the access regions. On the other hand, traps t2 which is showing a strong signal even when transient are recorded in partially openchannel conditions, it is likely to be located beneath the gate terminal where it can effectively change the electron concentration in the channel and thus give rise to the capture and emission process observed Fig. 8B. An important consideration can also be made by taking account the differences and similarity of the transients obtained on the FP and NOFP device. The FP device shows always a reduced signal associated with t1, and since the FP action is to reduce the electric-field in the gate–drain access region, and thus electron-injection, it is expected that if t1 is a surface traps the FP device will show a flatter transient than that the NOFP device does. On the other hand FP device does not show a significant difference
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Fig. 4. Typical RF power sweep at 2.5 GHz before and after the 75 h applied RF stress for a FP device. Temperature is 90 °C, and devices are biased at VDS = 30 V/5% of IDSS.
Fig. 5. Typical RF power sweep at 2.5 GHz before and after the 1.5 h applied RF stress for a NOFP device biased at VDS = 30 V/5% of IDSS. Temperature is 90 °C.
Fig. 6. Typical DC (left) and 200 ns pulsed (right) I–V characteristics for a FP device before (solid lines) and after (dashed lines) the applied 75 h RF stress. VGS is stepped from 5 to 1 V, 1 V/step for DC and pulsed measurements. VGS baseline for pulsed measurements is 5 V.
with respect to the NOFP one concerning the t2 capture and emission processes observed during the VGH = 2 V transient. This suggest that t2 is not located at the surface in the gate–drain access
region since, if this would be the case, a significant difference would be expected between the FP and NOFP devices transient behavior.
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Fig. 7. Typical DC (left) and 200 ns pulsed (right) I–V characteristics for a NOFP device before (solid lines) and after (dashed lines) the applied 1.5 h RF stress. VGS is stepped from 5 to 1 V, 1 V/step for DC and pulsed measurements. VGS baseline for pulsed measurements is 5 V.
Fig. 9. Schematic cross-section of the simulated NOFP device.
Fig. 8. Experimental turn-on drain current transient before the applied RF stress test.
After this preliminary analysis we proceeded with the activation energy extraction of the t1 and t2 emission process which yielded a 0.47 eV and 0.75 eV values, respectively. Numerical simulations were then carried out by using the device structure depicted in Fig. 9 where traps t1 and t2 have been settled as follows. T1 has been located as an acceptor trap on the AlGaN surface 0.47 eV below the conduction band, with a concentration of 3.5 1012 cm 2, while t2 has been located as an acceptor trap 0.75 eV below the conduction band and spatially confined below the gate contact but with a non constant concentration. The 30 nm barrier layer has been split in three regions of 10 nm depth each and the trap concentration has been settled to 1 1019, 3 1018 and
1 1018 cm 3 starting from the gate towards the GaN channel. A detailed analysis of the effects of t2 concentration goes beyond the intentions of this paper, however the proposed t2 distribution allowed us to obtain a reasonably good qualitative match between experimental and simulated transients. As can be seen in Fig. 10 the insertion of only two traps t1 and t2 allows to observe all the capture and emission processes which have been experimentally measured. Moreover it is also possible to see how the introduction of the FP structure is capable of reducing the emission process of t1 and t2 for the VGH = 0 V transient while it leaves the capture and emission processes of t2 during the VGH = 2 V transient almost unaffected. A brief explanation of the capture-emission process involved is now given in the following. When no bias is applied to the structure both t1 and t2 traps close to the gate terminal are emptied since the Schottky contact locks the Fermi level below the trap energy level. T2 traps close to the AlGaN/GaN interface are instead partially filled since the Fermi level crosses the trap energy level. Similarly t1 traps in the access region towards the ohmic contacts are partially filled. When a reverse bias is applied to the gate junction, and if no electron-injection occurs, both t1 and t2 traps would be emptied thanks to the electrostatic effect arising from reversebiasing the gate junction. However, when the gate junction is reverse-biased, electrons are also injected from the gate contact towards the device surface and barrier. As a consequence, traps located in regions were the leakage is significant can be filled instead of being emptied [8]. Since gate leakage is mainly concentrated at the gate edge, the traps distribution under high reverse-
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Fig. 10. Simulated turn-on drain current transient. Fig. 11. Experimental turn-on transient before and after the applied RF stress for a NOFP and a FP devices.
bias condition can be summarized as follows: t1 traps close to the gate contact are filled; t2 traps located at the gate edges are filled; t2 traps located in the center of the gate and close to the GaN channel are emptied. When the device is turned on, and the reverse gate voltage is thus decreased, filled t1 and t2 traps start to emit the trapped electrons giving rise to the t1 and t2 emission process observed both experimentally and by means of numerical simulations. On the other hand, t2 traps below the gate contact and close to the GaN channel will have to start an electron capture process in order to go back to their equilibrium conditions. This capture process is however not instantaneous since the AlGaN barrier is always depleted during measurement condition and thus the electron concentration within it is fairly low. The lack of electrons is thus causing a non instantaneous capture process which, being limited by the low electron concentration, gives rise to the t2 capture signatures observed in the drain current transients. Drain current transients were also recorded before and after the RF stress that has been previously presented. As can be seen in Fig. 11, the NOFP device stressed for 1.5 h is experiencing a clear increase in both t1 and t2 emission signatures when compared to the transient carried out before the RF stress. Particularly there are a 60% increase in the t1 signal and a 200% increase in the t2 signal suggesting that during the RF stress both t1 and t2 concentration have increased. On the other hand, the FP devices stressed for 75 h is showing a significant increase only in t2 emission signature while t1 remains practically unchanged. These results suggest that FP devices are definitely more robust than NOFP ones but they are experiencing a similar degradation process which is caused by an increase in t2 concentration, a trap level which is located beneath the gate contact. On the other hand the degradation associated to t1 is highly mitigated in FP devices thanks to the ability of the FP contact to reduce the electric-field in the gate–drain access region.
6. Conclusions Experimental and numerical simulations results are strongly supporting the hypothesis that the worsening of performance for both FP and NOFP devices can be ascribed to an increase in preexisting traps concentration due to high electric-field within the devices. The adoption of the FP structures greatly improves device reliability, although at least one degradation mechanism, i.e. increase in t2 concentration, is not fully removed. An increase in t2 concentration explains also the variation observed in terms of device static parameters. In fact, an increase in t2 concentration, and thus an increase in trapped electrons within the device AlGaN barrier, can account for the lowering in the drain [8] currents levels observed during DC stress test as well as for the lowering of gate current levels [10] observed both during DC and RF stress tests. Acknowledgments Work partially supported by the EDA project MANGA and the Italian MoD project GARANTE. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
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