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Reliability of 70 nm metamorphic HEMTs
Microelectronics Reliability 44 (2004) 939–943 www.elsevier.com/locate/microrel
Reliability of 70 nm metamorphic HEMTs M. Dammann *, A. Leuther, R. Quay, M. Meng, H. Konstanzer, W. Jantz, M. Mikulla Fraunhofer Institut Angewandte Festk€orperphysik, Tullastr. 72, D-79108 Freiburg, Germany Received 2 September 2003; received in revised form 7 January 2004 Available online 13 April 2004
Abstract The reliability and degradation mechanisms of 70 nm gate length metamorphic InAlAs/InGaAs HEMTs for low noise applications will be presented and discussed. Based on a 10% gm max failure criterion, a median time to failure of 106 h and an activation energy of 1.3 eV in air were found. By comparing the electrical device characteristics before and after stress, gate sinking, ohmic contact degradation, and hot electron degradation were found to be the major failure mechanisms. The stress induced platinum diffusion into the semiconductor was quantified by cross-section TEM. 2004 Elsevier Ltd. All rights reserved.
1. Introduction InAlAs/InGaAs HEMTs on InP substrate (InP based HEMTs) are used for low noise applications at 94 GHz and beyond [1,2]. In this work, the InAlAs/InGaAs HEMTs have been grown on GaAs with metamorphic buffer (MHEMT) to reduce chip costs. The reliability and degradation mechanisms of MHEMTs with 100 nm gate length and 65% In content in the channel has already been investigated in a previous study [3]. In this work, the switching speed of MHEMTs has been further improved by increasing the In content in the channel to 80% and by reducing the gate length to 70 nm. It is likely that both parameters have an important impact on device reliability. Therefore the long-term stability has been thoroughly studied by biased accelerated life time tests and the degradation mechanisms have been investigated by comparing the electrical device characteristics before and after stress. Gate sinking has already been positively identified by cross section TEM analysis of 100 nm gate length MHEMTs stressed with applied bias [3]. In this work TEM analysis has been used to inves-
* Corresponding author. Tel.: +49-761-5159-517; fax: +49761-5159-71517. E-mail address: [email protected] (M. Dammann).
tigate the effect of bias on gate sinking of 70 nm gate length devices. 2. Fabrication The InAlAs/InGaAs HEMTs were grown on 4 in. semi-insulating GaAs wafer by molecular beam epitaxy. The T-shaped Pt–Ti–Pt–Au gates were defined by direct e-beam lithography. More details of the epitaxial layer structure and the technology of the investigated device have been reported by Leuther et al. [4]. 3. Accelerated lifetime test procedure The long-term stability of metamorphic HEMTs was investigated by temperature accelerated life tests with and without bias, subsequently referred to as biased and storage tests, respectively. Biased tests were performed at three channel temperatures at a drain voltage of 1 V and a current density of 300 mA/mm in air. Owing to the high indium content of 80%, the room temperature onstate breakdown voltage was found to be 1.7 V at a drain current of 400 mA/mm. It is expected to decrease with increasing temperature [5]. Therefore special care had to be taken to avoid device failure due to electromagnetic radiation. The experiments were performed in a Faraday cage and the oven temperature was
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.01.015
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943
periodically ramped down from the stress temperature to 30 C for intermittent measurements. In order to investigate the stress induced degradation mechanisms, biased and storage tests at the same temperature were performed. The temperature increase due to device heating for the biased test was taken into account by a corresponding increase of the oven temperature for the storage test. After electrical characterization the stressed devices were examined by TEM analysis. The degradation of the ohmic contact resistance was investigated by storage tests of HEMTs and transmission line measurement (TLM) test structures at 180, 200 and 220 C.
300 Median time to failure (h)
940
T (°C) 200 ch 150
250
100
6
10
6
t50%=1.1x10 h Ea=1.3 eV
5
10
4
10
Tch=125°C
3
10
2
10
1.8
2.0
2.2 2.4 1000/Tch (1/K)
2.6
Fig. 2. Arrhenius plot of biased stressed HEMT.
4. Results on reliability
5. Results on degradation mechanisms The transfer characteristic after a storage test at an oven temperature of 240 C is shown in Fig. 3 and the result of the biased test at a channel temperature of 240 C is depicted in Fig. 4. The relative decrease of the gm max is only 15% and therefore smaller than for the storage test. The drain resistance increases three times faster than the source resistance due to hot electron induced degradation [8].
Tch=200°C Tch=220°C Tch=240°C
5
0
2000
-5
-10
initial after Ta =240°C, 240h
∆Vt=60 mV ∆gm max/gm max=-24% ∆Rs/Rs=50 % 1000 ∆Rd/Rd=44 % ∆gmi max/gmi max=13%
600 400
500
200
0 -1.5 0
500
1000
1500
2000
1000 800
1500 gm (mS/mm)
∆g m max/g m max (%)
energy of 1.9 eV and an extrapolated median life time of 3 · 107 h was calculated [3]. The reduction in gate length leads to a higher maximum electrical field and the increase of the indium content reduces the channel band gap which in turn increases the generation of electron– hole pairs by impact ionization. Both effects are expected to lead to a faster degradation rate due to hot carrier trapping.
Ids (mA/mm)
Fig. 1 shows the extrinsic maximum transconductance, gm max , versus aging time at three channel temperatures in ambient air. By three-dimensional temperature simulations [6] it was estimated that the channel temperature is approximately 20 C higher than the oven temperature due to device heating. The median life time was calculated based on a failure criterion of 10% degradation of gm max and the lognormal distribution. Fig. 2 shows the Arrhenius plot of the median life time versus inverse channel temperature, yielding an activation energy of 1.3 eV and an extrapolated life time of 1 · 106 h at Tch ¼ 125 C. This result compares well with the activation energy of 1.7 eV and the extrapolated life time of 2 · 106 h found by Chou et al. for pseudomorphic InP based HEMTs and 70 nm gate length [7]. Therefore we conclude that there is no negative impact of the metamorphic buffer on device reliability. For a gate length of 100 nm instead of 70 nm and an In content of 65% instead of 80% in the channel an activation
0 -1.0
-0.5 0.0 Vgs (V)
0.5
1.0
plateau time (h) Fig. 1. Degradation of the maximum transconductance.
Fig. 3. Transfer characteristic after storage test at 240 C for 240 h.
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943
initial after Tch=240°C, 240h, P=0.31000 W/mm
gm (mS/mm)
1000
∆Vt=170 mV ∆gm max/gm max=-15% ∆R /R =33 % s
800 600
s
∆Rd/Rd=92 % ∆gmi max/gmi max=45%
400
500
200
0 -1.5
Ids (mA/mm)
2000 1500
941
0 -1.0
-0.5
0.0
0.5
1.0
Vgs (V) Fig. 4. Transfer characteristic after biased stress test at Tch ¼ 240 C for 240 h and P ¼ 0:3 W/mm.
From the measured extrinsic maximum transconductance, gm max , the source and drain resistance corrected maximum intrinsic transconductance, gmi max , was calculated using the Eq. [9] gmi max ¼
Fig. 5. TEM cross-section of device after storage test at 240 C for 240 h.
gm max 1 gds ðRs þ Rd Þ gm max Rs
where Rs ðRd Þ denote the source (drain) resistance. From Fig. 3 and Fig. 4 it is seen that gmi max increases by 13% and 45% for the storage test and the biased test, respectively. According to the one-dimensional charge control model the intrinsic transconductance is inversely proportional to the gate to channel separation [10]. Thus the stress induced increase of gmi max indicates gate sinking which reduces the gate to channel distance. The positive shift of the threshold voltages, also given in Figs. 3 and 4, further supports this hypothesis. In order to visualize and to quantify the gate sinking process TEM analysis of three samples has been performed. Figs. 5 and 6 show the TEM cross sections after storage and biased test. For comparison the TEM cross section of an unstressed reference device is shown in Fig. 7. The thickness of the platinum layer as compared to the reference sample has increased by 1 nm after storage test and by 2 nm after biased test. The electrical and analytical results indicate that the gate sinking process is accelerated by the applied bias, to be verified by further experiments. By more elaborate two-dimensional simulations it was found that the threshold voltage increases linearly by about 80 mV per nm decrease of the gate to channel separation [11]. Experimentally a 60 mV (170 mV) increase of the threshold voltage was found for the stored device (biased device). In spite of the uncertainty of the experimental platinum layer thickness determination quite good agreement between measured and simulated threshold voltage shifts was found, given that the 1 nm
Fig. 6. TEM cross section of device after biased test at Tch ¼ 240 C for 240 h and P ¼ 0:3 W/mm.
(2 nm) Pt diffusion occurs primarily towards the semiconductor and not towards the titanium. The degradation of the ohmic contact resistance was studied by storage tests of TLM and HEMT structures. Fig. 8 shows the relative change of the contact resistance of TLM structures versus aging time at ambient temperatures of 180, 200, and 220 C. Based on a 50% increase of contact resistance failure criterion, which
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943
Median time to failure (h)
942
300 107
Tch (°C) 200 150
250
100
Rc gm max
6
10
5
10
4
10
3
10
2
10
1
10
0
10
1.8
2.0
2.2 2.4 1000/Tch (1/K)
2.6
Fig. 9. Arrhenius plot of unbiased stressed TLM and HEMT devices.
Fig. 7. TEM cross-section of unstressed reference device.
70.0 60.0
Ta=220°C
∆Rc/Rc [%]
50.0 Ta=200°C
40.0 30.0 20.0 10.0
Ta=180°C
0.0 200
400
6. Conclusions The reliability of MHEMTs with a gate length of 70 nm was investigated by accelerated temperature stress tests. The life time exceeds 106 h at a channel temperature of 125 C. The major degradation mechanisms were found to be gate sinking, ohmic contact degradation and hot carrier trapping. The gate sinking was investigated and quantified by measuring the platinum layer thickness using cross section TEM. Two-dimensional simulations can reproduce the experimentally observed threshold voltage shifts. The comparison of biased and unbiased stress tests indicates that gate sinking and gm max degradation of MHEMT devices is accelerated by the applied bias.
600
time (h) Fig. 8. Relative change of contact resistance versus aging time of TLM structures.
corresponds to about 15% parasitic drain and source resistance increase and a 10% gm max degradation, we estimated an activation energy of 1.9 eV and a median life time of 1.4 · 106 h at Tch ¼ 125 C. Fig. 9 shows the Arrhenius plot of TLM and HEMT devices. The activation energies and median life times of HEMTs and TLM structures are comparable indicating that ohmic contact degradation is the main degradation mechanism of storage tested HEMT devices. The activation energy of ohmic contact degradation is approximately 0.5 eV higher than the value found for the gm max degradation of biased tested HEMT devices. This result indicates that the degradation of HEMTs is accelerated by the applied bias.
Acknowledgements The author would like to thank F. Altmann, L. Berthold and I. Sch€ ulke from the Fraunhofer IWMH for the TEM preparation and analysis.
References [1] Streit D, Lai R, Oki A, Guitierrez-Aiteken. Proceedings of 14th Indium Phosphide and Related Materials Conference, Stockholm. 2002, pp. 11–14. [2] Tessmann A, Leuther A, Massler H, Reinert W, Schw€ orer C, Dammann M, et al. Third ESA Workshop on Millimetre Wave Technology and Applications, Espo, 2003. pp. 317–322. [3] Dammann M, Leuther A, Benkhelifa F, Feltgen T, Jantz W. Reliability and degradation mechanism of AlGaAs/ InGaAs and InAlAs/InGaAs HEMTs. Phys Stat Sol (a) 2003;1:81–6.
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943 [4] Leuther A, Tessmann A, Dammann M, Reinert W, Schlechtweg M, Mikulla M, et al. 15th Indium Phosphide and Related Materials Conference, Santa Barbara. 2003, pp. 215–218. [5] Meneghesso G, Massari G, Buttari D, Bortoletto A, Maretto M, Zanoni E. DC and pulsed measurements of on-state breakdown voltage in GaAs MESFETs and InPbased HEMTs. Microelectr Reliab 1999;39:1759–63. [6] Marsetz W, Dammann M, Kawashima H, R€ udiger J, Matthes B, H€ ulsmann A, et al. 28th European Microwave Conference, Amsterdam. 1998, pp. 439–442. [7] Chou YC, Leung D, Lai R, Grundbacher R, Barsky M, Tsai R, et al. Indium Phosphide and Related Materials Conference, Stockholm. 2002, pp. 365-368.
943
[8] Wakita AS, Rohdin H, Su C-Y, Moll N, Nagy A, Robbins VM. Indium Phosphide and Related Materials Conference, Santa Barbara, 1997,Cape Cod, pp. 376–379. [9] Chou SY, Antoniadis DA. Relationship between measured and intrinsic transconductance of FETs. IEEE Trans Electr Dev 1987;ED-34:448–50. [10] Bayens Y, Monolithic microwave integrated circuits using GaAs and InP based heterojunction field-effect transistors. Ph.D. thesis. Katholieke Universiteit Leuven, 1996. [11] Quay R. Analysis and simulation of high electron mobility transistors. Ph.D. thesis. Technische Universit€at Wien, Aachen: Shaker Verlag, 2002.
Reliability of 70 nm metamorphic HEMTs M. Dammann *, A. Leuther, R. Quay, M. Meng, H. Konstanzer, W. Jantz, M. Mikulla Fraunhofer Institut Angewandte Festk€orperphysik, Tullastr. 72, D-79108 Freiburg, Germany Received 2 September 2003; received in revised form 7 January 2004 Available online 13 April 2004
Abstract The reliability and degradation mechanisms of 70 nm gate length metamorphic InAlAs/InGaAs HEMTs for low noise applications will be presented and discussed. Based on a 10% gm max failure criterion, a median time to failure of 106 h and an activation energy of 1.3 eV in air were found. By comparing the electrical device characteristics before and after stress, gate sinking, ohmic contact degradation, and hot electron degradation were found to be the major failure mechanisms. The stress induced platinum diffusion into the semiconductor was quantified by cross-section TEM. 2004 Elsevier Ltd. All rights reserved.
1. Introduction InAlAs/InGaAs HEMTs on InP substrate (InP based HEMTs) are used for low noise applications at 94 GHz and beyond [1,2]. In this work, the InAlAs/InGaAs HEMTs have been grown on GaAs with metamorphic buffer (MHEMT) to reduce chip costs. The reliability and degradation mechanisms of MHEMTs with 100 nm gate length and 65% In content in the channel has already been investigated in a previous study [3]. In this work, the switching speed of MHEMTs has been further improved by increasing the In content in the channel to 80% and by reducing the gate length to 70 nm. It is likely that both parameters have an important impact on device reliability. Therefore the long-term stability has been thoroughly studied by biased accelerated life time tests and the degradation mechanisms have been investigated by comparing the electrical device characteristics before and after stress. Gate sinking has already been positively identified by cross section TEM analysis of 100 nm gate length MHEMTs stressed with applied bias [3]. In this work TEM analysis has been used to inves-
* Corresponding author. Tel.: +49-761-5159-517; fax: +49761-5159-71517. E-mail address: [email protected] (M. Dammann).
tigate the effect of bias on gate sinking of 70 nm gate length devices. 2. Fabrication The InAlAs/InGaAs HEMTs were grown on 4 in. semi-insulating GaAs wafer by molecular beam epitaxy. The T-shaped Pt–Ti–Pt–Au gates were defined by direct e-beam lithography. More details of the epitaxial layer structure and the technology of the investigated device have been reported by Leuther et al. [4]. 3. Accelerated lifetime test procedure The long-term stability of metamorphic HEMTs was investigated by temperature accelerated life tests with and without bias, subsequently referred to as biased and storage tests, respectively. Biased tests were performed at three channel temperatures at a drain voltage of 1 V and a current density of 300 mA/mm in air. Owing to the high indium content of 80%, the room temperature onstate breakdown voltage was found to be 1.7 V at a drain current of 400 mA/mm. It is expected to decrease with increasing temperature [5]. Therefore special care had to be taken to avoid device failure due to electromagnetic radiation. The experiments were performed in a Faraday cage and the oven temperature was
0026-2714/$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2004.01.015
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943
periodically ramped down from the stress temperature to 30 C for intermittent measurements. In order to investigate the stress induced degradation mechanisms, biased and storage tests at the same temperature were performed. The temperature increase due to device heating for the biased test was taken into account by a corresponding increase of the oven temperature for the storage test. After electrical characterization the stressed devices were examined by TEM analysis. The degradation of the ohmic contact resistance was investigated by storage tests of HEMTs and transmission line measurement (TLM) test structures at 180, 200 and 220 C.
300 Median time to failure (h)
940
T (°C) 200 ch 150
250
100
6
10
6
t50%=1.1x10 h Ea=1.3 eV
5
10
4
10
Tch=125°C
3
10
2
10
1.8
2.0
2.2 2.4 1000/Tch (1/K)
2.6
Fig. 2. Arrhenius plot of biased stressed HEMT.
4. Results on reliability
5. Results on degradation mechanisms The transfer characteristic after a storage test at an oven temperature of 240 C is shown in Fig. 3 and the result of the biased test at a channel temperature of 240 C is depicted in Fig. 4. The relative decrease of the gm max is only 15% and therefore smaller than for the storage test. The drain resistance increases three times faster than the source resistance due to hot electron induced degradation [8].
Tch=200°C Tch=220°C Tch=240°C
5
0
2000
-5
-10
initial after Ta =240°C, 240h
∆Vt=60 mV ∆gm max/gm max=-24% ∆Rs/Rs=50 % 1000 ∆Rd/Rd=44 % ∆gmi max/gmi max=13%
600 400
500
200
0 -1.5 0
500
1000
1500
2000
1000 800
1500 gm (mS/mm)
∆g m max/g m max (%)
energy of 1.9 eV and an extrapolated median life time of 3 · 107 h was calculated [3]. The reduction in gate length leads to a higher maximum electrical field and the increase of the indium content reduces the channel band gap which in turn increases the generation of electron– hole pairs by impact ionization. Both effects are expected to lead to a faster degradation rate due to hot carrier trapping.
Ids (mA/mm)
Fig. 1 shows the extrinsic maximum transconductance, gm max , versus aging time at three channel temperatures in ambient air. By three-dimensional temperature simulations [6] it was estimated that the channel temperature is approximately 20 C higher than the oven temperature due to device heating. The median life time was calculated based on a failure criterion of 10% degradation of gm max and the lognormal distribution. Fig. 2 shows the Arrhenius plot of the median life time versus inverse channel temperature, yielding an activation energy of 1.3 eV and an extrapolated life time of 1 · 106 h at Tch ¼ 125 C. This result compares well with the activation energy of 1.7 eV and the extrapolated life time of 2 · 106 h found by Chou et al. for pseudomorphic InP based HEMTs and 70 nm gate length [7]. Therefore we conclude that there is no negative impact of the metamorphic buffer on device reliability. For a gate length of 100 nm instead of 70 nm and an In content of 65% instead of 80% in the channel an activation
0 -1.0
-0.5 0.0 Vgs (V)
0.5
1.0
plateau time (h) Fig. 1. Degradation of the maximum transconductance.
Fig. 3. Transfer characteristic after storage test at 240 C for 240 h.
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943
initial after Tch=240°C, 240h, P=0.31000 W/mm
gm (mS/mm)
1000
∆Vt=170 mV ∆gm max/gm max=-15% ∆R /R =33 % s
800 600
s
∆Rd/Rd=92 % ∆gmi max/gmi max=45%
400
500
200
0 -1.5
Ids (mA/mm)
2000 1500
941
0 -1.0
-0.5
0.0
0.5
1.0
Vgs (V) Fig. 4. Transfer characteristic after biased stress test at Tch ¼ 240 C for 240 h and P ¼ 0:3 W/mm.
From the measured extrinsic maximum transconductance, gm max , the source and drain resistance corrected maximum intrinsic transconductance, gmi max , was calculated using the Eq. [9] gmi max ¼
Fig. 5. TEM cross-section of device after storage test at 240 C for 240 h.
gm max 1 gds ðRs þ Rd Þ gm max Rs
where Rs ðRd Þ denote the source (drain) resistance. From Fig. 3 and Fig. 4 it is seen that gmi max increases by 13% and 45% for the storage test and the biased test, respectively. According to the one-dimensional charge control model the intrinsic transconductance is inversely proportional to the gate to channel separation [10]. Thus the stress induced increase of gmi max indicates gate sinking which reduces the gate to channel distance. The positive shift of the threshold voltages, also given in Figs. 3 and 4, further supports this hypothesis. In order to visualize and to quantify the gate sinking process TEM analysis of three samples has been performed. Figs. 5 and 6 show the TEM cross sections after storage and biased test. For comparison the TEM cross section of an unstressed reference device is shown in Fig. 7. The thickness of the platinum layer as compared to the reference sample has increased by 1 nm after storage test and by 2 nm after biased test. The electrical and analytical results indicate that the gate sinking process is accelerated by the applied bias, to be verified by further experiments. By more elaborate two-dimensional simulations it was found that the threshold voltage increases linearly by about 80 mV per nm decrease of the gate to channel separation [11]. Experimentally a 60 mV (170 mV) increase of the threshold voltage was found for the stored device (biased device). In spite of the uncertainty of the experimental platinum layer thickness determination quite good agreement between measured and simulated threshold voltage shifts was found, given that the 1 nm
Fig. 6. TEM cross section of device after biased test at Tch ¼ 240 C for 240 h and P ¼ 0:3 W/mm.
(2 nm) Pt diffusion occurs primarily towards the semiconductor and not towards the titanium. The degradation of the ohmic contact resistance was studied by storage tests of TLM and HEMT structures. Fig. 8 shows the relative change of the contact resistance of TLM structures versus aging time at ambient temperatures of 180, 200, and 220 C. Based on a 50% increase of contact resistance failure criterion, which
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943
Median time to failure (h)
942
300 107
Tch (°C) 200 150
250
100
Rc gm max
6
10
5
10
4
10
3
10
2
10
1
10
0
10
1.8
2.0
2.2 2.4 1000/Tch (1/K)
2.6
Fig. 9. Arrhenius plot of unbiased stressed TLM and HEMT devices.
Fig. 7. TEM cross-section of unstressed reference device.
70.0 60.0
Ta=220°C
∆Rc/Rc [%]
50.0 Ta=200°C
40.0 30.0 20.0 10.0
Ta=180°C
0.0 200
400
6. Conclusions The reliability of MHEMTs with a gate length of 70 nm was investigated by accelerated temperature stress tests. The life time exceeds 106 h at a channel temperature of 125 C. The major degradation mechanisms were found to be gate sinking, ohmic contact degradation and hot carrier trapping. The gate sinking was investigated and quantified by measuring the platinum layer thickness using cross section TEM. Two-dimensional simulations can reproduce the experimentally observed threshold voltage shifts. The comparison of biased and unbiased stress tests indicates that gate sinking and gm max degradation of MHEMT devices is accelerated by the applied bias.
600
time (h) Fig. 8. Relative change of contact resistance versus aging time of TLM structures.
corresponds to about 15% parasitic drain and source resistance increase and a 10% gm max degradation, we estimated an activation energy of 1.9 eV and a median life time of 1.4 · 106 h at Tch ¼ 125 C. Fig. 9 shows the Arrhenius plot of TLM and HEMT devices. The activation energies and median life times of HEMTs and TLM structures are comparable indicating that ohmic contact degradation is the main degradation mechanism of storage tested HEMT devices. The activation energy of ohmic contact degradation is approximately 0.5 eV higher than the value found for the gm max degradation of biased tested HEMT devices. This result indicates that the degradation of HEMTs is accelerated by the applied bias.
Acknowledgements The author would like to thank F. Altmann, L. Berthold and I. Sch€ ulke from the Fraunhofer IWMH for the TEM preparation and analysis.
References [1] Streit D, Lai R, Oki A, Guitierrez-Aiteken. Proceedings of 14th Indium Phosphide and Related Materials Conference, Stockholm. 2002, pp. 11–14. [2] Tessmann A, Leuther A, Massler H, Reinert W, Schw€ orer C, Dammann M, et al. Third ESA Workshop on Millimetre Wave Technology and Applications, Espo, 2003. pp. 317–322. [3] Dammann M, Leuther A, Benkhelifa F, Feltgen T, Jantz W. Reliability and degradation mechanism of AlGaAs/ InGaAs and InAlAs/InGaAs HEMTs. Phys Stat Sol (a) 2003;1:81–6.
M. Dammann et al. / Microelectronics Reliability 44 (2004) 939–943 [4] Leuther A, Tessmann A, Dammann M, Reinert W, Schlechtweg M, Mikulla M, et al. 15th Indium Phosphide and Related Materials Conference, Santa Barbara. 2003, pp. 215–218. [5] Meneghesso G, Massari G, Buttari D, Bortoletto A, Maretto M, Zanoni E. DC and pulsed measurements of on-state breakdown voltage in GaAs MESFETs and InPbased HEMTs. Microelectr Reliab 1999;39:1759–63. [6] Marsetz W, Dammann M, Kawashima H, R€ udiger J, Matthes B, H€ ulsmann A, et al. 28th European Microwave Conference, Amsterdam. 1998, pp. 439–442. [7] Chou YC, Leung D, Lai R, Grundbacher R, Barsky M, Tsai R, et al. Indium Phosphide and Related Materials Conference, Stockholm. 2002, pp. 365-368.
943
[8] Wakita AS, Rohdin H, Su C-Y, Moll N, Nagy A, Robbins VM. Indium Phosphide and Related Materials Conference, Santa Barbara, 1997,Cape Cod, pp. 376–379. [9] Chou SY, Antoniadis DA. Relationship between measured and intrinsic transconductance of FETs. IEEE Trans Electr Dev 1987;ED-34:448–50. [10] Bayens Y, Monolithic microwave integrated circuits using GaAs and InP based heterojunction field-effect transistors. Ph.D. thesis. Katholieke Universiteit Leuven, 1996. [11] Quay R. Analysis and simulation of high electron mobility transistors. Ph.D. thesis. Technische Universit€at Wien, Aachen: Shaker Verlag, 2002.