- Email: [email protected]
Reliability of ultra thin oxide and nitride films in the 1 nm to 2 nm range
ELSEVIER
Microelectronic Engineering 48 (1999) 51-54 www.elsevier.nl/locate/mee
R e l i a b i l i t y o f U l t r a T h i n O x i d e a n d N i t r i d e F i l m s in t h e 1 n m to 2 n m Range B. Yuwono a, T. Schloesser a, A. Gschwandtner a, G. Innertsberger a, A. GrassP, A. Olbrich a and W.H. Krautschneider b aInfineon Technologies, Otto-Hahn-Ring 6, 81739 Munich, G e r m a n y e-mail: [email protected], [email protected] bTU Hamburg-Harburg, Technische Elektronik & Bildverarbeitung, Eissendorfer Str. 38, 21073 Hamburg, G e r m a n y e-mail: [email protected]
The scaled-down MOSFETs of the 16 Gbit generation and beyond will require a gate dielectric thickness less t h a n 2 nm. Reliability of ultra thin dielectrics were investigated in DC and AC stress at room and elevated temperatures.
1. I N T R O D U C T I O N
The scaled-down MOSFETs of the 16 Gbit generation and beyond will require a gate dielectric thickness less t h a n 2 n m [1]. In this paper, results will be presented about the reliability of ultra thin dielectric films (< 2nm) in terms of breakdown behavior, their homogeneity and reproducibility and their stability w h e n stressed by DC and AC voltages at room and elevated temperatures. It will be shown t h a t ultra thin oxide, nitrided oxide, oxynitride and nitride films m a y be suited for high Gigabit applications.
the polysilicon layer (thickness: 400 nm, phosphorus doped 5.1020 cm "3) were performed in a hot cluster tool in order to avoid exposure to room air. This procedure precludes any growth of native oxide, so t h a t the total thickness of the gate dielectric can be exactly controlled. Four different types of dielectric films were produced by rapid thermal processing (800°C to 1000°C, 5 sec. to 10 sec.): Thermal oxide, nitrided oxide, oxynitride and nitride. The dielectric film thicknesses were in the range from 1.5 n m to 2 nm. After deposition of an interlevel dielectric (thickness 1750 nm), the wafers were annealed for 10 sec. at 1072°C.
2. SAMPLE F A B R I C A T I O N 3. BREAKDOWN B E H A V I O U R
For our experiments we used MOS capacitors processed on a n-type substrate doped with antimony (20 mOhm-cm). A HF vapor preclean, the processing of the ultra thin dielectric films and the deposition of
DC stressing caused a soft breakdown with a modest current increase (Fig. 1). Extrapolation of the breakdown time TaD (VDc) data shows for a voltage less t h a n 2 V a
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S01 67-9317(99)00336-6
52
B. Yuwono et al. / Microelectronic Engineering 48 (1999) 5 1 - 5 4
lifetime exceeding ten years (Fig. 2). This will provide a very good margin at the expected m a x i m u m operation voltage of 1.2 V for the 16 Gbit generation [1]. After soft breakdown, the current level has increased by a factor of about five to ten and exhibits a significant current noise (Fig. 1). Our samples did not show a major change of the general shape of the current voltage characteristics after stress and soft breakdown (Fig. 4). The breakdown charge QBD of the ultra thin dielectrics exponentially increases with decreasing stress voltage (Fig. 3). F u r t h e r stress experiments were carried out using an AC stress voltage (duty cycle 1:1, VMAX = + 4 V). AC stress was not more detrimental t h a n DC stress. The change of the current voltage behavior of the MOS capacitors after DC and after AC stress was similar (Fig. 5).
4. R E P R O D U C I B I L I T Y
The current voltage characteristics of the MOS capacitors with ultra thin oxide films showed a significant spread across a wafer (Fig. 6). The gate area of the samples was 10 ~m 2. TEM cross sections show some thickness variations of the oxide film t h a t may be generated in the beginning of the oxidation [2]. But, these variations cannot sufficiently explain the data spread. For further analysis, Conducting Atomic Force Microscopy [3] was used to m e a s u r e the surface topography and local current distribution (Fig. 7). Local areas of significantly greater current densities were found that m a y control the current across the dielectric films. We observed t h a t our nitrided oxide (Fig. 8a), oxynitride (Fig. 8b) and nitride (Fig. 8c) films showed a significantly smaller data spread corresponding with a better uniformity of the film on a microscopic scale. This m a y be
caused by the deposition of the nitride with a low pressure in the hot cluster tool. Stressing at T = 140°C increases only very slightly the impact of stress on the current voltage behavior (Fig. 9).
5. C O N C L U S I O N Because of the exponential increase of the breakdown charge QBD at reduced gate voltages, it can be expected t h a t MOS transistors of the 16 Gbit generation with ultra thin dielectric gate films will meet the 10 years reliability specifications. A problem m a y arise for the reproducibility of oxide because of relatively large variations of the tunneling current. Nitrided oxide, oxynitride and nitride films showed a much narrower distribution of the tunneling current. DC and AC stress affected the current voltage characteristics in a similar manner. After soft breakdown, the current increased by about one decade. Stressing at 140°C accelerated and intesified the stress only very slightly. In general, ultra thin dielectric films (thickness < 2 nm) m a y be usable for MOS transistors of the 16 Gbit generation and beyond.
REFERENCES
[1] Semiconductor Industry Association, Roadmap, 1997. [2] H.S. Momose et al., IEEE Trans. Electr. Dev., vol. 45, p. 691, 1998. [3] A. Olbrich et al., Proc. IRPS, p. 163, 1998.
B. Yuwono et al. I Microelectronic Engineering 48 (1999) 51-54
1E+10
80
~ 1E+9
50
.
~.?1E+8 1E+7 1E+6
20
+3.6V 60
~" 1E+IO re+0 I
,~,
, ...........
1E+0
i
,
,~
,
.
.
.
.
,
.
.
.
.
.
.
r
.
.
.
.
.
.
.
.
\
Lo nitride .
.
.
.
.
.
.
.
.
%'t
.
.
.
.
.
.
.
~.
0.1
• •
after 60 ks • •
•
•
II
k
o.1 .....:...-. mm m
• • •
I I
• •
•
•
1
0.0001
• •fresh 0.00001 . . . . . . . . . . . . . . . . . -I -0.5 0 0.5 %IV] 1 Fig. 4 I-V characteristicsof MOScapacitor with oxide (Tox=l.5 nm) before and after DC stress with V.,r,,=+3.5V for 60 000 sec. •
. . . .
0
,
u
0.01
1E+1
,
.......
0 1 2 3 4 Voc ~/] 5 Fig. 2 Timeto breakdownTBDat different DC stress voltag# for oxide and nitride (1.5 nm), nitrlded oxide end oxynitrlde (2 nm).
~
1E+8 '-~ 1E+7 o 1E+6 1E+5 • oxide 1E+4 ~ i m nitrlded oxideI 1E+3 El-oxynltrlde I
,
/ A oxynltride
1E+2 1E+1 1E+0
O 200 400 600 800TaD[a] 1000 Fig. 1 Current density of MOScapacitors during DC stress until soft breakdown occurs. Diele©trlc:oxide, Tox=t.5nm.
.
• nltridsd oxide
IE+3
30
.
"°xJd' l
1E+5 1E+4
90
.
.~oy.r:
53
1
2
3
4
VDC IV]
5
Fig. 3 Breakdowncharge in dependenceof the DC stress voltage. Dielectrics: s. Fig. 2.
100
z~" 10 ~ ~- after DC~st;es' . . . . .
aftar'AC-atre'$~ m
l'Fml I
"~ 0.010"1~:AA 0.001L F 0.000010"0001I
"•:A
ill-e_, •&
mmi
lille'*** •
• "
A¢ ••• &•
'"Imiiiiill" ~-×
0.1
4"
• eA¢fresl~•
0.000001 . . . . . . . . . . . . . . . . . . . -1 -0.5 O 0.5 Va IV] 1 Fig. 5 Comparison of impact of DC and AC stress on the i-V characteristics of oxide (Tox=l.5nm).
0.01
0.001
.
-1
.
.
.
.
-0.5
.
.
.
....
.
o
.
.
.
.
.
o.s %IV] 1
Fig. 5 Thin oxide films show a significant chip to chip variation of the I-V characterictics,Tox=l.5 nm.
54
B. Yuwono et al.
Microelectronic Engineering 48 (1999) 51-54
Topography
z[
Current image
[pA]
?!
Fig. 7 Topography and local currant dbtdbution of oxide ('[= = 1.8 nm) !l tin
-~"~ 0.1
nltrlded oxide (NO): 1.8 nm oxide: 800°C, 58
0.01
nitrlde: gO0°C' lOs
il~ ×,;i
ill;
iii
I'
o.oo,'1111|1
0"01 f 0.001
-0.5
0
0.5 Fig. 8a Small data spread is observed for the I-V characteristics of thin NO film, TNO=1.8 nm.
V G
[V'J
1
i 0.0001 ~ -1
1000 f
. . -0.5
.
. . 0
900°C, lOs . . 0.5 VG IV] 1
10 1 "3
10 0.1 0.01
0.1 Fig. 8c I nltride: 1.5 nm 1000°C, 10s
0.01 i 0.001 -1
iii i io|x,nltri':1,nm 8b
0.0001
-1
i =1''
-0.5
0.5
VG IV] I
i
,et eeO
01!!! 140°C +AC
,-
lii li* *il it*140°C 25°C •
•
0.001 ~ ., .i ., . i . . . ~ -1 .0.5 0 0.5 VG iV] 1 Fig. 9 Stressing at T=140°C (DC and AC) only slightly influences the I-V characteristics of oxide films (Tox=l.5 nm).
Microelectronic Engineering 48 (1999) 51-54 www.elsevier.nl/locate/mee
R e l i a b i l i t y o f U l t r a T h i n O x i d e a n d N i t r i d e F i l m s in t h e 1 n m to 2 n m Range B. Yuwono a, T. Schloesser a, A. Gschwandtner a, G. Innertsberger a, A. GrassP, A. Olbrich a and W.H. Krautschneider b aInfineon Technologies, Otto-Hahn-Ring 6, 81739 Munich, G e r m a n y e-mail: [email protected], [email protected] bTU Hamburg-Harburg, Technische Elektronik & Bildverarbeitung, Eissendorfer Str. 38, 21073 Hamburg, G e r m a n y e-mail: [email protected]
The scaled-down MOSFETs of the 16 Gbit generation and beyond will require a gate dielectric thickness less t h a n 2 nm. Reliability of ultra thin dielectrics were investigated in DC and AC stress at room and elevated temperatures.
1. I N T R O D U C T I O N
The scaled-down MOSFETs of the 16 Gbit generation and beyond will require a gate dielectric thickness less t h a n 2 n m [1]. In this paper, results will be presented about the reliability of ultra thin dielectric films (< 2nm) in terms of breakdown behavior, their homogeneity and reproducibility and their stability w h e n stressed by DC and AC voltages at room and elevated temperatures. It will be shown t h a t ultra thin oxide, nitrided oxide, oxynitride and nitride films m a y be suited for high Gigabit applications.
the polysilicon layer (thickness: 400 nm, phosphorus doped 5.1020 cm "3) were performed in a hot cluster tool in order to avoid exposure to room air. This procedure precludes any growth of native oxide, so t h a t the total thickness of the gate dielectric can be exactly controlled. Four different types of dielectric films were produced by rapid thermal processing (800°C to 1000°C, 5 sec. to 10 sec.): Thermal oxide, nitrided oxide, oxynitride and nitride. The dielectric film thicknesses were in the range from 1.5 n m to 2 nm. After deposition of an interlevel dielectric (thickness 1750 nm), the wafers were annealed for 10 sec. at 1072°C.
2. SAMPLE F A B R I C A T I O N 3. BREAKDOWN B E H A V I O U R
For our experiments we used MOS capacitors processed on a n-type substrate doped with antimony (20 mOhm-cm). A HF vapor preclean, the processing of the ultra thin dielectric films and the deposition of
DC stressing caused a soft breakdown with a modest current increase (Fig. 1). Extrapolation of the breakdown time TaD (VDc) data shows for a voltage less t h a n 2 V a
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S01 67-9317(99)00336-6
52
B. Yuwono et al. / Microelectronic Engineering 48 (1999) 5 1 - 5 4
lifetime exceeding ten years (Fig. 2). This will provide a very good margin at the expected m a x i m u m operation voltage of 1.2 V for the 16 Gbit generation [1]. After soft breakdown, the current level has increased by a factor of about five to ten and exhibits a significant current noise (Fig. 1). Our samples did not show a major change of the general shape of the current voltage characteristics after stress and soft breakdown (Fig. 4). The breakdown charge QBD of the ultra thin dielectrics exponentially increases with decreasing stress voltage (Fig. 3). F u r t h e r stress experiments were carried out using an AC stress voltage (duty cycle 1:1, VMAX = + 4 V). AC stress was not more detrimental t h a n DC stress. The change of the current voltage behavior of the MOS capacitors after DC and after AC stress was similar (Fig. 5).
4. R E P R O D U C I B I L I T Y
The current voltage characteristics of the MOS capacitors with ultra thin oxide films showed a significant spread across a wafer (Fig. 6). The gate area of the samples was 10 ~m 2. TEM cross sections show some thickness variations of the oxide film t h a t may be generated in the beginning of the oxidation [2]. But, these variations cannot sufficiently explain the data spread. For further analysis, Conducting Atomic Force Microscopy [3] was used to m e a s u r e the surface topography and local current distribution (Fig. 7). Local areas of significantly greater current densities were found that m a y control the current across the dielectric films. We observed t h a t our nitrided oxide (Fig. 8a), oxynitride (Fig. 8b) and nitride (Fig. 8c) films showed a significantly smaller data spread corresponding with a better uniformity of the film on a microscopic scale. This m a y be
caused by the deposition of the nitride with a low pressure in the hot cluster tool. Stressing at T = 140°C increases only very slightly the impact of stress on the current voltage behavior (Fig. 9).
5. C O N C L U S I O N Because of the exponential increase of the breakdown charge QBD at reduced gate voltages, it can be expected t h a t MOS transistors of the 16 Gbit generation with ultra thin dielectric gate films will meet the 10 years reliability specifications. A problem m a y arise for the reproducibility of oxide because of relatively large variations of the tunneling current. Nitrided oxide, oxynitride and nitride films showed a much narrower distribution of the tunneling current. DC and AC stress affected the current voltage characteristics in a similar manner. After soft breakdown, the current increased by about one decade. Stressing at 140°C accelerated and intesified the stress only very slightly. In general, ultra thin dielectric films (thickness < 2 nm) m a y be usable for MOS transistors of the 16 Gbit generation and beyond.
REFERENCES
[1] Semiconductor Industry Association, Roadmap, 1997. [2] H.S. Momose et al., IEEE Trans. Electr. Dev., vol. 45, p. 691, 1998. [3] A. Olbrich et al., Proc. IRPS, p. 163, 1998.
B. Yuwono et al. I Microelectronic Engineering 48 (1999) 51-54
1E+10
80
~ 1E+9
50
.
~.?1E+8 1E+7 1E+6
20
+3.6V 60
~" 1E+IO re+0 I
,~,
, ...........
1E+0
i
,
,~
,
.
.
.
.
,
.
.
.
.
.
.
r
.
.
.
.
.
.
.
.
\
Lo nitride .
.
.
.
.
.
.
.
.
%'t
.
.
.
.
.
.
.
~.
0.1
• •
after 60 ks • •
•
•
II
k
o.1 .....:...-. mm m
• • •
I I
• •
•
•
1
0.0001
• •fresh 0.00001 . . . . . . . . . . . . . . . . . -I -0.5 0 0.5 %IV] 1 Fig. 4 I-V characteristicsof MOScapacitor with oxide (Tox=l.5 nm) before and after DC stress with V.,r,,=+3.5V for 60 000 sec. •
. . . .
0
,
u
0.01
1E+1
,
.......
0 1 2 3 4 Voc ~/] 5 Fig. 2 Timeto breakdownTBDat different DC stress voltag# for oxide and nitride (1.5 nm), nitrlded oxide end oxynitrlde (2 nm).
~
1E+8 '-~ 1E+7 o 1E+6 1E+5 • oxide 1E+4 ~ i m nitrlded oxideI 1E+3 El-oxynltrlde I
,
/ A oxynltride
1E+2 1E+1 1E+0
O 200 400 600 800TaD[a] 1000 Fig. 1 Current density of MOScapacitors during DC stress until soft breakdown occurs. Diele©trlc:oxide, Tox=t.5nm.
.
• nltridsd oxide
IE+3
30
.
"°xJd' l
1E+5 1E+4
90
.
.~oy.r:
53
1
2
3
4
VDC IV]
5
Fig. 3 Breakdowncharge in dependenceof the DC stress voltage. Dielectrics: s. Fig. 2.
100
z~" 10 ~ ~- after DC~st;es' . . . . .
aftar'AC-atre'$~ m
l'Fml I
"~ 0.010"1~:AA 0.001L F 0.000010"0001I
"•:A
ill-e_, •&
mmi
lille'*** •
• "
A¢ ••• &•
'"Imiiiiill" ~-×
0.1
4"
• eA¢fresl~•
0.000001 . . . . . . . . . . . . . . . . . . . -1 -0.5 O 0.5 Va IV] 1 Fig. 5 Comparison of impact of DC and AC stress on the i-V characteristics of oxide (Tox=l.5nm).
0.01
0.001
.
-1
.
.
.
.
-0.5
.
.
.
....
.
o
.
.
.
.
.
o.s %IV] 1
Fig. 5 Thin oxide films show a significant chip to chip variation of the I-V characterictics,Tox=l.5 nm.
54
B. Yuwono et al.
Microelectronic Engineering 48 (1999) 51-54
Topography
z[
Current image
[pA]
?!
Fig. 7 Topography and local currant dbtdbution of oxide ('[= = 1.8 nm) !l tin
-~"~ 0.1
nltrlded oxide (NO): 1.8 nm oxide: 800°C, 58
0.01
nitrlde: gO0°C' lOs
il~ ×,;i
ill;
iii
I'
o.oo,'1111|1
0"01 f 0.001
-0.5
0
0.5 Fig. 8a Small data spread is observed for the I-V characteristics of thin NO film, TNO=1.8 nm.
V G
[V'J
1
i 0.0001 ~ -1
1000 f
. . -0.5
.
. . 0
900°C, lOs . . 0.5 VG IV] 1
10 1 "3
10 0.1 0.01
0.1 Fig. 8c I nltride: 1.5 nm 1000°C, 10s
0.01 i 0.001 -1
iii i io|x,nltri':1,nm 8b
0.0001
-1
i =1''
-0.5
0.5
VG IV] I
i
,et eeO
01!!! 140°C +AC
,-
lii li* *il it*140°C 25°C •
•
0.001 ~ ., .i ., . i . . . ~ -1 .0.5 0 0.5 VG iV] 1 Fig. 9 Stressing at T=140°C (DC and AC) only slightly influences the I-V characteristics of oxide films (Tox=l.5 nm).