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Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology
MR-11572; No of Pages 5 Microelectronics Reliability xxx (2015) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Introductory invited paper
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology H. Cai a,⁎, Y. Wang a, L.A.B. Naviner a, W.S. Zhao b,c a b c
Institut Mines-Télécom, Télécom ParisTech, LTCI-CNRS-UMR 5141, 46 rue Barrault, 75013 Paris, France IEF L'Institut d'Électronique Fondamentale, Univ Paris-Sud, CNRS 8622, 91405 Orsay, France School of Electronics and Information, Beihang University, Beijing, China
a r t i c l e
i n f o
Article history: Received 25 May 2015 Received in revised form 19 June 2015 Accepted 20 June 2015 Available online xxxx Keywords: Magnetic tunnel junction STT-MFF Reliability FDSOI Ultra wide voltage range
a b s t r a c t We investigate stochastic and deterministic reliability problems in the hybrid magnetic tunnel junction (MTJ)/ MOS circuit which is implemented with ultra thin body and buried oxide (UTBB) fully depleted silicon-oninsulator (FDSOI) technology. A spin torque transfer (STT) magnetic flip-flop (MFF) is designed with ultra wide voltage range, with 0.5 V to 1.2 V sense/read voltage, and 0.95 V to 2 V writing voltage, by using an industrial 28 nm design kit and a physics-based STT-MTJ compact model. MFF performance can be improved with forward body bias (FBB) technology. The reliability-aware study shows that variability induced read/write failure is more dominant compared with aging induced degradation. Reliability-aware design of STT-MFF is discussed by proper selection of operation voltage. © 2015 Elsevier Ltd. All rights reserved.
1. Introduction Magneto-electronics or spintronics based non-volatile memories have been well-developed based on the spin-torque effect. Among the three methods to switch magnetic tunnel junction (MTJ): field induced magnetization switching (FIMS), thermally assisted switching (TAS) and spin torque transfer (STT), STT-MTJ based circuit has low switching current and fast writing access, which features high power efficiency, speed and infinite endurance [1]. Non-volatile MRAM has been implemented with different supply voltages (Vdd is from 0.4 V to 2 V) [2–5]. Ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology has been proposed and validated in low power circuit design [6]. Transistors with flexible forward/reverse body bias (FBB/RBB) can bring power–speed improvement. On the other hand, ultra wide operation voltage range can be achieved to enhance overall performance. Previous reliability studies of STT-MTJ circuits (mainly designed with bulk-CMOS technology) focus on variability induced performance fluctuation or functional failure [7,8]. Aging mechanisms, such as hot carrier injection (HCI), negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB) can significantly degrade the performance parameters of integrated circuits [9,10]. Furthermore, aging mechanisms remain and even become worse in high-k metal-gate (HKMG) transistors in advanced nanometer CMOS nodes ⁎ Corresponding author. E-mail address: [email protected] (H. Cai).
[11]. Since the thin layer of SiO2 has been maintained in between the substrate and the high-k stack, whereas the substrate/dielectric interface did not change, NBTI and HCI are still the critical problems in HKMG technologies. For STT-MTJ circuits implemented with FDSOI technology, neither deterministic reliability issues nor stochastic variability has been discussed before. The remainder of this paper is organized as follows. Section 2 describes different reliability issues. In Section 3, a 28 nm STT-MFF (magnetic flip-flop) with ultra wide voltage range is proposed. Its nominal performances are simulated with full operation range (supply voltage). Reliability-aware consideration of this circuit is presented in Section 4. Finally, the conclusion is drawn in Section 5.
2. Reliability issues Scaling-down of technology improves hybrid MTJ/CMOS circuit performance (e.g., area, speed and power consumption). However, the hybrid circuits should meet reliability challenges including deterministic degradations for active devices (transistors) and stochastic effects for both passive and active devices. Reviewing the research of aging phenomena in CMOS technology, the main aging effects of deep submicron CMOS transistor include NBTI, HCI and TDDB [9,10]. NBTI and HCI can cause the generation of the interface traps which result in transistor parameters shift over time (e.g., threshold voltage (Vth)). The time dependence of Vth degradation can be represented by the power law equation: ΔVth = Atn [12].
http://dx.doi.org/10.1016/j.microrel.2015.06.023 0026-2714/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
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H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
operation fails to store data and sensing operation may erroneously cause unexpected switching. This produces circuit functional failure which can influence negatively the reliability of CMOS/MTJ circuits. 3. STT-MFF with ultra wide voltage range — nominal simulation
Fig. 1. An equivalent transistor SPICE model for aging mechanisms (HCI, NBTI, TDDB).
An equivalent transistor SPICE model (see Fig. 1) for aging estimation is presented in [13]. For HCI and NBTI effects, parameter degradation is modeled as Vth, mobility and output conductance degradation (ΔVth, ΔIu and ΔIg0 respectively). For TDDB phenomena, the traditional Ohmic model can build a current leakage path between transistor gate and source or drain diffusion. RGD and RGS are setup as variable resistors which can be used to represent soft-breakdown (SBD), which can induce parametric variations but not functional failure [14]. When the dielectric breakdown (hard-breakdown) occurs at MTJ oxide barrier, the lifetime for MTJ around 1 nm thick barrier can be estimated to 10 years (at 400 mV operating voltage) [8]. For TDDB in FDSOI transistors, the breakdown voltage is as high as 2.4 V [15]. Thus, we focus on HCI and NBTI induced Vth degradation in this work. Although the fabrication techniques have been greatly developed, parametric process variations can still shift circuit performance, which may cause functional failure. The variations mainly exist in lot-to-lot, wafer-to-wafer, die-to-die, as well as intra-die variation (within a die) [16]. From the view of IC designers, parametric process variations are induced by different physical independent phenomena. The variability source in FDSOI transistor includes gate line-edge roughness (LER), random dopant fluctuations (RDFs) and metal gate granularity (MGG). These variations can be represented by a deviation in the parameter mean of the designed circuit. Moreover, circuit functional failure can be caused by stochastic process variations. Fig. 2 shows the random fluctuation of the relatively small number of dopants and their discrete microscopic arrangement in the channel. RDF leads to significant variations in the threshold voltage. Transistors can have mutually independent Vth variation with respect to each other, regardless of their spatial location. On the other hand, as an essential building block in STT-MFF, MTJ suffers intrinsically stochastic degradation due to the thermal fluctuations of magnetization. Due to the deviations of oxide barrier thickness (tox), free layer thickness (tsl) and tunnel magnetoresistance (TMR) ratio, MTJ switching errors occur with high probability. Indeed, writing
Fig. 2. A general view of line edge roughness and random dopant fluctuations.
Firstly we review the basic structure of STT-MTJ. It is an oxide barrier (MgO) sandwiched by two ferromagnetic layers (CoFeB) (see Fig. 3) [17]. Owing to the TMR effect, the MTJ resistance (Rp or Rap) is determined by the corresponding magnetization orientation of the two FM layers: parallel (P) or anti-parallel (AP). The state of MTJ can be changed to opposite by using the Spin-Transfer Torque phenomenon. The high TMR ratio = (Rap-Rp)/Rp (e.g., N600% at room temperature [18]) allows its easy integration into traditional MOS circuits [19]. Previous low power MFFs are designed by cascading two complementary latches [2–5]. In order to enhance MFF latency and reliability, we propose a modified MFF architecture with sense amplifier based flip-flop (SAFF) [20][21]. Fig. 4 illustrates the schematic view of the proposed STT-MFF. It consists of a differential write block, a sense amplifier as an input stage, a latch stage and the feedback circuit which is used to store non-volatile data. The advantages of this architecture include: 1) sensing amplifier strengthens weak input signals and latch them to supply voltage. 2) The symmetrical structure provides equal out delay for both true and complementary outputs. 3) Forward body bias FDSOI transistors can benefit both fast operations and low power consumption. In normal flip-flop mode, signal FFen (flip-flop enable) is high. When clock makes a rising transition, the pre-charged sense-amplifier is used to sample the complementary input data. The operation principle of the STT-MFF non-volatile memory (NVM) mode contains non-volatile data writing, standby and data sensing. The writing mode is executed when clock signal is low, write enable wren is high and FFen (Flip-flop enable) is low. In order to enhance write current to ensure data storing operation, the transistor W/L ratios (transistor M25–M28) are significantly increased, e.g., the W/L of M25 equals to 500 nm/30 nm. Previous data stored in cross-coupled inverters can be stored into MTJs. In order to successfully save the data, a minimum of 40 μA write current is required. The sensing mode executes after STTMFF standby mode. The SA circuit is multiplexed to reload non-volatile data in MTJs. SEen switches on M5 and M6 to read the data stored in MTJs. M3 and M4 are off to avoid sensing input data. A SPICE compact model of STT-MTJ [7] is used, which integrates both static and dynamic behaviors of STT-MTJ. The proposed circuit has been designed with a 28 nm UTBB FDSOI process. Functional simulations are performed with Spectre simulator in Cadence analog design environment (ADE), Fig. 5 shows the waveform of simulated STT-MFF. The simulated nominal performance parameters are presented in Table 1. In order to minimize circuit area, minimum transistor length (30 nm) is used in this design. With 2 V forward body bias, MFF latency is improved with 15.3%. A tradeoff exists at active power (12%). FBB brings on extended operation range of FDSOI circuits. Furthermore, we
Fig. 3. The structure of STT-MTJ, MTJ is composed of three layers: two ferromagnetic layers sandwiched by a tunnel barrier layer [17].
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
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Fig. 4. The schematic view of STT-MFF. It is composed by a write block (transistor M25–M28), a sense amplifier as an input stage, a two-NAND based latch stage and the feedback circuit.
study the full operation voltage range of designed STT-MFF. Low Vt transistors (LVT) using n-well below nMOSFET and p-well below pMOSFET devices are used in this design, which significantly extend low voltage range. Fig. 6 shows the simulation results: where write operation voltage can be setup between 0.95 V and 2 V, and sensing circuit can be operated between 0.45 V and 1.2 V. An ultra wide voltage range is achieved in the designed STT-MFF. From Fig. 6, we find that MTJ circuits' write energy (~ pJ level) is higher than read energy (~ fJ level). Thus, low power design of STT-
MTJ sensing circuits cannot significantly reduce the total power consumption. 4. Reliability analysis of STT-MFF As illustrated in Section 3, the proposed ultra wide voltage range STT-MFF achieves attractive performance. However, deterministic effects and stochastic effects impact performance parameters, sometimes cause circuit functional failure. In this section, HCI, NBTI and parametric process variations in STT-MFF are studied. 4.1. Full range stochastic effect failure The parametric process variations of transistors and MTJ devices, as well as the stochastic behaviors of MTJ are evaluated by Cadence ADEXL, with 500 runs Monte-Carlo methods. The simulation is performed with 100 MHz clock (10 ns write duration). The stochastic effects of transistors and MTJs are included. Fig. 7 shows the failure probability for both writing and reading operations. Failure probability of MTJ writing error is high around the threshold switching condition (minimum 40 μA write current), whereas the failure probability of read error is dominant at low supply voltage of
Table 1 The simulated nominal performances of designed MFF, under 1 V supply voltage (both sensing and write voltages are 1 V) and 100 MHz clock frequency. FBB technology can enhance MFF latency performance with power tradeoff.
Fig. 5. The nominal functional simulation of STT-MFF. D and Q stand for flip-flop input and output. The different operation modes are selected by control signals (FF_en, we_en and SE_en).
Output latency (ps) Clock-Q delay (ps) Active power (μW)
No body bias
Forward body bias
53.4 59 11.35
45.2 50.1 12.71
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
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Fig. 6. MFF performance with full voltage range. a. Clock to output latency. b. Write energy consumption. c. Read/sensing energy consumption.
sensing circuits. The failure probability increases when sensing voltage is lower than 0.9 V and/or writing voltage is lower than 1.3 V. A reduced sensing voltage cannot save power, whereas leading to increased sensing failure probability. On the other hand, small writing voltage can decrease the current flow through MTJs. In this design, 40 μA write current is required. Thus, the functional failure of designed STT-MFF is highly dependent of operation voltage. Reliability should be highlighted when sensing voltage is lower than 0.9 V and/or writing voltage is lower than 1.3 V.
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Fig. 7. The failure probability distribution with different sensing and writing voltages (MTJ read/sensing failure and MTJ writing error). a. The sensing failure probability under full operation range investigation. A high writing voltage can ensure low failure probability. b. The writing error probability under full operation range investigation.
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4.2. Deterministic aging effects Aging simulations are performed based on equivalent transistor SPICE model (see Fig. 1). It was experienced that both HCI and NBTI are strongly dependent on Vg. We choose the worst condition of transistor biasing, with Vdd-read = 1.2 V and Vdd-write = 2 V. Fig. 8 shows MRAM performance clock-to-output delay (Tclk-q) due to Vth shift. Considering
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Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
NBTI induced degradation, MRAM latency is not sensitive to NBTI mechanism due to the small Vth degradation (~10 mV@108 s aging node). The worst case degradation of the HCI occurs when transistor drain and gate transistor voltages are identical Vg = Vd. Transistor M7 and M8 are in the worst case of HCI degradation. From Fig. 7, it can be noticed that HCI induced additional latency is obvious from 106 s. HCI induced Tclk-q degradation is only 0.6% at 108 s aging node. The degradations in other operation voltage are lower than this worst case. In this design, aging induced degradation can be well alleviated by transistors with forward bias [9,10]. Thus, in the proposed STT-MFF circuits, deterministic aging effects (NBTI and HCI) only induce slight performance degradations, which are not dominant compared to stochastic variability. Both deterministic aging effects and stochastic variability can be alleviated by careful design of STT-MFF. 5. Conclusion Variability-aware and aging-aware analysis of STT-MRAM has been performed in this paper. 28 nm FDSOI devices achieve speed boost in ultra wide voltage range performance of STT-MFF. We find that low power design of STT-MTJ sensing circuits cannot significantly reduce the total power consumption where writing circuits are dominant. Variability induced failure problems are more dominant compared to aging induced degradation. The failure probability of STT-MFF is highly dependent of operation condition. Reliability-aware design of STT-MFF is discussed by proper selection of supply voltage. Acknowledgments This work is supported by a public grant overseen by the French National Research Agency (ANR) as part of the Investissement d'Avenir program, through the ANCD2, project funded by the IDEX Paris-Saclay, ANR-11-IDEX-0003-02.
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[2] K. Ryu, et al., A magnetic tunnel junction based zero standby leakage current retention flip-flop, IEEE Trans. VLSI 20 (11) (2012) 2044–2053. [3] D. Chabi, et al., Ultra low power magnetic flip-flop based on checkpointing/power gating and self-enable mechanisms, IEEE Trans. CAS-I 60 (6) (2014) 1755–1765. [4] W.S. Zhao, et al., Design considerations and strategies for high-reliable STT-MRAM, Microelectron. Reliab. 51 (2011) 1454–1458. [5] Kazi, et al., A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write, Proc in IEEE NEWCAS 2013, pp. 1–4. [6] T. Skotnicki, et al., Innovative materials, devices, and CMOS technologies for lowpower mobile multimedia, IEEE Trans. Electron Devices 55 (1) (2008) 96–130. [7] W.S. Zhao, et al., Failure and reliability analysis of STT-MRAM, Microelectron. Reliab. 52 (2012) 1848–1852. [8] Y. Wang, et al., Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses, Microelectron. Reliab. 54 (2014) 1774–1778. [9] H. Cai, et al., Reliability aware design of low power continuous-time sigma-delta modulator, Microelectron. Reliab. 51 (2011) 1449–1453. [10] H. Cai, et al., Cross-layer investigation of continuous-time sigma-delta modulator under aging effects, Microelectron. Reliab. 55 (2015) 645–653. [11] E. Maricau, et al., Analog circuit reliability in sub-32 nanometer CMOS: analysis and mitigation, Proc in DATE 2011, pp. 1–6. [12] T. Ishigaki, et al., Effects of device structure and back biasing on HCI and NBTI in silicon-on-thin-BOX (SOTB) CMOSFET, IEEE Trans. Electron Devices 58 (4) (2011) 1197–1204. [13] E. Maricau, G. Gielen, Computer-aided analog circuit design for reliability in nanometer CMOS, IEEE Trans. Emerg. Sel. Top. Circ. Syst. 1 (1) (2011) 50–58. [14] H. Wang, et al., Impact of random soft oxide breakdown on SRAM energy/delay drift, IEEE Trans. Device Mater. Reliab. 7 (4) (2007) 581–591. [15] X. Federspiel, et al., 28 nm node bulk vs FDSOI reliability comparison, Proc in IEEE IPRS, 2012 (3B.1.1–3B.1.4). [16] H. Cai, et al., A hierarchical reliability simulation methodology for AMS integrated circuits and systems, J. Low Power Electron. 8 (5) (2012) 697–705. [17] M. Julliere, et al., Tunneling between ferromagnetic films, Phys. Lett. A 54 (3) (1975) 225–226. [18] S. Ikeda, et al., Tunnel magnetoresistance of 604% at 300 k by suppression of ta diffusion in CoFeBMgOCoFeB pseudospin-valves annealed at high temperature, Appl. Phys. Lett. 93 (8) (2008) (082508-082508-3). [19] Y. Zhang, et al., Compact modeling of perpendicular-anisotropy CoFeB/MgO magnetic tunnel junctions, IEEE Trans. Electron Devices 59 (3) (2012) 819–826. [20] D. Markovic, et al., Analysis and design of low energy flip-flops, Proc in ISLPED 2001, pp. 52–55. [21] H. Cai, et al., Multiplexing Sense Amplifier Based Magnetic Flip-Flop in 28nm FDSOI Technology, Nanotechnology, IEEE Transactions on 99 (2012)http://dx.doi.org/10. 1109/TNANO.2015.2438017 vol.PP, no.99, pp.1.
References [1] C. Chappert, A. Fert, F.N. Van Dau, The emergence of spin electronics in data storage, Nat. Mater. 6 (2007) 813–823.
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Introductory invited paper
Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology H. Cai a,⁎, Y. Wang a, L.A.B. Naviner a, W.S. Zhao b,c a b c
Institut Mines-Télécom, Télécom ParisTech, LTCI-CNRS-UMR 5141, 46 rue Barrault, 75013 Paris, France IEF L'Institut d'Électronique Fondamentale, Univ Paris-Sud, CNRS 8622, 91405 Orsay, France School of Electronics and Information, Beihang University, Beijing, China
a r t i c l e
i n f o
Article history: Received 25 May 2015 Received in revised form 19 June 2015 Accepted 20 June 2015 Available online xxxx Keywords: Magnetic tunnel junction STT-MFF Reliability FDSOI Ultra wide voltage range
a b s t r a c t We investigate stochastic and deterministic reliability problems in the hybrid magnetic tunnel junction (MTJ)/ MOS circuit which is implemented with ultra thin body and buried oxide (UTBB) fully depleted silicon-oninsulator (FDSOI) technology. A spin torque transfer (STT) magnetic flip-flop (MFF) is designed with ultra wide voltage range, with 0.5 V to 1.2 V sense/read voltage, and 0.95 V to 2 V writing voltage, by using an industrial 28 nm design kit and a physics-based STT-MTJ compact model. MFF performance can be improved with forward body bias (FBB) technology. The reliability-aware study shows that variability induced read/write failure is more dominant compared with aging induced degradation. Reliability-aware design of STT-MFF is discussed by proper selection of operation voltage. © 2015 Elsevier Ltd. All rights reserved.
1. Introduction Magneto-electronics or spintronics based non-volatile memories have been well-developed based on the spin-torque effect. Among the three methods to switch magnetic tunnel junction (MTJ): field induced magnetization switching (FIMS), thermally assisted switching (TAS) and spin torque transfer (STT), STT-MTJ based circuit has low switching current and fast writing access, which features high power efficiency, speed and infinite endurance [1]. Non-volatile MRAM has been implemented with different supply voltages (Vdd is from 0.4 V to 2 V) [2–5]. Ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology has been proposed and validated in low power circuit design [6]. Transistors with flexible forward/reverse body bias (FBB/RBB) can bring power–speed improvement. On the other hand, ultra wide operation voltage range can be achieved to enhance overall performance. Previous reliability studies of STT-MTJ circuits (mainly designed with bulk-CMOS technology) focus on variability induced performance fluctuation or functional failure [7,8]. Aging mechanisms, such as hot carrier injection (HCI), negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB) can significantly degrade the performance parameters of integrated circuits [9,10]. Furthermore, aging mechanisms remain and even become worse in high-k metal-gate (HKMG) transistors in advanced nanometer CMOS nodes ⁎ Corresponding author. E-mail address: [email protected] (H. Cai).
[11]. Since the thin layer of SiO2 has been maintained in between the substrate and the high-k stack, whereas the substrate/dielectric interface did not change, NBTI and HCI are still the critical problems in HKMG technologies. For STT-MTJ circuits implemented with FDSOI technology, neither deterministic reliability issues nor stochastic variability has been discussed before. The remainder of this paper is organized as follows. Section 2 describes different reliability issues. In Section 3, a 28 nm STT-MFF (magnetic flip-flop) with ultra wide voltage range is proposed. Its nominal performances are simulated with full operation range (supply voltage). Reliability-aware consideration of this circuit is presented in Section 4. Finally, the conclusion is drawn in Section 5.
2. Reliability issues Scaling-down of technology improves hybrid MTJ/CMOS circuit performance (e.g., area, speed and power consumption). However, the hybrid circuits should meet reliability challenges including deterministic degradations for active devices (transistors) and stochastic effects for both passive and active devices. Reviewing the research of aging phenomena in CMOS technology, the main aging effects of deep submicron CMOS transistor include NBTI, HCI and TDDB [9,10]. NBTI and HCI can cause the generation of the interface traps which result in transistor parameters shift over time (e.g., threshold voltage (Vth)). The time dependence of Vth degradation can be represented by the power law equation: ΔVth = Atn [12].
http://dx.doi.org/10.1016/j.microrel.2015.06.023 0026-2714/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
2
H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
operation fails to store data and sensing operation may erroneously cause unexpected switching. This produces circuit functional failure which can influence negatively the reliability of CMOS/MTJ circuits. 3. STT-MFF with ultra wide voltage range — nominal simulation
Fig. 1. An equivalent transistor SPICE model for aging mechanisms (HCI, NBTI, TDDB).
An equivalent transistor SPICE model (see Fig. 1) for aging estimation is presented in [13]. For HCI and NBTI effects, parameter degradation is modeled as Vth, mobility and output conductance degradation (ΔVth, ΔIu and ΔIg0 respectively). For TDDB phenomena, the traditional Ohmic model can build a current leakage path between transistor gate and source or drain diffusion. RGD and RGS are setup as variable resistors which can be used to represent soft-breakdown (SBD), which can induce parametric variations but not functional failure [14]. When the dielectric breakdown (hard-breakdown) occurs at MTJ oxide barrier, the lifetime for MTJ around 1 nm thick barrier can be estimated to 10 years (at 400 mV operating voltage) [8]. For TDDB in FDSOI transistors, the breakdown voltage is as high as 2.4 V [15]. Thus, we focus on HCI and NBTI induced Vth degradation in this work. Although the fabrication techniques have been greatly developed, parametric process variations can still shift circuit performance, which may cause functional failure. The variations mainly exist in lot-to-lot, wafer-to-wafer, die-to-die, as well as intra-die variation (within a die) [16]. From the view of IC designers, parametric process variations are induced by different physical independent phenomena. The variability source in FDSOI transistor includes gate line-edge roughness (LER), random dopant fluctuations (RDFs) and metal gate granularity (MGG). These variations can be represented by a deviation in the parameter mean of the designed circuit. Moreover, circuit functional failure can be caused by stochastic process variations. Fig. 2 shows the random fluctuation of the relatively small number of dopants and their discrete microscopic arrangement in the channel. RDF leads to significant variations in the threshold voltage. Transistors can have mutually independent Vth variation with respect to each other, regardless of their spatial location. On the other hand, as an essential building block in STT-MFF, MTJ suffers intrinsically stochastic degradation due to the thermal fluctuations of magnetization. Due to the deviations of oxide barrier thickness (tox), free layer thickness (tsl) and tunnel magnetoresistance (TMR) ratio, MTJ switching errors occur with high probability. Indeed, writing
Fig. 2. A general view of line edge roughness and random dopant fluctuations.
Firstly we review the basic structure of STT-MTJ. It is an oxide barrier (MgO) sandwiched by two ferromagnetic layers (CoFeB) (see Fig. 3) [17]. Owing to the TMR effect, the MTJ resistance (Rp or Rap) is determined by the corresponding magnetization orientation of the two FM layers: parallel (P) or anti-parallel (AP). The state of MTJ can be changed to opposite by using the Spin-Transfer Torque phenomenon. The high TMR ratio = (Rap-Rp)/Rp (e.g., N600% at room temperature [18]) allows its easy integration into traditional MOS circuits [19]. Previous low power MFFs are designed by cascading two complementary latches [2–5]. In order to enhance MFF latency and reliability, we propose a modified MFF architecture with sense amplifier based flip-flop (SAFF) [20][21]. Fig. 4 illustrates the schematic view of the proposed STT-MFF. It consists of a differential write block, a sense amplifier as an input stage, a latch stage and the feedback circuit which is used to store non-volatile data. The advantages of this architecture include: 1) sensing amplifier strengthens weak input signals and latch them to supply voltage. 2) The symmetrical structure provides equal out delay for both true and complementary outputs. 3) Forward body bias FDSOI transistors can benefit both fast operations and low power consumption. In normal flip-flop mode, signal FFen (flip-flop enable) is high. When clock makes a rising transition, the pre-charged sense-amplifier is used to sample the complementary input data. The operation principle of the STT-MFF non-volatile memory (NVM) mode contains non-volatile data writing, standby and data sensing. The writing mode is executed when clock signal is low, write enable wren is high and FFen (Flip-flop enable) is low. In order to enhance write current to ensure data storing operation, the transistor W/L ratios (transistor M25–M28) are significantly increased, e.g., the W/L of M25 equals to 500 nm/30 nm. Previous data stored in cross-coupled inverters can be stored into MTJs. In order to successfully save the data, a minimum of 40 μA write current is required. The sensing mode executes after STTMFF standby mode. The SA circuit is multiplexed to reload non-volatile data in MTJs. SEen switches on M5 and M6 to read the data stored in MTJs. M3 and M4 are off to avoid sensing input data. A SPICE compact model of STT-MTJ [7] is used, which integrates both static and dynamic behaviors of STT-MTJ. The proposed circuit has been designed with a 28 nm UTBB FDSOI process. Functional simulations are performed with Spectre simulator in Cadence analog design environment (ADE), Fig. 5 shows the waveform of simulated STT-MFF. The simulated nominal performance parameters are presented in Table 1. In order to minimize circuit area, minimum transistor length (30 nm) is used in this design. With 2 V forward body bias, MFF latency is improved with 15.3%. A tradeoff exists at active power (12%). FBB brings on extended operation range of FDSOI circuits. Furthermore, we
Fig. 3. The structure of STT-MTJ, MTJ is composed of three layers: two ferromagnetic layers sandwiched by a tunnel barrier layer [17].
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
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Fig. 4. The schematic view of STT-MFF. It is composed by a write block (transistor M25–M28), a sense amplifier as an input stage, a two-NAND based latch stage and the feedback circuit.
study the full operation voltage range of designed STT-MFF. Low Vt transistors (LVT) using n-well below nMOSFET and p-well below pMOSFET devices are used in this design, which significantly extend low voltage range. Fig. 6 shows the simulation results: where write operation voltage can be setup between 0.95 V and 2 V, and sensing circuit can be operated between 0.45 V and 1.2 V. An ultra wide voltage range is achieved in the designed STT-MFF. From Fig. 6, we find that MTJ circuits' write energy (~ pJ level) is higher than read energy (~ fJ level). Thus, low power design of STT-
MTJ sensing circuits cannot significantly reduce the total power consumption. 4. Reliability analysis of STT-MFF As illustrated in Section 3, the proposed ultra wide voltage range STT-MFF achieves attractive performance. However, deterministic effects and stochastic effects impact performance parameters, sometimes cause circuit functional failure. In this section, HCI, NBTI and parametric process variations in STT-MFF are studied. 4.1. Full range stochastic effect failure The parametric process variations of transistors and MTJ devices, as well as the stochastic behaviors of MTJ are evaluated by Cadence ADEXL, with 500 runs Monte-Carlo methods. The simulation is performed with 100 MHz clock (10 ns write duration). The stochastic effects of transistors and MTJs are included. Fig. 7 shows the failure probability for both writing and reading operations. Failure probability of MTJ writing error is high around the threshold switching condition (minimum 40 μA write current), whereas the failure probability of read error is dominant at low supply voltage of
Table 1 The simulated nominal performances of designed MFF, under 1 V supply voltage (both sensing and write voltages are 1 V) and 100 MHz clock frequency. FBB technology can enhance MFF latency performance with power tradeoff.
Fig. 5. The nominal functional simulation of STT-MFF. D and Q stand for flip-flop input and output. The different operation modes are selected by control signals (FF_en, we_en and SE_en).
Output latency (ps) Clock-Q delay (ps) Active power (μW)
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53.4 59 11.35
45.2 50.1 12.71
Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
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Fig. 6. MFF performance with full voltage range. a. Clock to output latency. b. Write energy consumption. c. Read/sensing energy consumption.
sensing circuits. The failure probability increases when sensing voltage is lower than 0.9 V and/or writing voltage is lower than 1.3 V. A reduced sensing voltage cannot save power, whereas leading to increased sensing failure probability. On the other hand, small writing voltage can decrease the current flow through MTJs. In this design, 40 μA write current is required. Thus, the functional failure of designed STT-MFF is highly dependent of operation voltage. Reliability should be highlighted when sensing voltage is lower than 0.9 V and/or writing voltage is lower than 1.3 V.
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Fig. 7. The failure probability distribution with different sensing and writing voltages (MTJ read/sensing failure and MTJ writing error). a. The sensing failure probability under full operation range investigation. A high writing voltage can ensure low failure probability. b. The writing error probability under full operation range investigation.
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4.2. Deterministic aging effects Aging simulations are performed based on equivalent transistor SPICE model (see Fig. 1). It was experienced that both HCI and NBTI are strongly dependent on Vg. We choose the worst condition of transistor biasing, with Vdd-read = 1.2 V and Vdd-write = 2 V. Fig. 8 shows MRAM performance clock-to-output delay (Tclk-q) due to Vth shift. Considering
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Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023
H. Cai et al. / Microelectronics Reliability xxx (2015) xxx–xxx
NBTI induced degradation, MRAM latency is not sensitive to NBTI mechanism due to the small Vth degradation (~10 mV@108 s aging node). The worst case degradation of the HCI occurs when transistor drain and gate transistor voltages are identical Vg = Vd. Transistor M7 and M8 are in the worst case of HCI degradation. From Fig. 7, it can be noticed that HCI induced additional latency is obvious from 106 s. HCI induced Tclk-q degradation is only 0.6% at 108 s aging node. The degradations in other operation voltage are lower than this worst case. In this design, aging induced degradation can be well alleviated by transistors with forward bias [9,10]. Thus, in the proposed STT-MFF circuits, deterministic aging effects (NBTI and HCI) only induce slight performance degradations, which are not dominant compared to stochastic variability. Both deterministic aging effects and stochastic variability can be alleviated by careful design of STT-MFF. 5. Conclusion Variability-aware and aging-aware analysis of STT-MRAM has been performed in this paper. 28 nm FDSOI devices achieve speed boost in ultra wide voltage range performance of STT-MFF. We find that low power design of STT-MTJ sensing circuits cannot significantly reduce the total power consumption where writing circuits are dominant. Variability induced failure problems are more dominant compared to aging induced degradation. The failure probability of STT-MFF is highly dependent of operation condition. Reliability-aware design of STT-MFF is discussed by proper selection of supply voltage. Acknowledgments This work is supported by a public grant overseen by the French National Research Agency (ANR) as part of the Investissement d'Avenir program, through the ANCD2, project funded by the IDEX Paris-Saclay, ANR-11-IDEX-0003-02.
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Please cite this article as: H. Cai, et al., Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.06.023