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Optimization of the interconnect resistance contribution for STT-MRAM technology
Journal Pre-proof Optimization of the interconnect resistance contribution for STT-MRAM technology Hemant Dixit, Sudarshan Narayanan, Bert Pfefferling, Johannes Mueller PII:
S0026-2692(19)30482-3
DOI:
https://doi.org/10.1016/j.mejo.2019.104663
Reference:
MEJ 104663
To appear in:
Microelectronics Journal
Received Date: 6 June 2019 Revised Date:
4 October 2019
Accepted Date: 13 November 2019
Please cite this article as: H. Dixit, S. Narayanan, B. Pfefferling, J. Mueller, Optimization of the interconnect resistance contribution for STT-MRAM technology, Microelectronics Journal (2019), doi: https://doi.org/10.1016/j.mejo.2019.104663. This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. © 2019 Published by Elsevier Ltd.
Optimization of the Interconnect Resistance Contribution for STT-MRAM Technology Hemant Dixit*, Sudarshan Narayanan
Bert Pfefferling, Johannes Mueller
GLOBALFOUNDRIES Inc. 400 Stone Break Rd Extension, Malta, NY, USA *[email protected]
GLOBALFOUNDRIES Inc. Wilschdorfer Landstrasse 101, 01109 Dresden, Germany
Abstract— STT-MRAM has emerged as versatile memory technology, capable of serving a broad range of memory applications. A key figure of merit for the STT-MRAM device is the tunneling magnetoresistance ratio (TMR), which distinguishes between the high resistance (“Off”) and low resistance (“On”) state. In an Integrated Circuit (IC), the MRAM device is fabricated in back-end-of-line process and is powered using a MRAM Vertical Interconnect Access (M-VIA) structure. The series resistance from M-VIA structure, however, adversely impacts the TMR reducing the sense margin. Thus, to improve the TMR/sense margin of MRAM device, reduction of series M-VIA resistance is. We present a combination of ab-initio & TCAD simulations to estimate the M-VIA resistance contributions. Advanced interconnect metals, which include Co, Ru and W, are studied with TiN as barrier metal. The role of barrier metal and geometry is systematically investigated. These simulations provide potential pathways to reduce the M-VIA resistance contributions, allowing for a high density MRAM array. Keywords—STT-MRAM, TMR, VIA, Interconnects
I. INTRODUCTION Currently, perpendicular Magnetic Tunnel Junction (pMTJ) based Spin-Transfer Torque (STT) Magnetoresistive Random Access Memories (MRAM), which enables low power and high-speed operation, are being developed and are entering the commercialization phase for both stand-alone and embedded applications [1]–[3]. In its basic configuration MRAM bit-cell consists of 1 transistor and 1 MTJ, and is integrated as a back-end-of-the-line device in between metal layers, as illustrated in Figure 1. The MTJ consists of two ferromagnetic layers separated by an oxide which is typically MgO. Among these two ferromagnetic layers, one has fixed orientation of the magnetic moment – known as reference layer and the other layer can freely switch its magnetic orientation between parallel and anti-parallel configuration with respect to the reference layer orientation. Now, when an electric current flows through the MTJ, it sees either low or high resistance depending on the parallel or antiparallel orientation of the free layer. This magnetoresistance effect is harvested in MRAM technology and the information is stored as a high (RAP) or low (RP) resistance state based on the relative magnetization orientations of the free layer and reference layer. Tunnel Magnetoresistance Ratio (TMR) is a measure that is used to distinguish the RAP and RP states from each other and is defined as follows:
Fig. 1 a) BEOL integration of MTJ element and M-VIA structure underneath b) the M-VIA contributes a series resistance to the MTJ.
The TMR is thus a key figure of merit for MTJ devices and critical to determine its performance. The stored information in MRAM bit-cell can be read using either voltage or current sensing scheme. In case of current sensing scheme, current flows through MTJ and the MRAM bit-cell current is compared to a reference current, IREF, using a current sense amplifier (CSA). The MRAM bit-cell is in low resistance state (RP) if ICELL > IREF, and the CSA outputs a “0”. Otherwise, the MRAM bit-cell stores high resistance state (RAP) and the CSA outputs a “1”. If the value of high and low resistance states are close to each other (low TMR case), it can interfere with the sense margin of CSA. This naturally leads to a read failure and incorrect decisions. Thus, large TMR is often necessary to increase the sense margin and typical values of TMR lies between 150-175% for reliable memory operation. Although, TMR is primarily an MTJ property which originates from ferromagnet-oxide interface, there are also other additional external factors that need to be considered at a circuit level. In an integrated circuit, when MTJ element is incorporated as BEOL device, the series resistance from the metal interconnect, known as M-VIA plugs, reduces the effective TMR values. Figure 2, illustrates a decreasing TMR as a function of increasing M-VIA series resistance offered by the metal interconnects. It is observed that, a series resistance of 100 Ω can reduce the TMR by up to ~5%, with RP of 2.5 kΩ and TMR of 175%. This is especially important for advanced technology nodes where the interconnect dimensions are
immersed into the inter-layer dielectric (ILD) material in an IC. In this work, our goal is to establish the resistance dependence on the M-VIA CD. For this purpose, we run couple of process splits. The first one deals with BCD variation between 40-65 nm (in steps of 5 nm) and the second one deals with M-VIA
Fig. 2. TMR reduction as a function of increasing MVIA resistance.
shrinking but their resistance is growing due to quantum size effects. On the other hand, for higher density of MTJ elements – a smaller M-VIA is desired. In this article, we present TCAD simulations for evaluating the series resistance offered by a typical M-VIA structure in BEOL. We work with advanced interconnect metals that include Co, Ru and W [4]. First, we investigate the impact of M-VIA critical dimensions (CD) on its resistance and later discuss the role of TiN barrier metal. The simulation results provides useful physical insights for the design of experiment
Fig. 3. M-VIA structure (left) and its vertical cross section (right) used in TCAD simulations
to optimize the M-VIA series resistance. Further, these effort help to improve the scaling, or density of the MTJ elements in the MRAM array. II. M-VIA STRUCTURE AND RESISTANCE CONTRIBUTIONS The M-VIA structures were generated using Sentaurus tool SProcess and the device simulations were completed using Sdevice [5]. The M-VIA structure considered in this study is illustrated in Figure 3. It consists of cylindrical metal plug with a top and bottom CD (TCD and BCD) connected together with a constant taper angle of about 84°. The metal plug is surrounded by a layer of barrier metal used to prevent the electromigration. The electromigration concern also dictates how thin the barrier metal can be and typically these thickness ranges between 5-10 nm thick. The M-VIA structure is then
Fig. 4. Thickness dependent resistivity of Co, Ru and W metals.
height variations between 20 – 140 nm (in steps of 20 nm) representative of the separation between different metal levels. Finally, the barrier thickness is also varied between 5-10 nm in steps of 2.5 nm each. We choose to work with advanced metallization that include Co, Ru and W metals, with TiN as the barrier metal. In order to accurately evaluate the total resistance offered by the M-VIA structure, two important factors need to be considered – the contribution of thickness dependent resistance of each metal layer and the contribution from metal-metal interface resistivity. Firstly, it is well-established that the interconnect resistivity increases exponentially with decreasing interconnect dimensions due to quantum size effects and scattering mechanisms. Furthermore, the processing conditions also affect the blanket resistivity of individual metal owing to the traces of impurities left during deposition. Here, we have used well known Mayadas-Shatzkes expression [6] to evaluate the resistivity scaling as a function of decreasing metal thickness. We observe that an average grain-boundary reflection coefficient of 0.58, 0.50 and 0.51 provide best fit for the hardware data, for Co, W and Ru, respectively [7]–[10]. It should be noted that the bulk resistivity values are, however, measured from blanket films pertaining to the process conditions and adopted in the scaling. The resistivity variations of all these metals are shown in Figure 4. An average resistivity values of ~ 25, 15 & 48.4 µΩ-cm for Co, Ru and W, respectively, corresponding to the 45 nm thickness, are chosen to be input for the TCAD . Secondly, the metal-metal interfaces also contribute to the total resistance of M-VIA. In order to evaluate the interface resistance for metal/barrier
Fig. 5. Illustration of atomistic device used to calculate the interface resistivity between two metals using ab-initio DFT+NEGF framework.
interfaces, we used ab initio Density Functional Theory (DFT) and non-equilibrium Green’s Function (NEGF) approach [10], [11]. In this method a device configuration is constructed using atomistic geometry of the metals (see Figure 5), and later electron transport across the interface, from the left electrode to Metal TiN
Co 43.18×e-12 ( Ω-cm2)
Ru 25.11×e-12 ( Ω-cm2)
W 61.02×e-12 ( Ω-cm2)
Table 1. Calculated interface resistivity for metal/liner interface.
the right electrode, is evaluated as depicted in Figure 5. Since, in reality the interface structure can be polycrystalline or amorphous, we apply random fractional displacement to the Fig. 7. Total resistance as a function of the MVIA height at 40 nm BCD with 5 nm TiN barrier.
evaluate the CD dependence of resistivity at fixed barrier thickness. The calculated resistance values for Co, Ru & W plugs are listed in Table 2.
Fig. 6. Quasi Fermi Potential drop across the M-VIA structure.
interface atoms and thereby evaluate the averaged effect of interface resistance. The calculated values of Co, Ru, W/TiN interface resistance are listed in Table 1. III. IMPACT OF CRITICAL DIMENSIONS AND LINER METAL Sdevice TCAD simulations were performed to determine the quasi-Fermi potential across the M-VIA structure, after including thickness dependent bulk resistivity of metals and metal-metal interface resistivity as discussed in the previous section. Figure 6 shows a representative quasi-Fermi potential profile across M-VIA structure calculated using TCAD simulation. We observe a potential drop of ~ 68 % and ~ 32 % within the metal and liner region of the M-VIA plug, respectively. The resistance distribution indicate that both metal plug and liner significantly contribute to the total resistance. These knobs can be turned independently – for example, by reducing the liner thickness or by changing the MVIA metal fill – for resistance optimization. Thus we investigate both the above mentioned possibilities. First, we BCD (nm) 40 45 50 55 60 65
Co
Ru
W
53.34 Ω 42.00 Ω 33.92Ω 27.97 Ω 23.46 Ω 23.36 Ω
43.85 Ω 34.50 Ω 27.84 Ω 22.94 Ω 19.45 Ω 19.22 Ω
75.51 Ω 59.59 Ω 48.22 Ω 39.84 Ω 33.46 Ω 32.49 Ω
Table 2. Resistance impact of BCD variations on total M-VIA resistance, corresponding to the TiN liner thickness is 5 nm.
We observe that about 50% decrease in M-VIA resistance, by increasing BCD from 40 nm to 65 nm, is possible. The resistance evolution is, however, non-linear and the initial average slope of ~3 Ω/nm for W, flattens out beyond 60 nm of BCD - indicating that there will not be any significant scaling disadvantage. Similarly, we also evaluate the M-VIA resistance as a function of increasing M-VIA height between 20-140 nm and the results are shown in Figure 7. The graph indicates that the resistance difference between different metal is more pronounced at increased M-VIA heights (> 100 nm). Finally, we also calculate the impact of barrier thickness on the M-VIA resistance. For this purpose, barrier thickness of 5, 7.5 and 10 nm were studied. The calculated M-VIA resistance are shown
Fig. 8. Total resistance as a function of the TiN liner thickness.
in Figure 8. We observe almost linear dependence of M-VIA resistance on the barrier thickness and the resistance increases @ 2 Ω/nm for W and this slope is further decreased for Co and Ru, respectively.
IV. CONCLUSIONS We evaluated the series resistance contribution arising from M-VIA structures using a combination of ab-initio and TCAD simulations. Advanced BEOL metals interconnects and
corresponding combinations of liner metals were systematically studied. The results indicate that both BCD and barrier thickness provide an independent control to optimize the M-VIA resistance. Our simulations results shows that 60 nm is the optimal choice for the M-VIA BCD and it further does not offer any significant advantage in terms of resistance reduction. Similarly, for the barrier metal thickness - 5 nm thick barrier metal is most appropriate to reduce the total MVIA resistance. Further reduction in the barrier thickness may lead to electromigration issues. We also considered the M-VIA height variation and the results indicate that the M-VIA resistance monotonically decreases with decreasing height. The average slope is about 0.5 Ω/nm for W and is the slope is further reduced for Co and Ru, respectively. These finding may lead to potential pathways to reduce the series resistance of MVIA and thereby improve the STT-MRAM density in advanced technology nodes for embedded memory applications. ACKNOWLEDGMENT We thank Konstantin Korablev, Reshma Krishnan for useful discussion related to this work. REFERENCES [1]
K. Lee and S. H. Kang, “Development of Embedded STT-MRAM for Mobile System-on-Chips,” IEEE Trans. Magn., vol. 47, no. 1, pp. 131– 136, Jan. 2011.
[2]
Y. J. Song et al., “Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic,” IEDM 2016, pp. 27.2.1-27.2.4. [3] J. M. Slaughter et al., “Technology for reliable spin-torque MRAM products,” IEDM 2016, pp. 21.5.1-21.5.4. [4] C. Adelmann et al., “Alternative metals for advanced interconnects,” Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2014 IEEE International 2014, pp. 173–176. [5] “Sentaurus Device.” [Online]. Available: https://www.synopsys.com/silicon/tcad/device-simulation/sentaurusdevice.html. [Accessed: 22-Jan-2019]. [6] A. F. Mayadas and M. Shatzkes, “Electrical-Resistivity Model for Polycrystalline Films: the Case of Arbitrary Reflection at External Surfaces,” Phys. Rev. B, vol. 1, no. 4, pp. 1382–1389, Feb. 1970. [7] V. Kamineni et al., “Contact Metallization for Advanced CMOS Technology Nodes,” in 2018 IEEE International Interconnect Technology Conference (IITC), 2018, pp. 28–29. [8] E. Milosevic et al., “Validity and Application of the TCR Method to MOL contactS,” in IEEE International Interconnect Technology Conference (IITC), 2018, pp. 36–38. [9] N. A. Lanzillo et al., “Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study,” J. Appl. Phys., vol. 123, no. 15, p. 154303, Apr. 2018. [10] H. Dixit, J. Cho, and F. Benistant, “First-principles evaluation of resistance contributions in Ruthenium interconnects for advanced technology nodes,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2018, pp. 220–223. [11] “QuantumATK Atomic-Scale Modeling for Semiconductor & Materials.” [Online]. Available: https://www.synopsys.com/silicon/quantumatk.html. [Accessed: 22-Jan2019].
Conflict of Interest and Authorship Conformation Form Please check the following as appropriate:
All authors have participated in (a) conception and design, or analysis and interpretation of the data; (b) drafting the article or revising it critically for important intellectual content; and (c) approval of the final version.
This manuscript has not been submitted to, nor is under review at, another journal or other publishing venue.
The authors have no affiliation with any organization with a direct or indirect financial interest in the subject matter discussed in the manuscript
The following authors have affiliations with organizations with direct or indirect financial interest in the subject matter discussed in the manuscript:
Author’s name Hemant Dixit Sudarshan Narayanan
Affiliation GlobalFoundires. USA. GlobalFoundires. USA.
Bert Pfefferling Johannes Mueller
GlobalFoundires. Germany. GlobalFoundires. Germany.
S0026-2692(19)30482-3
DOI:
https://doi.org/10.1016/j.mejo.2019.104663
Reference:
MEJ 104663
To appear in:
Microelectronics Journal
Received Date: 6 June 2019 Revised Date:
4 October 2019
Accepted Date: 13 November 2019
Please cite this article as: H. Dixit, S. Narayanan, B. Pfefferling, J. Mueller, Optimization of the interconnect resistance contribution for STT-MRAM technology, Microelectronics Journal (2019), doi: https://doi.org/10.1016/j.mejo.2019.104663. This is a PDF file of an article that has undergone enhancements after acceptance, such as the addition of a cover page and metadata, and formatting for readability, but it is not yet the definitive version of record. This version will undergo additional copyediting, typesetting and review before it is published in its final form, but we are providing this version to give early visibility of the article. Please note that, during the production process, errors may be discovered which could affect the content, and all legal disclaimers that apply to the journal pertain. © 2019 Published by Elsevier Ltd.
Optimization of the Interconnect Resistance Contribution for STT-MRAM Technology Hemant Dixit*, Sudarshan Narayanan
Bert Pfefferling, Johannes Mueller
GLOBALFOUNDRIES Inc. 400 Stone Break Rd Extension, Malta, NY, USA *[email protected]
GLOBALFOUNDRIES Inc. Wilschdorfer Landstrasse 101, 01109 Dresden, Germany
Abstract— STT-MRAM has emerged as versatile memory technology, capable of serving a broad range of memory applications. A key figure of merit for the STT-MRAM device is the tunneling magnetoresistance ratio (TMR), which distinguishes between the high resistance (“Off”) and low resistance (“On”) state. In an Integrated Circuit (IC), the MRAM device is fabricated in back-end-of-line process and is powered using a MRAM Vertical Interconnect Access (M-VIA) structure. The series resistance from M-VIA structure, however, adversely impacts the TMR reducing the sense margin. Thus, to improve the TMR/sense margin of MRAM device, reduction of series M-VIA resistance is. We present a combination of ab-initio & TCAD simulations to estimate the M-VIA resistance contributions. Advanced interconnect metals, which include Co, Ru and W, are studied with TiN as barrier metal. The role of barrier metal and geometry is systematically investigated. These simulations provide potential pathways to reduce the M-VIA resistance contributions, allowing for a high density MRAM array. Keywords—STT-MRAM, TMR, VIA, Interconnects
I. INTRODUCTION Currently, perpendicular Magnetic Tunnel Junction (pMTJ) based Spin-Transfer Torque (STT) Magnetoresistive Random Access Memories (MRAM), which enables low power and high-speed operation, are being developed and are entering the commercialization phase for both stand-alone and embedded applications [1]–[3]. In its basic configuration MRAM bit-cell consists of 1 transistor and 1 MTJ, and is integrated as a back-end-of-the-line device in between metal layers, as illustrated in Figure 1. The MTJ consists of two ferromagnetic layers separated by an oxide which is typically MgO. Among these two ferromagnetic layers, one has fixed orientation of the magnetic moment – known as reference layer and the other layer can freely switch its magnetic orientation between parallel and anti-parallel configuration with respect to the reference layer orientation. Now, when an electric current flows through the MTJ, it sees either low or high resistance depending on the parallel or antiparallel orientation of the free layer. This magnetoresistance effect is harvested in MRAM technology and the information is stored as a high (RAP) or low (RP) resistance state based on the relative magnetization orientations of the free layer and reference layer. Tunnel Magnetoresistance Ratio (TMR) is a measure that is used to distinguish the RAP and RP states from each other and is defined as follows:
Fig. 1 a) BEOL integration of MTJ element and M-VIA structure underneath b) the M-VIA contributes a series resistance to the MTJ.
The TMR is thus a key figure of merit for MTJ devices and critical to determine its performance. The stored information in MRAM bit-cell can be read using either voltage or current sensing scheme. In case of current sensing scheme, current flows through MTJ and the MRAM bit-cell current is compared to a reference current, IREF, using a current sense amplifier (CSA). The MRAM bit-cell is in low resistance state (RP) if ICELL > IREF, and the CSA outputs a “0”. Otherwise, the MRAM bit-cell stores high resistance state (RAP) and the CSA outputs a “1”. If the value of high and low resistance states are close to each other (low TMR case), it can interfere with the sense margin of CSA. This naturally leads to a read failure and incorrect decisions. Thus, large TMR is often necessary to increase the sense margin and typical values of TMR lies between 150-175% for reliable memory operation. Although, TMR is primarily an MTJ property which originates from ferromagnet-oxide interface, there are also other additional external factors that need to be considered at a circuit level. In an integrated circuit, when MTJ element is incorporated as BEOL device, the series resistance from the metal interconnect, known as M-VIA plugs, reduces the effective TMR values. Figure 2, illustrates a decreasing TMR as a function of increasing M-VIA series resistance offered by the metal interconnects. It is observed that, a series resistance of 100 Ω can reduce the TMR by up to ~5%, with RP of 2.5 kΩ and TMR of 175%. This is especially important for advanced technology nodes where the interconnect dimensions are
immersed into the inter-layer dielectric (ILD) material in an IC. In this work, our goal is to establish the resistance dependence on the M-VIA CD. For this purpose, we run couple of process splits. The first one deals with BCD variation between 40-65 nm (in steps of 5 nm) and the second one deals with M-VIA
Fig. 2. TMR reduction as a function of increasing MVIA resistance.
shrinking but their resistance is growing due to quantum size effects. On the other hand, for higher density of MTJ elements – a smaller M-VIA is desired. In this article, we present TCAD simulations for evaluating the series resistance offered by a typical M-VIA structure in BEOL. We work with advanced interconnect metals that include Co, Ru and W [4]. First, we investigate the impact of M-VIA critical dimensions (CD) on its resistance and later discuss the role of TiN barrier metal. The simulation results provides useful physical insights for the design of experiment
Fig. 3. M-VIA structure (left) and its vertical cross section (right) used in TCAD simulations
to optimize the M-VIA series resistance. Further, these effort help to improve the scaling, or density of the MTJ elements in the MRAM array. II. M-VIA STRUCTURE AND RESISTANCE CONTRIBUTIONS The M-VIA structures were generated using Sentaurus tool SProcess and the device simulations were completed using Sdevice [5]. The M-VIA structure considered in this study is illustrated in Figure 3. It consists of cylindrical metal plug with a top and bottom CD (TCD and BCD) connected together with a constant taper angle of about 84°. The metal plug is surrounded by a layer of barrier metal used to prevent the electromigration. The electromigration concern also dictates how thin the barrier metal can be and typically these thickness ranges between 5-10 nm thick. The M-VIA structure is then
Fig. 4. Thickness dependent resistivity of Co, Ru and W metals.
height variations between 20 – 140 nm (in steps of 20 nm) representative of the separation between different metal levels. Finally, the barrier thickness is also varied between 5-10 nm in steps of 2.5 nm each. We choose to work with advanced metallization that include Co, Ru and W metals, with TiN as the barrier metal. In order to accurately evaluate the total resistance offered by the M-VIA structure, two important factors need to be considered – the contribution of thickness dependent resistance of each metal layer and the contribution from metal-metal interface resistivity. Firstly, it is well-established that the interconnect resistivity increases exponentially with decreasing interconnect dimensions due to quantum size effects and scattering mechanisms. Furthermore, the processing conditions also affect the blanket resistivity of individual metal owing to the traces of impurities left during deposition. Here, we have used well known Mayadas-Shatzkes expression [6] to evaluate the resistivity scaling as a function of decreasing metal thickness. We observe that an average grain-boundary reflection coefficient of 0.58, 0.50 and 0.51 provide best fit for the hardware data, for Co, W and Ru, respectively [7]–[10]. It should be noted that the bulk resistivity values are, however, measured from blanket films pertaining to the process conditions and adopted in the scaling. The resistivity variations of all these metals are shown in Figure 4. An average resistivity values of ~ 25, 15 & 48.4 µΩ-cm for Co, Ru and W, respectively, corresponding to the 45 nm thickness, are chosen to be input for the TCAD . Secondly, the metal-metal interfaces also contribute to the total resistance of M-VIA. In order to evaluate the interface resistance for metal/barrier
Fig. 5. Illustration of atomistic device used to calculate the interface resistivity between two metals using ab-initio DFT+NEGF framework.
interfaces, we used ab initio Density Functional Theory (DFT) and non-equilibrium Green’s Function (NEGF) approach [10], [11]. In this method a device configuration is constructed using atomistic geometry of the metals (see Figure 5), and later electron transport across the interface, from the left electrode to Metal TiN
Co 43.18×e-12 ( Ω-cm2)
Ru 25.11×e-12 ( Ω-cm2)
W 61.02×e-12 ( Ω-cm2)
Table 1. Calculated interface resistivity for metal/liner interface.
the right electrode, is evaluated as depicted in Figure 5. Since, in reality the interface structure can be polycrystalline or amorphous, we apply random fractional displacement to the Fig. 7. Total resistance as a function of the MVIA height at 40 nm BCD with 5 nm TiN barrier.
evaluate the CD dependence of resistivity at fixed barrier thickness. The calculated resistance values for Co, Ru & W plugs are listed in Table 2.
Fig. 6. Quasi Fermi Potential drop across the M-VIA structure.
interface atoms and thereby evaluate the averaged effect of interface resistance. The calculated values of Co, Ru, W/TiN interface resistance are listed in Table 1. III. IMPACT OF CRITICAL DIMENSIONS AND LINER METAL Sdevice TCAD simulations were performed to determine the quasi-Fermi potential across the M-VIA structure, after including thickness dependent bulk resistivity of metals and metal-metal interface resistivity as discussed in the previous section. Figure 6 shows a representative quasi-Fermi potential profile across M-VIA structure calculated using TCAD simulation. We observe a potential drop of ~ 68 % and ~ 32 % within the metal and liner region of the M-VIA plug, respectively. The resistance distribution indicate that both metal plug and liner significantly contribute to the total resistance. These knobs can be turned independently – for example, by reducing the liner thickness or by changing the MVIA metal fill – for resistance optimization. Thus we investigate both the above mentioned possibilities. First, we BCD (nm) 40 45 50 55 60 65
Co
Ru
W
53.34 Ω 42.00 Ω 33.92Ω 27.97 Ω 23.46 Ω 23.36 Ω
43.85 Ω 34.50 Ω 27.84 Ω 22.94 Ω 19.45 Ω 19.22 Ω
75.51 Ω 59.59 Ω 48.22 Ω 39.84 Ω 33.46 Ω 32.49 Ω
Table 2. Resistance impact of BCD variations on total M-VIA resistance, corresponding to the TiN liner thickness is 5 nm.
We observe that about 50% decrease in M-VIA resistance, by increasing BCD from 40 nm to 65 nm, is possible. The resistance evolution is, however, non-linear and the initial average slope of ~3 Ω/nm for W, flattens out beyond 60 nm of BCD - indicating that there will not be any significant scaling disadvantage. Similarly, we also evaluate the M-VIA resistance as a function of increasing M-VIA height between 20-140 nm and the results are shown in Figure 7. The graph indicates that the resistance difference between different metal is more pronounced at increased M-VIA heights (> 100 nm). Finally, we also calculate the impact of barrier thickness on the M-VIA resistance. For this purpose, barrier thickness of 5, 7.5 and 10 nm were studied. The calculated M-VIA resistance are shown
Fig. 8. Total resistance as a function of the TiN liner thickness.
in Figure 8. We observe almost linear dependence of M-VIA resistance on the barrier thickness and the resistance increases @ 2 Ω/nm for W and this slope is further decreased for Co and Ru, respectively.
IV. CONCLUSIONS We evaluated the series resistance contribution arising from M-VIA structures using a combination of ab-initio and TCAD simulations. Advanced BEOL metals interconnects and
corresponding combinations of liner metals were systematically studied. The results indicate that both BCD and barrier thickness provide an independent control to optimize the M-VIA resistance. Our simulations results shows that 60 nm is the optimal choice for the M-VIA BCD and it further does not offer any significant advantage in terms of resistance reduction. Similarly, for the barrier metal thickness - 5 nm thick barrier metal is most appropriate to reduce the total MVIA resistance. Further reduction in the barrier thickness may lead to electromigration issues. We also considered the M-VIA height variation and the results indicate that the M-VIA resistance monotonically decreases with decreasing height. The average slope is about 0.5 Ω/nm for W and is the slope is further reduced for Co and Ru, respectively. These finding may lead to potential pathways to reduce the series resistance of MVIA and thereby improve the STT-MRAM density in advanced technology nodes for embedded memory applications. ACKNOWLEDGMENT We thank Konstantin Korablev, Reshma Krishnan for useful discussion related to this work. REFERENCES [1]
K. Lee and S. H. Kang, “Development of Embedded STT-MRAM for Mobile System-on-Chips,” IEEE Trans. Magn., vol. 47, no. 1, pp. 131– 136, Jan. 2011.
[2]
Y. J. Song et al., “Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic,” IEDM 2016, pp. 27.2.1-27.2.4. [3] J. M. Slaughter et al., “Technology for reliable spin-torque MRAM products,” IEDM 2016, pp. 21.5.1-21.5.4. [4] C. Adelmann et al., “Alternative metals for advanced interconnects,” Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 2014 IEEE International 2014, pp. 173–176. [5] “Sentaurus Device.” [Online]. Available: https://www.synopsys.com/silicon/tcad/device-simulation/sentaurusdevice.html. [Accessed: 22-Jan-2019]. [6] A. F. Mayadas and M. Shatzkes, “Electrical-Resistivity Model for Polycrystalline Films: the Case of Arbitrary Reflection at External Surfaces,” Phys. Rev. B, vol. 1, no. 4, pp. 1382–1389, Feb. 1970. [7] V. Kamineni et al., “Contact Metallization for Advanced CMOS Technology Nodes,” in 2018 IEEE International Interconnect Technology Conference (IITC), 2018, pp. 28–29. [8] E. Milosevic et al., “Validity and Application of the TCR Method to MOL contactS,” in IEEE International Interconnect Technology Conference (IITC), 2018, pp. 36–38. [9] N. A. Lanzillo et al., “Defect and grain boundary scattering in tungsten: A combined theoretical and experimental study,” J. Appl. Phys., vol. 123, no. 15, p. 154303, Apr. 2018. [10] H. Dixit, J. Cho, and F. Benistant, “First-principles evaluation of resistance contributions in Ruthenium interconnects for advanced technology nodes,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) 2018, pp. 220–223. [11] “QuantumATK Atomic-Scale Modeling for Semiconductor & Materials.” [Online]. Available: https://www.synopsys.com/silicon/quantumatk.html. [Accessed: 22-Jan2019].
Conflict of Interest and Authorship Conformation Form Please check the following as appropriate:
All authors have participated in (a) conception and design, or analysis and interpretation of the data; (b) drafting the article or revising it critically for important intellectual content; and (c) approval of the final version.
This manuscript has not been submitted to, nor is under review at, another journal or other publishing venue.
The authors have no affiliation with any organization with a direct or indirect financial interest in the subject matter discussed in the manuscript
The following authors have affiliations with organizations with direct or indirect financial interest in the subject matter discussed in the manuscript:
Author’s name Hemant Dixit Sudarshan Narayanan
Affiliation GlobalFoundires. USA. GlobalFoundires. USA.
Bert Pfefferling Johannes Mueller
GlobalFoundires. Germany. GlobalFoundires. Germany.