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Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material
Microelectronics Reliability 51 (2011) 953–958
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material Bhavana N. Joshi, Yogesh S. Mhaisagar, Ashok M. Mahajan ⇑ Department of Electronics, North Maharashtra University, Jalgaon 425 001, India
a r t i c l e
i n f o
Article history: Received 30 July 2010 Received in revised form 24 November 2010 Accepted 17 January 2011 Available online 12 February 2011
a b s t r a c t A vital parameter interconnect capacitance in the ULSI has been investigated in this paper. The potential and static capacitance under the metal line strip has been determined by solving the Poisson’s equation by finite difference method. It has been observed that, the lowering of interconnect width and spacing between the two metal lines affect significantly on coupling capacitance. The total capacitance (CT) is dominantly being contributed by coupling capacitance (Cc). The calculations of CT have been made by using the low dielectric constant (k = 2.97) of the deposited hybrid thin film. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Miniaturization of interconnects results in increasingly high current densities leading to the open-and/or short-circuit electrical failures. Noticeably, interconnects play a crucial role in the development of the nanoscale integrated circuits and that, in addition to the development of the various nano devices. In sub nanometer (<100 nm) technology circuit designs [1–3], gate delay is reduced and clock frequency is achieved in gigahertz by packing the millions of transistors on a single chip [4]. The advantage of densely packed transistors in single integrated circuits (IC) is the shrinkage of device area and huge enhancement in performance speed of nano devices. However, the continuous lowering of transistor size is not sustainable to achieve further speed escalation, since the vital issues like Resistance–Capacitance (RC) propagation delay, crosstalk noise and power consumption have to be taken into account in the optimization and designing of the devices. Multilevel of interconnects increases to realize multifunctionality [5] within the downsized geometry in Ultra Large Scale Integrated (ULSI) circuits with high density of transistors on a single chip. Though, this downsizing of interconnect geometry and multifunctionality reduces device area and enhances the operation speed, however, it results in higher geometrical complexity of the device. Hence, the determination of interconnect capacitance becomes a great challenge to the design engineers to obtain an optimum interconnect capacitance to reduce the RC delay time of the IC. The RC delay arises due to interconnect which forms many wire couplings and crossovers [6]. These, couplings and crossovers induce high capacitance, and thereby becomes the major factor in affecting ⇑ Corresponding author. Tel.: +91 257 2257476; fax: +91 257 2258403. E-mail addresses: [email protected], [email protected] (A.M. Mahajan). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.01.009
the circuit speed. Therefore, it is essential to minimize RC delay by using low resistivity interconnect metal line and low permittivity dielectric insulator [7,8]. Consequently, one can have the alternative low resistivity (q) metal Copper (Cu, q 1.67 X cm) to replace the high resistivity metal Aluminum (Al, q 2.66 X cm). The Cu significantly used as interconnect metal line due to its higher thermal conductivity and capability of bearing higher thermal stress as compared to Al. Along with the lowering of resistance one needs to lower the capacitance as well, by utilizing the low permittivity dielectric material having the dielectric constant (k) less than that of SiO2 [9–11]. Even though low-k and low resistivity materials are available as an alternative in back end, the proper understanding of interconnect geometry is important to optimize the different parameters of interconnect for accurate interconnect capacitance and signal integrity estimation. The ULSI circuits show an increase in the density of transistor per chip and the number of metallization layers. The metal interconnect nanowires have thin width which increases the resistance of interconnects, to compensate this resistance its thickness needs to be increased. Thus, the slight variation in dimensions of the interconnect affects significantly to the electrical properties [12]. As the complexity increases radically with 32 nm technology [13,14] it is increasingly important to compute all its parasitic components, mainly wiring capacitances accurately. Their evaluation is challenging and various efforts are devoted to this work. There are two major approaches to calculate the parasitic capacitance. The first type is to use a numerical simulation [15], often based on Finite Difference Time Domain or on Finite Element Method. The numerical methods have good accuracy and powerful in complex geometries, however they are too time-consuming, in case of complete IC. The second approach uses analytic formulations, derived from the equations of electromagnetism. These methods have a sufficient accuracy and a simulation speed.
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B.N. Joshi et al. / Microelectronics Reliability 51 (2011) 953–958
Sakurai’s empirical model [16] has been widely used on the basis of its simplicity and accuracy. Choudhury’s model [17] gives formulae for several representative layouts, but it is only suitable for limited set of process parameters. The Chern et al. [18] also described model by considering multilevel lines crossing with each other on adjacent layers and are observed to be accurate. The work carried out on various models mentioned above is purely based on theoretical aspect. However, in this work, we included the experimental values of hybrid dielectric constant and implementation of finite difference method for solving the Poisson equation to get the charge density. Then, using the charge density and Green’s function the potential on conductor and the static capacitance have been determined. Further, the work is extended for the estimation of the various capacitances for 32 nm technology node using the model reported by Kurokawa et al. and references therein [19] for one and two ground planes; combinations of these two fundamental structures are useful to pretend layout of interconnect structures of high speed IC [20]. For all the simulation work the low dielectric constant (k = 2.97) value used is of the hybrid thin film deposited by us [21].
Gh ¼
1 X eam Dx pjam j m¼1 eox cothðtox am Þ þ es cothðts am Þ ½es cothðt s am Þ½1 þ eox cothðt ox am Þ þ eox ½eox þ eox cothðt ox am Þ
ð2Þ 2mpþh , p
where am is given by the following expression, am ¼ m is the integer, P is the pitch as shown in Fig. 1. The thickness of the oxide layer is tox, while ts is the thickness of the substrate. eox and es are the dielectric constant of oxide layer and substrate respectively.
V¼
Z
W=2
W=2
Gh qh dx
ð3Þ
2. Mathematical approach 2.1. Green function and Poisson equation Fig. 2. (a) Typical structure of interconnect geometry on one ground plane.
The Metal Insulator Semiconductor (MIS) structures, shown in Fig. 1 have been used to realize the potential and static capacitance under the metal line strip. The Poisson equation (1a) [22] has been solved by using finite difference method to obtain the values of electron and hole concentrations. Further, the charge density equation is estimated using the values of electron and hole concentration in accordance to Eq. (1b) [23] for the given interconnect structure.
d dx
eðxÞ
d q /ðxÞ ¼ pðxÞ nðxÞ þ Nþd ðxÞ Na ðxÞ dx eo
qh ¼ q p þ Nþd n Na
ð1aÞ ð1bÞ
where /, q, e and eo are the electrostatic potential, electric charge dielectric constant and permittivity of vacuum respectively. The n and p are the free electron and hole densities and Nþ d and N a are position dependent ionized acceptor and donor concentrations. Further, to realize the potential, the Green function [24–26] Eq. (2) has been solved. The green’s function equation used here is according to the work carried out by Yamashita et al. and they have already performed the Fourier transform of two dimensional Lapalce equation and they have given the resultant expression as shown in Eq. (2) [27]. The charge density and Green Function’s output are integrated as given in Eq. (3).
Fig. 1. Schematic of Metal Insulator Semiconductor (MIS) structure.
Fig. 2. (b) Interconnect structure between two ground planes.
Fig. 2. (c) Capacitance voltage curve of deposited hybrid low-k thin film (k 2.97) [28]. Inset figure is SEM image.
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B.N. Joshi et al. / Microelectronics Reliability 51 (2011) 953–958
Here, W is the width of the metal line, Gh is Green function and qh is the charge density function. The values of potential, derived from Eq. (3) have been used to determine the static capacitance by using Eq. (4).
Cs ¼
1 V
Z
W=2
W=2
qh dx
ð4Þ
A detailed structure of interconnect geometry with one ground plane and two ground plane is presented in Fig. 2a and b respectively, that clearly elaborates the lateral, crossover and overlap capacitance between different metal lines. The lateral capacitance is the capacitance between parallel edges of two metal lines in same plane also known as coupling capacitance. The capacitance between the edge of one metal and surface area of other metal above or below the first metal is called as crossover or fringe capacitance, whereas the parallel plate capacitance or the capacitance between surfaces of two metals is known as overlap capacitance. Fig. 2b shows interconnect schematic geometry of two metal lines with insulating material along with different capacitances. The thin layer used in between the metal lines is Interlayer Dielectric (ILD). These, ILD need to have low dielectric constant to reduce the RC delay of the ULSI circuit for achieving high speed. Hence, we have worked to produce the hybrid low dielectric thin films deposited via spin coating technique in which methylmethacrylate (MMA organic material) is doped in SiO2. The thin films deposited by us yields the low dielectric constant with k 2.97. Further the dielectric constant is also determined by forming the Metal Insulator Semiconductor (MIS) structure explained elsewhere [28]. The paper presents the detail analysis of overlap, lateral and crossover capacitances for one ground and two ground plane structures. These, capacitances show dependence on wire width, wire spacing and wire thickness. The equations involved in the analysis of these capacitances are given below [19].
2.3. Line to line capacitance (coupling/lateral capacitance) It is obligatory to investigate coupling capacitance, as for the high aspect ratio and the increased line thickness increases delay in the device and creates high signal coupling noises. These limitations will hamper to the practical implementation of scaling techniques. Thus, inclusion of low dielectric material in place of SiO2 effectively reduces interconnect parasitic capacitances by lowering the RC delay and crosstalk effect. One ground plane:
0 B C L ¼ e@
1:064
T S
Tþ2H Tþ2Hþ0:5S
0:695
þ
W Wþ0:8S
1:414
0:055 W 2H þ0:831 Wþ0:8S 2Hþ0:5S
0:804 1 Tþ2H Tþ2Hþ0:5S C A 3:542 ð6aÞ
Two Ground Plane:
0 1 H H T T T 1 1:879e0:31S 2:474S þ 1:302e0:082S 0:1292e1:326S S B C S C L ¼ e@ A W þ1:722 1 0:654e0:3477H e0:651H ð6bÞ
2.2. Line to ground capacitance (Overlap capacitance) The interlayer dielectric has been a bottleneck for the efficient performance of the devices. As already discussed, present low dielectric material cannot meet all the required characteristics of recent ITRS in all respects. The parasitic capacitance is very vital and has a high impact on device and circuit performance. The parasitic capacitance makes significant distortion in device and degrades its performance, while the spacer dielectric material drastically influence to the fringing capacitance. Hence, to have a divergence to the rising RC delay, it is very much essential to have advances in geometrical structures and material perspective. In this paper, we had used the following physical models which have higher accuracy with new geometrical aspects in terms of the dimension wise and the new material perspective of using the fabricated MIS structure’s dielectric constant determined through CV curves obtained from the Keithley CV 590 system. The miniaturization of the devices has led to reduction in the interconnect dimensions to be lowered and due to this the delay becomes much larger. It is very necessary to note that the high aspect ratio is imperative in metal to ground capacitance which is directly proportional to line width and material dielectric constant has observed from the following equation (5). One ground plane:
CO ¼ e
0:023 1:16 ! W T S þ 3:28 H T þ 2H S þ 2H
Fig. 3. Variation of potential with increase in metal line width obtained through Poisson equation.
ð5aÞ
Two ground plane:
W T S þ 1:086 1 þ 0:685e1:343S 0:9964e1:421H CO ¼ e H
ð5bÞ Fig. 4. Variation of potential with increase in spacing between metal lines.
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2.4. Crossover / fringe capacitance
0 B B B B B B C C ¼ eB B B B B @
3. Results and discussion
0:2 1 T 1 S1 S1 þ 0:9413 1 0:326e0:133S1 0:959e1:966H 2W 2 S1 þ0:01H C 0:2 C T 2 S2 C S2 0:133S2 C þ0:9413 1 0:326e 0:950e1:966H 2W 1 S2 þ0:01H C C C T 1 W 0:182 S1 C 0:5 2 þ1:14 1 0:326e0:133S1 0:959e1:966H ðS2 S1 Þ C H C C T 2 A S2 0:182 0:5 þ1:14 1 0:326e0:133S2 0:9591:966H ðS1 S2 Þ WH1
W1 W2 H
ð7Þ where the CO is the overlap capacitance, CL is line to line capacitance, CC is crossover capacitance, e is dielectric constant, W is width of interconnect, T is thickness of interconnect, S is spacing between two interconnects in plane, H is thickness of dielectric. The total capacitance CT is determined by adding the CO, CL, CC for respective planes.
In present work, we have focused ourselves to realize the impact of various dimensional parameters incorporation with the measured dielectric constant of the hybrid low-k (2.97) thin film deposited by us. As mentioned above, the capacitance voltage curve of deposited hybrid low-k thin film determined from CV 590 is shown in Fig. 2c [28] with variation in biasing voltage from 1 V to 5 V. The inset of Fig. 2c shows the SEM image of deposited thin film that reveals the surface of film is uniform and crack free. From Fig. 3 it has been observed that, with the decrease in the width of the metal line the potential of MIS structure under metal strip decreases. The potential have been deduced by solving the Green’s function for mode ‘0’. The charge density has been calculated through Poisson equation by using the finite difference method. The reference voltage (Vref) for calculation of the charge density has been taken to be 1 V. Utilizing the same charge density values obtained from Poisson equation the study has been extended to realize the effect of spacing between the two metal lines on potential. It has been depicted in Fig. 4 that, with the decrease in the spacing the potential founds to be increasing. The potential rises from 2.45 V to 3.8 V with the decrease in spacing from 0.31 to 0.08 lm. Interconnect and the device performance are very much interlinked and hence, it is essential to investigate the capacitances involved in device performance. Some of the existing simulation
Fig. 5. Static capacitance dependence on metal line width for the hybrid based MIS structure. Fig. 7. Overlap capacitance for one ground plane with variation in wire width and spacing.
Fig. 6. Dependence of static capacitance on spacing between two metal lines for interconnect layer of dielectric constant 2.97.
Fig. 8. Overlap capacitance for two ground plane with variation in wire width and spacing.
B.N. Joshi et al. / Microelectronics Reliability 51 (2011) 953–958
software tries to investigate different geometry of the multilevel interconnect structures. However, here we have used the numerical approach for studying the variation of static capacitance in MIS structure. From Fig. 5 the variation of static capacitance has been observed to be non-linearly increasing with the decrease in width of the metal line. The increase in the static capacitance with the decrease in width may be due to the increase in the charge density and decrement in the surface area. The investigation of the static capacitance dependence on spacing between the two metal lines has been carried out as shown in Fig. 6. The static capacitance has been found to be decreasing nonlinearly. The change in static capacitance values was deduced to be 0.057 pF for the 0.08 lm spacing between metal lines. The decrement in the static capacitance with the spacing may be attributed because of the fringing capacitance and lateral capacitance. Fig. 7 represents the overlap capacitance for one ground plane due to the effect of wire width and spacing between the two metal wires. The figure clearly reveals the variation of the capacitance as observed through the different colour shades present in the three dimensional plots and the respective values of the capacitance in accordance to colour shade can be easily judged by viewing the colour bar next of the figure. It reveals from Fig. 7 that, the overlap capacitance decreases to 0.27 pF with decrease in wire width and spacing to 0.08 lm. This capacitance is actually a parallel plate
Fig. 9. Crossover capacitance with variation in wire width and spacing of hybrid interlayer dielectric.
957
Fig. 11. Coupling capacitance for two ground plane with variation in wire width and spacing.
capacitance. Hence, the overlap capacitance decreases with lowering in interconnect area. The effect of wire width and spacing between metal lines for two ground plane is shown in Fig. 8. It is observed from Fig. 8 that the reduction in wire width has negligible effect on overlap capacitance. However, the capacitance falls linearly with decrease in spacing between the metal lines from 0.35 lm to 0.08 lm. The crossover capacitance decreases from 7.52 pF to 0.01 pF drastically with decrease in spacing from 0.35 lm to 0.08 lm for fixed dielectric thickness of 0.15 lm, this is because the adjacent lines shield the substrate from the field at the edges of metal. The capacitance also lowers with the decrease in wire width giving rise to leaf shape to graph as shown in Fig. 9. The coupling capacitance is observed to be increasing nonlinearly from 1.04 pF to 1.58 pF with decrease in spacing from 0.35 lm to 0.08 lm where as no significant effect of lowering in wire width is observed on coupling capacitance as shown in Fig. 10. The effect of lowering of wire width and spacing on coupling capacitance for two ground planes is depicted in Fig. 11. Fig. 11 clearly shows as spacing decreases the coupling capacitance increases fastly, minimizing the effect of lowering in wire width. The reduced width of interconnect and interwire spacing mainly increases the coupling capacitance contributing 84% in total capacitance of interconnects in case of one ground plane. The contribution of crossover capacitance and overlap capacitance is 0.58 and 14.83% respectively. For two ground planes the contribution of coupling capacitance decreases to 68% and overlap capacitance increases to 30.87%. The CT of 2.44 pF and 1.74 pF (SiO2 k 3.9) reduced to 1.87 pF and 1.33 pF (low-k, k = 2.97) for one and two ground planes respectively. 4. Conclusions
Fig. 10. Coupling capacitance for one ground plane with variation in wire width and spacing.
The effect of metal width and spacing between two metal lines on potential and static capacitance of MIS structure has been studied by using the Green’s function. It has been observed that, potential on conductor increases for lower spacing between the metal lines whereas, the lowering of metal width enhances the static capacitance due to raised charge density. The interconnect capacitance get affected significantly by the lowering in interconnect width and interwire spacing as a requirement of 32 nm technology. The coupling capacitance contributes to total capacitance by 84% and 68% for one and two ground planes. It has been observed that, the total capacitance reduced by 76% by replacing the SiO2 dielectric with the low dielectric material deposited by us. Hence, it can be concluded that, the material deposited by us is suitable as ILD to reduce the capacitance of circuit and in turn, RC delay.
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References [1] International technology roadmap of semiconductors –ITRS 2007. [2] Bansal Aditya, Paul Bipul C, Roy Kaushik. IEEE T Compu Aid D 2006;25(12): 2765. [3] Liu B, Yang JJ, Liu CH, Wang Y. Appl Phys Lett 2009;94:153116. [4] Banerjee Kaustav, Im Sungjun and Srivastava, Navin. In: proceedings of the 22nd advanced metallization conference, Colorado Springs, CO, 2005. [5] Heitzinger Clemens, Sheikholeslami Alireza, Badrieh Fuad, Puchner Helmut, Selberherr Siegfried. IEEE T Electron Dev 2004;51(7):1129. [6] Wong Shyh-Chyi, Lee Gwo-Yann, Ma Dye-Jyun, Chao Chuan-Jane. IEEE T Semiconduct M 2000;13(2):219. [7] Sonanvane A, Joshi BN, Mahajan AM. Prog Electromagnetics Res Lett 2008;1: 189. [8] Viitanen AJ, Nefedov IS, Tretyakov SA. PIERS Online 2007;3:1080. [9] Theis TN. IBM J Res Devel 2000;44(3):379. [10] Joshi Bhavana N, Mahajan AM. J Optoelectron Adv M 2008;10(2):422. [11] Tripathi R, Gangwar R, Singh N. Prog Electromagnetics Res Lett 2007;77:367. [12] Kumar R, Kang K, Rustagi SC, Mouthaan K, Wong TKS. Electron Lett 2007;43(24). [13] Deleonibus S, de Salvo B, Ernst T, Faynot O, Poiroux T, Vinet M. CEA-Grenoble, Grenoble, In: proceedings of international workshop on physics of semiconductor devices (IWPSD), 2007, p. 16.
[14] Claeys C, Put S, Rafi JM, Pavanello MA, Martino JA and Simoen E. In: proceddings of 2nd international workshop on electron devices and semiconductor technology (IEDST), 2009, p. 1. [15] Taylor CD, Elkhouri GN, Wade TE. IEEE T Electron Dev 1985;32:1414. [16] Sakurai T, Tamaru K. T Electron Dev 1983;30:183. [17] Choudhury U and Sangiovanni-Vincentelli A. IEEE custom integrated circuits conference, 1991. [18] Chern J-H, Huang J, Arledge L, Li P-C, Yang P. IEEE Electron Dev Lett 1992;13:32. [19] Kurokawa Atsushi, Masuda Hiroo, Fujii Junko, Inoshita Toshinori, Kasebe Akira, Huang Zhangcai, et al. IEICE T Fund 2006;E89–A(4):856. [20] Wong Shyh-Chyi, Lee Gwo-Yann, Ma Dye-Jyun. IEEE T Semiconduct M 2000;13(1):108. [21] Joshi Bhavana N, Mahajan AM. Bull Mater Sci 2010;33(3):197. [22] Raynaud C. J Appl Phys 2000;88(1):424. [23] Kuo Jen Tsai. IEEE T Microw Theory 1995;43(8):1881. [24] Niknejad Ali M, Gharpurey Ranjit, Meyer Robert G. IEEE T Compu Aid D 1998;17(4):305. [25] Ymeri H, Nauwelaer B, Maex K. Period Polytech Ser El Eng 2001;45(1):13. [26] Jain Jitesh, Koh Cheng-Kok, Balakrishnan Venkataramanan. IEEE T Circuits and Syst 2006;53(6):458. [27] Goel Ashok. High speed VLSI interconnections, 2nd ed. Wiley interscience, John Wiley and Sons’s Publications. (247). [28] Joshi Bhavana N, Mahajan AM. Mater Sci Semiconduct Process 2010;13(1):41.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Analysis of interconnect capacitance for sub nano CMOS technology using the low dielectric material Bhavana N. Joshi, Yogesh S. Mhaisagar, Ashok M. Mahajan ⇑ Department of Electronics, North Maharashtra University, Jalgaon 425 001, India
a r t i c l e
i n f o
Article history: Received 30 July 2010 Received in revised form 24 November 2010 Accepted 17 January 2011 Available online 12 February 2011
a b s t r a c t A vital parameter interconnect capacitance in the ULSI has been investigated in this paper. The potential and static capacitance under the metal line strip has been determined by solving the Poisson’s equation by finite difference method. It has been observed that, the lowering of interconnect width and spacing between the two metal lines affect significantly on coupling capacitance. The total capacitance (CT) is dominantly being contributed by coupling capacitance (Cc). The calculations of CT have been made by using the low dielectric constant (k = 2.97) of the deposited hybrid thin film. Ó 2011 Elsevier Ltd. All rights reserved.
1. Introduction Miniaturization of interconnects results in increasingly high current densities leading to the open-and/or short-circuit electrical failures. Noticeably, interconnects play a crucial role in the development of the nanoscale integrated circuits and that, in addition to the development of the various nano devices. In sub nanometer (<100 nm) technology circuit designs [1–3], gate delay is reduced and clock frequency is achieved in gigahertz by packing the millions of transistors on a single chip [4]. The advantage of densely packed transistors in single integrated circuits (IC) is the shrinkage of device area and huge enhancement in performance speed of nano devices. However, the continuous lowering of transistor size is not sustainable to achieve further speed escalation, since the vital issues like Resistance–Capacitance (RC) propagation delay, crosstalk noise and power consumption have to be taken into account in the optimization and designing of the devices. Multilevel of interconnects increases to realize multifunctionality [5] within the downsized geometry in Ultra Large Scale Integrated (ULSI) circuits with high density of transistors on a single chip. Though, this downsizing of interconnect geometry and multifunctionality reduces device area and enhances the operation speed, however, it results in higher geometrical complexity of the device. Hence, the determination of interconnect capacitance becomes a great challenge to the design engineers to obtain an optimum interconnect capacitance to reduce the RC delay time of the IC. The RC delay arises due to interconnect which forms many wire couplings and crossovers [6]. These, couplings and crossovers induce high capacitance, and thereby becomes the major factor in affecting ⇑ Corresponding author. Tel.: +91 257 2257476; fax: +91 257 2258403. E-mail addresses: [email protected], [email protected] (A.M. Mahajan). 0026-2714/$ - see front matter Ó 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2011.01.009
the circuit speed. Therefore, it is essential to minimize RC delay by using low resistivity interconnect metal line and low permittivity dielectric insulator [7,8]. Consequently, one can have the alternative low resistivity (q) metal Copper (Cu, q 1.67 X cm) to replace the high resistivity metal Aluminum (Al, q 2.66 X cm). The Cu significantly used as interconnect metal line due to its higher thermal conductivity and capability of bearing higher thermal stress as compared to Al. Along with the lowering of resistance one needs to lower the capacitance as well, by utilizing the low permittivity dielectric material having the dielectric constant (k) less than that of SiO2 [9–11]. Even though low-k and low resistivity materials are available as an alternative in back end, the proper understanding of interconnect geometry is important to optimize the different parameters of interconnect for accurate interconnect capacitance and signal integrity estimation. The ULSI circuits show an increase in the density of transistor per chip and the number of metallization layers. The metal interconnect nanowires have thin width which increases the resistance of interconnects, to compensate this resistance its thickness needs to be increased. Thus, the slight variation in dimensions of the interconnect affects significantly to the electrical properties [12]. As the complexity increases radically with 32 nm technology [13,14] it is increasingly important to compute all its parasitic components, mainly wiring capacitances accurately. Their evaluation is challenging and various efforts are devoted to this work. There are two major approaches to calculate the parasitic capacitance. The first type is to use a numerical simulation [15], often based on Finite Difference Time Domain or on Finite Element Method. The numerical methods have good accuracy and powerful in complex geometries, however they are too time-consuming, in case of complete IC. The second approach uses analytic formulations, derived from the equations of electromagnetism. These methods have a sufficient accuracy and a simulation speed.
954
B.N. Joshi et al. / Microelectronics Reliability 51 (2011) 953–958
Sakurai’s empirical model [16] has been widely used on the basis of its simplicity and accuracy. Choudhury’s model [17] gives formulae for several representative layouts, but it is only suitable for limited set of process parameters. The Chern et al. [18] also described model by considering multilevel lines crossing with each other on adjacent layers and are observed to be accurate. The work carried out on various models mentioned above is purely based on theoretical aspect. However, in this work, we included the experimental values of hybrid dielectric constant and implementation of finite difference method for solving the Poisson equation to get the charge density. Then, using the charge density and Green’s function the potential on conductor and the static capacitance have been determined. Further, the work is extended for the estimation of the various capacitances for 32 nm technology node using the model reported by Kurokawa et al. and references therein [19] for one and two ground planes; combinations of these two fundamental structures are useful to pretend layout of interconnect structures of high speed IC [20]. For all the simulation work the low dielectric constant (k = 2.97) value used is of the hybrid thin film deposited by us [21].
Gh ¼
1 X eam Dx pjam j m¼1 eox cothðtox am Þ þ es cothðts am Þ ½es cothðt s am Þ½1 þ eox cothðt ox am Þ þ eox ½eox þ eox cothðt ox am Þ
ð2Þ 2mpþh , p
where am is given by the following expression, am ¼ m is the integer, P is the pitch as shown in Fig. 1. The thickness of the oxide layer is tox, while ts is the thickness of the substrate. eox and es are the dielectric constant of oxide layer and substrate respectively.
V¼
Z
W=2
W=2
Gh qh dx
ð3Þ
2. Mathematical approach 2.1. Green function and Poisson equation Fig. 2. (a) Typical structure of interconnect geometry on one ground plane.
The Metal Insulator Semiconductor (MIS) structures, shown in Fig. 1 have been used to realize the potential and static capacitance under the metal line strip. The Poisson equation (1a) [22] has been solved by using finite difference method to obtain the values of electron and hole concentrations. Further, the charge density equation is estimated using the values of electron and hole concentration in accordance to Eq. (1b) [23] for the given interconnect structure.
d dx
eðxÞ
d q /ðxÞ ¼ pðxÞ nðxÞ þ Nþd ðxÞ Na ðxÞ dx eo
qh ¼ q p þ Nþd n Na
ð1aÞ ð1bÞ
where /, q, e and eo are the electrostatic potential, electric charge dielectric constant and permittivity of vacuum respectively. The n and p are the free electron and hole densities and Nþ d and N a are position dependent ionized acceptor and donor concentrations. Further, to realize the potential, the Green function [24–26] Eq. (2) has been solved. The green’s function equation used here is according to the work carried out by Yamashita et al. and they have already performed the Fourier transform of two dimensional Lapalce equation and they have given the resultant expression as shown in Eq. (2) [27]. The charge density and Green Function’s output are integrated as given in Eq. (3).
Fig. 1. Schematic of Metal Insulator Semiconductor (MIS) structure.
Fig. 2. (b) Interconnect structure between two ground planes.
Fig. 2. (c) Capacitance voltage curve of deposited hybrid low-k thin film (k 2.97) [28]. Inset figure is SEM image.
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Here, W is the width of the metal line, Gh is Green function and qh is the charge density function. The values of potential, derived from Eq. (3) have been used to determine the static capacitance by using Eq. (4).
Cs ¼
1 V
Z
W=2
W=2
qh dx
ð4Þ
A detailed structure of interconnect geometry with one ground plane and two ground plane is presented in Fig. 2a and b respectively, that clearly elaborates the lateral, crossover and overlap capacitance between different metal lines. The lateral capacitance is the capacitance between parallel edges of two metal lines in same plane also known as coupling capacitance. The capacitance between the edge of one metal and surface area of other metal above or below the first metal is called as crossover or fringe capacitance, whereas the parallel plate capacitance or the capacitance between surfaces of two metals is known as overlap capacitance. Fig. 2b shows interconnect schematic geometry of two metal lines with insulating material along with different capacitances. The thin layer used in between the metal lines is Interlayer Dielectric (ILD). These, ILD need to have low dielectric constant to reduce the RC delay of the ULSI circuit for achieving high speed. Hence, we have worked to produce the hybrid low dielectric thin films deposited via spin coating technique in which methylmethacrylate (MMA organic material) is doped in SiO2. The thin films deposited by us yields the low dielectric constant with k 2.97. Further the dielectric constant is also determined by forming the Metal Insulator Semiconductor (MIS) structure explained elsewhere [28]. The paper presents the detail analysis of overlap, lateral and crossover capacitances for one ground and two ground plane structures. These, capacitances show dependence on wire width, wire spacing and wire thickness. The equations involved in the analysis of these capacitances are given below [19].
2.3. Line to line capacitance (coupling/lateral capacitance) It is obligatory to investigate coupling capacitance, as for the high aspect ratio and the increased line thickness increases delay in the device and creates high signal coupling noises. These limitations will hamper to the practical implementation of scaling techniques. Thus, inclusion of low dielectric material in place of SiO2 effectively reduces interconnect parasitic capacitances by lowering the RC delay and crosstalk effect. One ground plane:
0 B C L ¼ e@
1:064
T S
Tþ2H Tþ2Hþ0:5S
0:695
þ
W Wþ0:8S
1:414
0:055 W 2H þ0:831 Wþ0:8S 2Hþ0:5S
0:804 1 Tþ2H Tþ2Hþ0:5S C A 3:542 ð6aÞ
Two Ground Plane:
0 1 H H T T T 1 1:879e0:31S 2:474S þ 1:302e0:082S 0:1292e1:326S S B C S C L ¼ e@ A W þ1:722 1 0:654e0:3477H e0:651H ð6bÞ
2.2. Line to ground capacitance (Overlap capacitance) The interlayer dielectric has been a bottleneck for the efficient performance of the devices. As already discussed, present low dielectric material cannot meet all the required characteristics of recent ITRS in all respects. The parasitic capacitance is very vital and has a high impact on device and circuit performance. The parasitic capacitance makes significant distortion in device and degrades its performance, while the spacer dielectric material drastically influence to the fringing capacitance. Hence, to have a divergence to the rising RC delay, it is very much essential to have advances in geometrical structures and material perspective. In this paper, we had used the following physical models which have higher accuracy with new geometrical aspects in terms of the dimension wise and the new material perspective of using the fabricated MIS structure’s dielectric constant determined through CV curves obtained from the Keithley CV 590 system. The miniaturization of the devices has led to reduction in the interconnect dimensions to be lowered and due to this the delay becomes much larger. It is very necessary to note that the high aspect ratio is imperative in metal to ground capacitance which is directly proportional to line width and material dielectric constant has observed from the following equation (5). One ground plane:
CO ¼ e
0:023 1:16 ! W T S þ 3:28 H T þ 2H S þ 2H
Fig. 3. Variation of potential with increase in metal line width obtained through Poisson equation.
ð5aÞ
Two ground plane:
W T S þ 1:086 1 þ 0:685e1:343S 0:9964e1:421H CO ¼ e H
ð5bÞ Fig. 4. Variation of potential with increase in spacing between metal lines.
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2.4. Crossover / fringe capacitance
0 B B B B B B C C ¼ eB B B B B @
3. Results and discussion
0:2 1 T 1 S1 S1 þ 0:9413 1 0:326e0:133S1 0:959e1:966H 2W 2 S1 þ0:01H C 0:2 C T 2 S2 C S2 0:133S2 C þ0:9413 1 0:326e 0:950e1:966H 2W 1 S2 þ0:01H C C C T 1 W 0:182 S1 C 0:5 2 þ1:14 1 0:326e0:133S1 0:959e1:966H ðS2 S1 Þ C H C C T 2 A S2 0:182 0:5 þ1:14 1 0:326e0:133S2 0:9591:966H ðS1 S2 Þ WH1
W1 W2 H
ð7Þ where the CO is the overlap capacitance, CL is line to line capacitance, CC is crossover capacitance, e is dielectric constant, W is width of interconnect, T is thickness of interconnect, S is spacing between two interconnects in plane, H is thickness of dielectric. The total capacitance CT is determined by adding the CO, CL, CC for respective planes.
In present work, we have focused ourselves to realize the impact of various dimensional parameters incorporation with the measured dielectric constant of the hybrid low-k (2.97) thin film deposited by us. As mentioned above, the capacitance voltage curve of deposited hybrid low-k thin film determined from CV 590 is shown in Fig. 2c [28] with variation in biasing voltage from 1 V to 5 V. The inset of Fig. 2c shows the SEM image of deposited thin film that reveals the surface of film is uniform and crack free. From Fig. 3 it has been observed that, with the decrease in the width of the metal line the potential of MIS structure under metal strip decreases. The potential have been deduced by solving the Green’s function for mode ‘0’. The charge density has been calculated through Poisson equation by using the finite difference method. The reference voltage (Vref) for calculation of the charge density has been taken to be 1 V. Utilizing the same charge density values obtained from Poisson equation the study has been extended to realize the effect of spacing between the two metal lines on potential. It has been depicted in Fig. 4 that, with the decrease in the spacing the potential founds to be increasing. The potential rises from 2.45 V to 3.8 V with the decrease in spacing from 0.31 to 0.08 lm. Interconnect and the device performance are very much interlinked and hence, it is essential to investigate the capacitances involved in device performance. Some of the existing simulation
Fig. 5. Static capacitance dependence on metal line width for the hybrid based MIS structure. Fig. 7. Overlap capacitance for one ground plane with variation in wire width and spacing.
Fig. 6. Dependence of static capacitance on spacing between two metal lines for interconnect layer of dielectric constant 2.97.
Fig. 8. Overlap capacitance for two ground plane with variation in wire width and spacing.
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software tries to investigate different geometry of the multilevel interconnect structures. However, here we have used the numerical approach for studying the variation of static capacitance in MIS structure. From Fig. 5 the variation of static capacitance has been observed to be non-linearly increasing with the decrease in width of the metal line. The increase in the static capacitance with the decrease in width may be due to the increase in the charge density and decrement in the surface area. The investigation of the static capacitance dependence on spacing between the two metal lines has been carried out as shown in Fig. 6. The static capacitance has been found to be decreasing nonlinearly. The change in static capacitance values was deduced to be 0.057 pF for the 0.08 lm spacing between metal lines. The decrement in the static capacitance with the spacing may be attributed because of the fringing capacitance and lateral capacitance. Fig. 7 represents the overlap capacitance for one ground plane due to the effect of wire width and spacing between the two metal wires. The figure clearly reveals the variation of the capacitance as observed through the different colour shades present in the three dimensional plots and the respective values of the capacitance in accordance to colour shade can be easily judged by viewing the colour bar next of the figure. It reveals from Fig. 7 that, the overlap capacitance decreases to 0.27 pF with decrease in wire width and spacing to 0.08 lm. This capacitance is actually a parallel plate
Fig. 9. Crossover capacitance with variation in wire width and spacing of hybrid interlayer dielectric.
957
Fig. 11. Coupling capacitance for two ground plane with variation in wire width and spacing.
capacitance. Hence, the overlap capacitance decreases with lowering in interconnect area. The effect of wire width and spacing between metal lines for two ground plane is shown in Fig. 8. It is observed from Fig. 8 that the reduction in wire width has negligible effect on overlap capacitance. However, the capacitance falls linearly with decrease in spacing between the metal lines from 0.35 lm to 0.08 lm. The crossover capacitance decreases from 7.52 pF to 0.01 pF drastically with decrease in spacing from 0.35 lm to 0.08 lm for fixed dielectric thickness of 0.15 lm, this is because the adjacent lines shield the substrate from the field at the edges of metal. The capacitance also lowers with the decrease in wire width giving rise to leaf shape to graph as shown in Fig. 9. The coupling capacitance is observed to be increasing nonlinearly from 1.04 pF to 1.58 pF with decrease in spacing from 0.35 lm to 0.08 lm where as no significant effect of lowering in wire width is observed on coupling capacitance as shown in Fig. 10. The effect of lowering of wire width and spacing on coupling capacitance for two ground planes is depicted in Fig. 11. Fig. 11 clearly shows as spacing decreases the coupling capacitance increases fastly, minimizing the effect of lowering in wire width. The reduced width of interconnect and interwire spacing mainly increases the coupling capacitance contributing 84% in total capacitance of interconnects in case of one ground plane. The contribution of crossover capacitance and overlap capacitance is 0.58 and 14.83% respectively. For two ground planes the contribution of coupling capacitance decreases to 68% and overlap capacitance increases to 30.87%. The CT of 2.44 pF and 1.74 pF (SiO2 k 3.9) reduced to 1.87 pF and 1.33 pF (low-k, k = 2.97) for one and two ground planes respectively. 4. Conclusions
Fig. 10. Coupling capacitance for one ground plane with variation in wire width and spacing.
The effect of metal width and spacing between two metal lines on potential and static capacitance of MIS structure has been studied by using the Green’s function. It has been observed that, potential on conductor increases for lower spacing between the metal lines whereas, the lowering of metal width enhances the static capacitance due to raised charge density. The interconnect capacitance get affected significantly by the lowering in interconnect width and interwire spacing as a requirement of 32 nm technology. The coupling capacitance contributes to total capacitance by 84% and 68% for one and two ground planes. It has been observed that, the total capacitance reduced by 76% by replacing the SiO2 dielectric with the low dielectric material deposited by us. Hence, it can be concluded that, the material deposited by us is suitable as ILD to reduce the capacitance of circuit and in turn, RC delay.
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