- Email: [email protected]
Interconnect fabrication processes and the development of low-cost wiring for CMOS products
World abstracts on microelectronics and reliability predicts the clustering of defects and the yield predictions are significantly better than traditional binomial models.
1285
a standard low cost 1.6/zm double-metal singlepoly CMOS process, has a die area of l cm 2, and is mounted in a 120-pin PGA package. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, and thus has a true asynchronous digital behavior. Experimental chip test results are available, obtained through digital chip test equipment. Fault tolerance at the system level operation is demonstrated through the experimental testing of faulty chips.
Interconnect fabrication processes and the development of low-cost wiring for CMOS products. T. J. LICATA, E. G. COLGAN,J. M. E. HARPER and S. E. LUCE. IBM J. Res. Develop., 1995, 39(4), 419. As the cost and performance of integrated circuit (IC) interconnections, or "interconnects," become increasingly important to the development and manufacturing of successful advanced IC products, so also do A silicon-on-silicon field programmable multichip underlying metallization and patterning processes. In model (FPMCM)---integrating FPGA and MCM particular, the goals of achieving product design technologies. JOEL DARNAUER, TSUYOSHI ISSHIKI, specifications, low development cost (high and early PORFIRIO GARAY, JOHN RAMIREZ, VIJAYSHR1 yield), low manufacturing cost, and portability across MAHESHWEARI and WAYNE WEI-MING DAI. IEEE products can only result from applying robust unit Transactions on Components, Packaging and Manuprocesses that combine to form integrable and facturing Technology--Part B, 1995, 18(4), 601. scalable process modules. In this paper, we review the Multichip module technology can dramatically interconnect fabrication processes used to form increase the capability of field programmable logic currently manufactured IBM CMOS products, and devices (FPLD's) and field programmable systems describe the materials and process integration issues (FPS). We present the special advantages that that motivated their selection. In addition, we MCM's offer FPLD's and the design of our identify factors which may inhibit application of the first-generation field programmable multichip modfabrication processes to future products having ule (FPMCM). Our prototype is the first siliconsmaller dimensions. The review suggests that large on-silicon FPMCM and has a maximum capacity improvements in cost and scalability can be achieved of 40 K gates and 256 user IO, achieving a factor by forming dual-damascene monolithic studs/wires. of four increase in capacity over the FPLD family Previously, the dual-damascene approach was not with which it was designed. Our FPMCM has generally applicable because of the lack of suitable been demonstrated in a system that can deliver metal deposition techniques for filling high-aspect200 MOP's of computing power for image processing ratio features with highly conductive metal. However, applications. recent advances may provide that capability both FPMCM's can cost-effectively deliver four-eight for near-term applications using Al-based wiring, and times the capacity of the largest FPLD's and provide also for future applications using more extendible even larger reductions in the area of PCB-based field Cu-based wiring. programmable systems. The upper capacity limits for A real-time clustering microchip neural engine. TERESA FPMCM are determined mainly by the cost and SERRANO-GOTARREDONA and BERNABE LINARES- defect density of the substrate technology. As CMOS BARRANCO. IEEE Transactions on Very Large Scale processes move into the deep-submicron range, Integration (VLSI) Systems, 1996, 4(2), 195. This FPMCM's will lead to even faster and denser paper presents an analog current-mode VLSI substrates. implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the Low-temperature chemical vapour deposition processes popular ARTI algorithm, but has been modified and dielectrics for microelectronic circuit manufacturresulting in a more VLSI-friendly algorithm that ing at IBM. D. R. COTE, S. V. NGUYEN, W. J. COTE, S. allows a more efficient hardware implementation with L. PENNINGTON,A. K. STAMPERand D. V. PODLESNIK. simple circuit operators, little memory requirements, IBM J. Res. Develop., 1995, 39(4), 437. Significant modular chip assembly capability, and higher speed progress has been made over the past decade in figures. The chip described in this paper implements low-temperature plasma-enhanced and thermal a network that can cluster 100 binary pixels input chemical vapour deposition (CVD). The progress has patterns into up to 18 different categories. Modular occurred in response to the high demands placed on expansibility of the system is directly possible by the insulators of multilevel microelectronic circuits assembling an N x M array of chips without any because of the continuing reduction in circuit extra interfacing circuitry, so that the maximum dimensions. High-aspect-ratio gap filling is foremost number of clusters is 18 x M and the maximum among these demands, which also include lower number of bits of the input pattern is N × 100. processing temperatures and improved dielectric Pattern classification and learning is performed in planarization. This paper reviews the history of 1.8 k~s, which is an equivalent computing power of interlevel and intermetal dielectrics used in microelec4.4 x 109 connections per second plus connection- tronic circuit manufacturing at IBM and the current updates per second. The chip has been fabricated in status of processes used in IBM manufacturing and
1285
a standard low cost 1.6/zm double-metal singlepoly CMOS process, has a die area of l cm 2, and is mounted in a 120-pin PGA package. Although internally the chip is analog in nature, it interfaces to the outside world through digital signals, and thus has a true asynchronous digital behavior. Experimental chip test results are available, obtained through digital chip test equipment. Fault tolerance at the system level operation is demonstrated through the experimental testing of faulty chips.
Interconnect fabrication processes and the development of low-cost wiring for CMOS products. T. J. LICATA, E. G. COLGAN,J. M. E. HARPER and S. E. LUCE. IBM J. Res. Develop., 1995, 39(4), 419. As the cost and performance of integrated circuit (IC) interconnections, or "interconnects," become increasingly important to the development and manufacturing of successful advanced IC products, so also do A silicon-on-silicon field programmable multichip underlying metallization and patterning processes. In model (FPMCM)---integrating FPGA and MCM particular, the goals of achieving product design technologies. JOEL DARNAUER, TSUYOSHI ISSHIKI, specifications, low development cost (high and early PORFIRIO GARAY, JOHN RAMIREZ, VIJAYSHR1 yield), low manufacturing cost, and portability across MAHESHWEARI and WAYNE WEI-MING DAI. IEEE products can only result from applying robust unit Transactions on Components, Packaging and Manuprocesses that combine to form integrable and facturing Technology--Part B, 1995, 18(4), 601. scalable process modules. In this paper, we review the Multichip module technology can dramatically interconnect fabrication processes used to form increase the capability of field programmable logic currently manufactured IBM CMOS products, and devices (FPLD's) and field programmable systems describe the materials and process integration issues (FPS). We present the special advantages that that motivated their selection. In addition, we MCM's offer FPLD's and the design of our identify factors which may inhibit application of the first-generation field programmable multichip modfabrication processes to future products having ule (FPMCM). Our prototype is the first siliconsmaller dimensions. The review suggests that large on-silicon FPMCM and has a maximum capacity improvements in cost and scalability can be achieved of 40 K gates and 256 user IO, achieving a factor by forming dual-damascene monolithic studs/wires. of four increase in capacity over the FPLD family Previously, the dual-damascene approach was not with which it was designed. Our FPMCM has generally applicable because of the lack of suitable been demonstrated in a system that can deliver metal deposition techniques for filling high-aspect200 MOP's of computing power for image processing ratio features with highly conductive metal. However, applications. recent advances may provide that capability both FPMCM's can cost-effectively deliver four-eight for near-term applications using Al-based wiring, and times the capacity of the largest FPLD's and provide also for future applications using more extendible even larger reductions in the area of PCB-based field Cu-based wiring. programmable systems. The upper capacity limits for A real-time clustering microchip neural engine. TERESA FPMCM are determined mainly by the cost and SERRANO-GOTARREDONA and BERNABE LINARES- defect density of the substrate technology. As CMOS BARRANCO. IEEE Transactions on Very Large Scale processes move into the deep-submicron range, Integration (VLSI) Systems, 1996, 4(2), 195. This FPMCM's will lead to even faster and denser paper presents an analog current-mode VLSI substrates. implementation of an unsupervised clustering algorithm. The clustering algorithm is based on the Low-temperature chemical vapour deposition processes popular ARTI algorithm, but has been modified and dielectrics for microelectronic circuit manufacturresulting in a more VLSI-friendly algorithm that ing at IBM. D. R. COTE, S. V. NGUYEN, W. J. COTE, S. allows a more efficient hardware implementation with L. PENNINGTON,A. K. STAMPERand D. V. PODLESNIK. simple circuit operators, little memory requirements, IBM J. Res. Develop., 1995, 39(4), 437. Significant modular chip assembly capability, and higher speed progress has been made over the past decade in figures. The chip described in this paper implements low-temperature plasma-enhanced and thermal a network that can cluster 100 binary pixels input chemical vapour deposition (CVD). The progress has patterns into up to 18 different categories. Modular occurred in response to the high demands placed on expansibility of the system is directly possible by the insulators of multilevel microelectronic circuits assembling an N x M array of chips without any because of the continuing reduction in circuit extra interfacing circuitry, so that the maximum dimensions. High-aspect-ratio gap filling is foremost number of clusters is 18 x M and the maximum among these demands, which also include lower number of bits of the input pattern is N × 100. processing temperatures and improved dielectric Pattern classification and learning is performed in planarization. This paper reviews the history of 1.8 k~s, which is an equivalent computing power of interlevel and intermetal dielectrics used in microelec4.4 x 109 connections per second plus connection- tronic circuit manufacturing at IBM and the current updates per second. The chip has been fabricated in status of processes used in IBM manufacturing and