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RF inductors and capacitors integrated on silicon chip by CMOS compatible Cu interconnect technology
Microelectronics Reliability 43 (2003) 367–370 www.elsevier.com/locate/microrel
RF inductors and capacitors integrated on silicon chip by CMOS compatible Cu interconnect technology q Guo Lihui *, Yu Mingbin, Foo Pang Dow Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, 117685 Singapore, Singapore Received 11 July 2002
Abstract High-Q inductors and high-density capacitors have been designed and fabricated with a post-process of additional metal layers on the top of interconnect layers. The fabrication was carried out with advanced Cu interconnect technology, which was compatible with nowadays CMOS backend of line. The Qmax of inductors with inductance from 0.4 to 11 nH was over 11 on low-resistivity silicon substrates. Two kinds of structures of on-chip capacitors, MIM and MIMIM, have been studied. A capacitance of 1.75 fF/lm2 has been achieved with MIMIM structure using Si3 N4 as dielectric. Ó 2003 Elsevier Science Ltd. All rights reserved.
1. Introduction RF inductors and capacitors are the key components for RF communication systems. It strongly impacts the quality of RF circuits and systems. Nowadays, different kinds of RF transceivers are designed and fabricated with CMOS technology on silicon wafers to achieve the benefit of low cost, small in size and mass production. However, it has been found that the major bottleneck for achieving high quality RF systems with CMOS technology comes from the RF passive components rather than CMOS transistors for working frequency under 6 GHz. Generally speaking, off-chip inductors and capacitors should be used to achieve high quality for RF applications and, as the result, the cost and the volume of system become sacrificial factors. Therefore, to achieve RF on-chip inductors with high Q-value and capacitors with high capacitance density has been a very important research area in recent years. Burghartz et al.
q An earlier version of this paper was published in Proceedings of the European Microelectronics Packaging and Interconnection Symposium (IMAPS-Europe), Cracow, 16–18 June 2002, pp. 251–4. * Corresponding author. E-mail address: [email protected] (G. Lihui).
published an early study about the on-chip inductors and capacitors fabricated using M2/M3/M4 layers of 0.8 lm CMOS interconnect standard process [1]. The maximum Q-value of 9.3 was achieved with inductance of 1.95 nH. The wires of spiral inductors were made of AlCu film. To highly improve the Q-value of inductors, some unconventional structures and processes have been used, such as three-dimensional coil inductor [2], using spin-on photosensitive varnish as thick interlayer [3] and using MEMS technology to hollow or suspend the structure [4,5]. However, the high Q-value of on-chip inductors achieved by those unconventional methods suffers the cost of complex process and different technology or, together with decreasing the mechanical strength. Therefore, they are, more or less, not easy for fabrication and practical usage. Cu-damascene interconnect technology has been introduced into IC backend interconnect process along with 0.18 and 0.13 lm CMOS technology, with which people have considered and realized the integration of RF passive components on chip using Cu-damascene technology. Burghartz, et al., reported their study of on-chip inductor fabricated using Cu-damascene technology [6]. However, the study was mainly focused on highresistivity substrates and, only few testing points were made for low-resistivity silicon. In this paper, RF inductors and capacitors were fabricated on low-resistivity
0026-2714/03/$ - see front matter Ó 2003 Elsevier Science Ltd. All rights reserved. doi:10.1016/S0026-2714(02)00344-X
368
Guo Lihui et al. / Microelectronics Reliability 43 (2003) 367–370
silicon substrates with advanced Cu/SiO2 damascene technology, which is for 0.18 lm CMOS backend process. On-chip inductors and capacitors were designed and integrated within the top metal layer and an additional metal layer on the top metal layer. High-Q inductors, high-density capacitors and good uniformity on wafers have been achieved.
2. Structure and fabrication of the components In previous works, such as published in Ref. [1], the on-chip inductor was usually designed and fabricated within the interconnect layers, e.g. using the top metal layer and the second top layer. RF designers normally follow the design rules of backend process in their design of RF inductors. Those design rules were particularly developed for digital technology and extended into RF passives to meet the rapid increasing demand of RF CMOS circuits in recent years. However, the quality of RF passives, e.g. the Q-value of inductors, based on those design and integration is hard to be improved since the geometric sizes of passives are strictly limited by the design rules. Fig. 1 shows the schematic structure of inductors and capacitors studied. The thickness of the metal has been increased by an additional metal layer on the top of interconnect layers. However, the fabrication is fully compatible with the facilitiesÕ capabilities for 0.18 lm interconnect technology. The proposed structure can be employed in RF applications in two areas. One is directly used for RF chip, where the number of active devices are limited and the density of interconnect wires are quite low, therefore, the interconnect wires can be associated with RF passives in the same metal layers. The other is for system on chip (SoC) application, where the structure of Fig. 1 can be added on the top of multi-interconnect layers existed for digital circuits.
The fabrication was carried out with using Cu/SiO2 damascene technology. A low resistivity, 1–10 X cm, silicon wafer was used as substrates, which are the same as that used in normal CMOS process. A silicon dioxide, SiO2 , layer was deposited with thickness of 2–4 lm as an insulator between the substrate and the passives. After the formation of under pass for inductors, not shown in Fig. 1, a silicon nitride, Si3 N4 , layer was deposited as an etching stop layer in fabrication process. A SiO2 layer was consequently deposited on the Si3 N4 layer as shown in Fig. 1 and patterned for filling the metal, Cu. Cu was filled with electro-chemical plating (ECP) after Tantalum (Ta) as a barrier layer and Cu seed layer were sputtered. After that, chemical mechanical polishing (CMP) was performed to make the first Cu layer planar. The bottom electrode of MIM capacitor and part of spiral inductor were formed at the same time. The thickness of the first Cu layer was decided by the thickness of the SiO2 layer, which was about 2 lm. The sec, acts as the ond Si3 N4 layer in Fig. 1, about 700 A etching stop layer, and meanwhile, as the dielectric for MIM capacitor. In order to improve the break-down was voltage of MIM capacitor, a Ta layer about 1000 A used and, also acts as the thin film for resistor. After patterning the Ta layer, the third SiO2 layer in Fig. 1 with thickness of 2 lm was deposited and the second damascene process was applied. The up-electrode of MIM capacitor, the upper part of spiral inductor and the electrodes of resistor are formed with another round of ECP and CMP. The fabrication of spiral inductor, MIM capacitor and thin film resistor were completed. The final thickness of inductorsÕ spiral was measured to be 3.7 lm. In this study, MIMIM structure of capacitor has also been fabricated by repeating the aforementioned damascene process. In order to test the structures, Aluminum (Al) pads, not shown in Fig. 1, were fabricated on the outputs of the electrodes.
3. Results and discussion The RF testing of spiral inductors with two ports was conducted with HP 8510C network analyzer. Effective inductance, Leff and Q-value of inductors were deduced from the measured S-parameters in a conventional procedure as following: (1) y11 was directly drawn from S-parameters [7]; and (2) Leff and Q were achieved with the formulae,
Leff ¼
Fig. 1. Schematic structure of passive components on silicon substrate.
Q¼
imageð1=y11 Þ 2pf
imageð1=y11 Þ realð1=y11 Þ
Guo Lihui et al. / Microelectronics Reliability 43 (2003) 367–370
Fig. 2(a) and (b) shows the results of Leff and Q in RF frequency region for a set of circular spiral inductors with turns from 1 to 8. Ls that indicates the inductance at 0.5 GHz has a region from 0.4 to 11 nH, which is currently suitable for the most of RF applications. And, from Fig. 2(b), it is not difficult to find that this set of inductors has good Q-values at around 2 GHz, which is resulted from the designed optimal geometric sizes of inductors for that frequency region, such as the central hole, the wire width and the wire space. Fig. 3 shows the peak of Q-value, Qmax , and corresponding frequency, fQ max , of the inductors. It is easy to find that all Qmax -values are larger than 11 for whole set of inductors with the turns from 1 to 8, which may be the highest values for a set of inductors ever reported to our own knowledge. The wafer-map has been checked for both inductance and Q-value. The variation of inductance is less than 0.56%, and the variation of Q-value less than 2.69% on a whole 8-in. wafer. The yield on a wafer is 100%. Fig. 4 indicates the capacitance of MIM capacitor and MIMIM capacitor with various area size of the electrodes. The capacitance densities for MIM structure and MIMIM structure are 0.89 fF/lm2 and 1.75 fF/lm2 , Si3 N4 as the respectively, with the thickness of 700 A dielectric. MIMIM structure gives near double value of capacitance density, which is able to be used to save the area for RF designers. The MIM capacitors with 325 A
369
Fig. 3. Maximum Q-value, Qmax , and the frequency for Qmax versus turns of inductors.
µ Fig. 4. Capacitance of MIM and MIMIM capacitors with various area of the electrodes.
Si3 N4 dielectric have also been measured, which can provide 1.9 fF/lm2 of capacitance density. As a deduction, capacitance density of 3.8 fF/lm2 can be achieved if MIMIM structure is coordinated with the dielectric of Si3 N4 . However, the benefit of capacitance density 325 A comes along with the increasing of the leakage current and decreasing of the yield. The leakage currents at bias of 5 V are 0.03–0.04 fA/lm2 for MIM and 0.06–0.08 fA/ Si3 N4 , respectively. lm2 for MIMIM with 700 A Fig. 5 depicts the capacitance of MIM structure with Si3 N4 changes with RF frequency. The capaci700 A tance is deduced according to the formula as following: Capacitance ¼
1 2pf imageð1=y11 Þ
The sharp increase of capacitance means the happening of resonance. The larger the capacitance, the lower the resonant frequency. The effective resonant inductance can be deduced from the resonant frequency and capacitance, Fig. 2. Effective inductance, Leff and Q-value varying with frequency for a set of circular inductors.
Leff
res
¼
1 ð2pfres Þ2 C
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Guo Lihui et al. / Microelectronics Reliability 43 (2003) 367–370
Fig. 5. Capacitance of MIM capacitors versus frequency.
of inductors with inductance from 0.4 to 11 nH are larger than 11, which may be the highest reported Qvalues for a set of inductors made on a low-resistivity Si substrate using interconnect technology. MIM and MIMIM structures for on-chip capacitors have been studied. MIMIM structure can achieve near double capacitance of MIM structure with a same top area. The leakage current has been measured and studied at 5 V bias. RF testing shows that the resonance phenomenon of the capacitor limits the application of capacitors with relatively large capacitance in high GHz region. Very good uniformity can be achieved for RF inductors and capacitors with our Cu/SiO2 interconnect technology.
Acknowledgements The authors like to thank the people of DSIC-MD department of IME for their support in fabrication process and, Dr. C.R. Subhash and Mr. Xiong Yongzhong for their support in RF test and Dr. Liao Huai Lin for reviewing the manuscript.
µ Fig. 6. Effective resonant inductance versus electrodes area of capacitors.
where fres and Leff res are the resonant frequency and effective resonant inductance introduced by the electrodes and leading wires, which is shown in Fig. 6. The intersection of fitted linear line with y-axis in Fig. 6 gives out the leading wiresÕ inductance. The size of the leading wires is fixed for all capacitors in our design. The inductance contributed by the electrodes is proportional to the surface size.
4. Conclusion High-Q spiral inductors and high-density capacitors have been integrated on a low-resistively silicon substrate with Cu/SiO3 interconnect technology, which is compatible with 0.18 lm CMOS backend process. The proposed structure can be used not only for RF IC analog chip but also for SoC chip with aforementioned top-added solution. All of maximum Q-values for a set
References [1] Burghartz JN, Soyuer M, Jenkins KA. Microwave inductors and capacitors in standard multilevel interconnect silicon technology. IEEE Trans Microwave Theory Tech 1996; 44(1):100–4. [2] Young DJ et al. Monolithic high-performance three-dimensional coil inductors for wireless communication applications. Electron Devices Meeting, 1997. Technical Digest, International Published; 1997. p. 67–70. [3] Saito K et al. A tick-Cu process for add-on interconnections using photosensitive varnish for thick interlayer dielectric. Interconnect Technology Conference, 2000. In: Proceedings of the IEEE 2000. International Published; 2000. p. 123–5. [4] Lopez-Villegas JM et al. Improvement of quality factor of RF integrated inductors by layout optimization. IEEE Trans Microwave Theory Tech 2000;48(1):76–83. [5] Jiang H et al. On-chip spiral inductors suspended over deep copper-lined cavities. IEEE Trans Microwave Theory Tech 2000;48(12):2415–23. [6] Burghartz JN. Monolithic spiral inductors fabricated using a VLSI Cu-damascene interconnect technology and low-loss substrates. IEEE International Electron Device Meeting (IEDMÕ96), 1996. p. 99–102. [7] Pozar DM. Microwave engineering. Addison-Wesley Publishing Company; 1993 [Chapter 5, Section 5.6].
RF inductors and capacitors integrated on silicon chip by CMOS compatible Cu interconnect technology q Guo Lihui *, Yu Mingbin, Foo Pang Dow Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, 117685 Singapore, Singapore Received 11 July 2002
Abstract High-Q inductors and high-density capacitors have been designed and fabricated with a post-process of additional metal layers on the top of interconnect layers. The fabrication was carried out with advanced Cu interconnect technology, which was compatible with nowadays CMOS backend of line. The Qmax of inductors with inductance from 0.4 to 11 nH was over 11 on low-resistivity silicon substrates. Two kinds of structures of on-chip capacitors, MIM and MIMIM, have been studied. A capacitance of 1.75 fF/lm2 has been achieved with MIMIM structure using Si3 N4 as dielectric. Ó 2003 Elsevier Science Ltd. All rights reserved.
1. Introduction RF inductors and capacitors are the key components for RF communication systems. It strongly impacts the quality of RF circuits and systems. Nowadays, different kinds of RF transceivers are designed and fabricated with CMOS technology on silicon wafers to achieve the benefit of low cost, small in size and mass production. However, it has been found that the major bottleneck for achieving high quality RF systems with CMOS technology comes from the RF passive components rather than CMOS transistors for working frequency under 6 GHz. Generally speaking, off-chip inductors and capacitors should be used to achieve high quality for RF applications and, as the result, the cost and the volume of system become sacrificial factors. Therefore, to achieve RF on-chip inductors with high Q-value and capacitors with high capacitance density has been a very important research area in recent years. Burghartz et al.
q An earlier version of this paper was published in Proceedings of the European Microelectronics Packaging and Interconnection Symposium (IMAPS-Europe), Cracow, 16–18 June 2002, pp. 251–4. * Corresponding author. E-mail address: [email protected] (G. Lihui).
published an early study about the on-chip inductors and capacitors fabricated using M2/M3/M4 layers of 0.8 lm CMOS interconnect standard process [1]. The maximum Q-value of 9.3 was achieved with inductance of 1.95 nH. The wires of spiral inductors were made of AlCu film. To highly improve the Q-value of inductors, some unconventional structures and processes have been used, such as three-dimensional coil inductor [2], using spin-on photosensitive varnish as thick interlayer [3] and using MEMS technology to hollow or suspend the structure [4,5]. However, the high Q-value of on-chip inductors achieved by those unconventional methods suffers the cost of complex process and different technology or, together with decreasing the mechanical strength. Therefore, they are, more or less, not easy for fabrication and practical usage. Cu-damascene interconnect technology has been introduced into IC backend interconnect process along with 0.18 and 0.13 lm CMOS technology, with which people have considered and realized the integration of RF passive components on chip using Cu-damascene technology. Burghartz, et al., reported their study of on-chip inductor fabricated using Cu-damascene technology [6]. However, the study was mainly focused on highresistivity substrates and, only few testing points were made for low-resistivity silicon. In this paper, RF inductors and capacitors were fabricated on low-resistivity
0026-2714/03/$ - see front matter Ó 2003 Elsevier Science Ltd. All rights reserved. doi:10.1016/S0026-2714(02)00344-X
368
Guo Lihui et al. / Microelectronics Reliability 43 (2003) 367–370
silicon substrates with advanced Cu/SiO2 damascene technology, which is for 0.18 lm CMOS backend process. On-chip inductors and capacitors were designed and integrated within the top metal layer and an additional metal layer on the top metal layer. High-Q inductors, high-density capacitors and good uniformity on wafers have been achieved.
2. Structure and fabrication of the components In previous works, such as published in Ref. [1], the on-chip inductor was usually designed and fabricated within the interconnect layers, e.g. using the top metal layer and the second top layer. RF designers normally follow the design rules of backend process in their design of RF inductors. Those design rules were particularly developed for digital technology and extended into RF passives to meet the rapid increasing demand of RF CMOS circuits in recent years. However, the quality of RF passives, e.g. the Q-value of inductors, based on those design and integration is hard to be improved since the geometric sizes of passives are strictly limited by the design rules. Fig. 1 shows the schematic structure of inductors and capacitors studied. The thickness of the metal has been increased by an additional metal layer on the top of interconnect layers. However, the fabrication is fully compatible with the facilitiesÕ capabilities for 0.18 lm interconnect technology. The proposed structure can be employed in RF applications in two areas. One is directly used for RF chip, where the number of active devices are limited and the density of interconnect wires are quite low, therefore, the interconnect wires can be associated with RF passives in the same metal layers. The other is for system on chip (SoC) application, where the structure of Fig. 1 can be added on the top of multi-interconnect layers existed for digital circuits.
The fabrication was carried out with using Cu/SiO2 damascene technology. A low resistivity, 1–10 X cm, silicon wafer was used as substrates, which are the same as that used in normal CMOS process. A silicon dioxide, SiO2 , layer was deposited with thickness of 2–4 lm as an insulator between the substrate and the passives. After the formation of under pass for inductors, not shown in Fig. 1, a silicon nitride, Si3 N4 , layer was deposited as an etching stop layer in fabrication process. A SiO2 layer was consequently deposited on the Si3 N4 layer as shown in Fig. 1 and patterned for filling the metal, Cu. Cu was filled with electro-chemical plating (ECP) after Tantalum (Ta) as a barrier layer and Cu seed layer were sputtered. After that, chemical mechanical polishing (CMP) was performed to make the first Cu layer planar. The bottom electrode of MIM capacitor and part of spiral inductor were formed at the same time. The thickness of the first Cu layer was decided by the thickness of the SiO2 layer, which was about 2 lm. The sec, acts as the ond Si3 N4 layer in Fig. 1, about 700 A etching stop layer, and meanwhile, as the dielectric for MIM capacitor. In order to improve the break-down was voltage of MIM capacitor, a Ta layer about 1000 A used and, also acts as the thin film for resistor. After patterning the Ta layer, the third SiO2 layer in Fig. 1 with thickness of 2 lm was deposited and the second damascene process was applied. The up-electrode of MIM capacitor, the upper part of spiral inductor and the electrodes of resistor are formed with another round of ECP and CMP. The fabrication of spiral inductor, MIM capacitor and thin film resistor were completed. The final thickness of inductorsÕ spiral was measured to be 3.7 lm. In this study, MIMIM structure of capacitor has also been fabricated by repeating the aforementioned damascene process. In order to test the structures, Aluminum (Al) pads, not shown in Fig. 1, were fabricated on the outputs of the electrodes.
3. Results and discussion The RF testing of spiral inductors with two ports was conducted with HP 8510C network analyzer. Effective inductance, Leff and Q-value of inductors were deduced from the measured S-parameters in a conventional procedure as following: (1) y11 was directly drawn from S-parameters [7]; and (2) Leff and Q were achieved with the formulae,
Leff ¼
Fig. 1. Schematic structure of passive components on silicon substrate.
Q¼
imageð1=y11 Þ 2pf
imageð1=y11 Þ realð1=y11 Þ
Guo Lihui et al. / Microelectronics Reliability 43 (2003) 367–370
Fig. 2(a) and (b) shows the results of Leff and Q in RF frequency region for a set of circular spiral inductors with turns from 1 to 8. Ls that indicates the inductance at 0.5 GHz has a region from 0.4 to 11 nH, which is currently suitable for the most of RF applications. And, from Fig. 2(b), it is not difficult to find that this set of inductors has good Q-values at around 2 GHz, which is resulted from the designed optimal geometric sizes of inductors for that frequency region, such as the central hole, the wire width and the wire space. Fig. 3 shows the peak of Q-value, Qmax , and corresponding frequency, fQ max , of the inductors. It is easy to find that all Qmax -values are larger than 11 for whole set of inductors with the turns from 1 to 8, which may be the highest values for a set of inductors ever reported to our own knowledge. The wafer-map has been checked for both inductance and Q-value. The variation of inductance is less than 0.56%, and the variation of Q-value less than 2.69% on a whole 8-in. wafer. The yield on a wafer is 100%. Fig. 4 indicates the capacitance of MIM capacitor and MIMIM capacitor with various area size of the electrodes. The capacitance densities for MIM structure and MIMIM structure are 0.89 fF/lm2 and 1.75 fF/lm2 , Si3 N4 as the respectively, with the thickness of 700 A dielectric. MIMIM structure gives near double value of capacitance density, which is able to be used to save the area for RF designers. The MIM capacitors with 325 A
369
Fig. 3. Maximum Q-value, Qmax , and the frequency for Qmax versus turns of inductors.
µ Fig. 4. Capacitance of MIM and MIMIM capacitors with various area of the electrodes.
Si3 N4 dielectric have also been measured, which can provide 1.9 fF/lm2 of capacitance density. As a deduction, capacitance density of 3.8 fF/lm2 can be achieved if MIMIM structure is coordinated with the dielectric of Si3 N4 . However, the benefit of capacitance density 325 A comes along with the increasing of the leakage current and decreasing of the yield. The leakage currents at bias of 5 V are 0.03–0.04 fA/lm2 for MIM and 0.06–0.08 fA/ Si3 N4 , respectively. lm2 for MIMIM with 700 A Fig. 5 depicts the capacitance of MIM structure with Si3 N4 changes with RF frequency. The capaci700 A tance is deduced according to the formula as following: Capacitance ¼
1 2pf imageð1=y11 Þ
The sharp increase of capacitance means the happening of resonance. The larger the capacitance, the lower the resonant frequency. The effective resonant inductance can be deduced from the resonant frequency and capacitance, Fig. 2. Effective inductance, Leff and Q-value varying with frequency for a set of circular inductors.
Leff
res
¼
1 ð2pfres Þ2 C
370
Guo Lihui et al. / Microelectronics Reliability 43 (2003) 367–370
Fig. 5. Capacitance of MIM capacitors versus frequency.
of inductors with inductance from 0.4 to 11 nH are larger than 11, which may be the highest reported Qvalues for a set of inductors made on a low-resistivity Si substrate using interconnect technology. MIM and MIMIM structures for on-chip capacitors have been studied. MIMIM structure can achieve near double capacitance of MIM structure with a same top area. The leakage current has been measured and studied at 5 V bias. RF testing shows that the resonance phenomenon of the capacitor limits the application of capacitors with relatively large capacitance in high GHz region. Very good uniformity can be achieved for RF inductors and capacitors with our Cu/SiO2 interconnect technology.
Acknowledgements The authors like to thank the people of DSIC-MD department of IME for their support in fabrication process and, Dr. C.R. Subhash and Mr. Xiong Yongzhong for their support in RF test and Dr. Liao Huai Lin for reviewing the manuscript.
µ Fig. 6. Effective resonant inductance versus electrodes area of capacitors.
where fres and Leff res are the resonant frequency and effective resonant inductance introduced by the electrodes and leading wires, which is shown in Fig. 6. The intersection of fitted linear line with y-axis in Fig. 6 gives out the leading wiresÕ inductance. The size of the leading wires is fixed for all capacitors in our design. The inductance contributed by the electrodes is proportional to the surface size.
4. Conclusion High-Q spiral inductors and high-density capacitors have been integrated on a low-resistively silicon substrate with Cu/SiO3 interconnect technology, which is compatible with 0.18 lm CMOS backend process. The proposed structure can be used not only for RF IC analog chip but also for SoC chip with aforementioned top-added solution. All of maximum Q-values for a set
References [1] Burghartz JN, Soyuer M, Jenkins KA. Microwave inductors and capacitors in standard multilevel interconnect silicon technology. IEEE Trans Microwave Theory Tech 1996; 44(1):100–4. [2] Young DJ et al. Monolithic high-performance three-dimensional coil inductors for wireless communication applications. Electron Devices Meeting, 1997. Technical Digest, International Published; 1997. p. 67–70. [3] Saito K et al. A tick-Cu process for add-on interconnections using photosensitive varnish for thick interlayer dielectric. Interconnect Technology Conference, 2000. In: Proceedings of the IEEE 2000. International Published; 2000. p. 123–5. [4] Lopez-Villegas JM et al. Improvement of quality factor of RF integrated inductors by layout optimization. IEEE Trans Microwave Theory Tech 2000;48(1):76–83. [5] Jiang H et al. On-chip spiral inductors suspended over deep copper-lined cavities. IEEE Trans Microwave Theory Tech 2000;48(12):2415–23. [6] Burghartz JN. Monolithic spiral inductors fabricated using a VLSI Cu-damascene interconnect technology and low-loss substrates. IEEE International Electron Device Meeting (IEDMÕ96), 1996. p. 99–102. [7] Pozar DM. Microwave engineering. Addison-Wesley Publishing Company; 1993 [Chapter 5, Section 5.6].