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Black Diamond™ layer in CMOS interconnect process for RF passive components
Microelectronics Reliability 44 (2004) 581–585 www.elsevier.com/locate/microrel
Integrating thick copper/Black Diamonde layer in CMOS interconnect process for RF passive components Guo Lihui, Zhang Yibin *, Su Yong Jie Jeffrey Semiconductor Process Technology Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, 117685 Singapore, Singapore Received 29 August 2003; received in revised form 1 December 2003
Abstract Thick copper (Cu)/Black Diamonde (BD) layer up to 4 lm has successfully been integrated in CMOS interconnect process to improve the quality of on-chip RF passive components. It is shown that BD film is easy to crack when its thickness is up to 4 lm. However, by inserting one or few layers of dielectric material, BloKe, the stress in the entire dielectric film stack can be reduced. Although the reduction of the tensile stress of the stack is insignificant, the inserted BloKe layer effectively prevents cracking from happening in the film stack. Spiral inductors have been integrated in developed Cu/BD (4 lm) top-metal-layer. Both Q value and resonate frequency of developed inductors are improved comparing to the inductors fabricated in previous top-metal-layer with 1 lm Cu/SiO2 stack. Ó 2003 Elsevier Ltd. All rights reserved.
1. Introduction Along with the development of CMOS technology the relevant interconnect process migrates from aluminum (Al)/SiO2 (USG) scheme for 0.18 lm technology node and before towards Copper (Cu)/low k or ultra low k scheme for 0.13 lm technology node and beyond. The reason is to reduce the RC delay and power dissipation caused by metal traces and dielectric layers that compose CMOS interconnect layers of chips. Black Diamonde (BD) is one of the candidates of low k dielectrics formed with CVD carbon doped silicon oxides (SiOC) for 0.13 lm technology node and beyond. It has a k value of about 2.8 and matches well thermally with copper. BloKe is a silicon carbide (SiC) type of material and has been proved a good copper diffusion barrier and etchstop layer for BD in integration process. Both BD and BloKe can be deposited by conventional PECVD methods using the same organo-silane precursor. Integration of Cu/BD damascene structure was demon-
*
Corresponding author. Tel.: +65-6770-5771; fax: +65-67731914/1714. E-mail address: [email protected] (Z. Yibin).
strated in Ref. [1], in which 25% reduction in intra-lead capacitance comparing with conventional oxide integration could be realized. On the other hand, one must consider the integration of RF passives, e.g. inductors, in interconnect top-metallayer as interconnect process and technology progressing forward. However, with upgrading of technology node, the thickness of interconnect layers is getting thinner, e.g. it is less than 0.4 lm for 0.13 lm technology node. The thinner metal layer is unfavorable to RF passive components since it will enhance the ohmic loss. In order to compensate such loss, an extra thick metal layer is introduced to thicken the top-metal-layer [2,3]. The extra thick metal layer can be formed with an additional process loop after accomplishing whole interconnect process; therefore, an additional cost will be counted for that. In order to improve the quality of passive components as well as to lower the fabrication cost, it is necessary to develop a process with which a thick topmetal-layer can be directly formed without additional thickening processes. However, this will introduce great challenges in process technology, such as thick film deposition, deep trench etch and metallization. Specially, very thick dielectric film may crack because of the film stress, which makes the process impossible.
0026-2714/$ - see front matter Ó 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2003.12.006
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In this work, the top-metal-layer with 4 lm BD has been developed and integrated with conventional CMOS interconnect layers without additional top added process. In the development, the stress of thick BD has been studied, which is essential to achieve a thick layer without cracking. And, the characterization results of integrated inductors incorporated in 4 lm BD show much better RF performance than those fabricated using conventional interconnect technology.
2. Stress in thick BD film Unlike the Al/SiO2 scheme served for 0.18 lm technology node and before, the copper/low k scheme served for 0.13 lm technology node and beyond is formed by so called damascene technology [4]. In damascene process, copper traces are formed by several steps. Those are deposition of intermetal dielectric (IMD), trench etch of IMD, copper filled in trench area by electrical– chemical plating (ECP) method and chemical–mechanical polishing (CMP) of copper. Therefore, to achieve a thick BD layer as IMD is essential for achieving thick copper layer. However, it is found in our practice that the BD layer is much easy to crack than USG in integration process. It is caused by film stress. It has been known that USG film deposited on silicon with PECVD has compressive stress, therefore, is relatively not easy to crack. However, the BD film shows tensile stress [5], 4E þ 8 8E þ 8 dyne/cm2 on silicon, which makes it difficult to achieve a thick BD layer since it may induce a film crack. There are some research papers on properties of BD, but most of which deal with stress on the thermal expansion incorporating with copper to study the adhesion or Cu electromigration in damascene structure [6,7]. A few of published papers discusses the stress issue for achieving thick BD film. To research the relation between stress and film cracking of BD film, a set of samples was deposited with different thickness of BD films up to 6 lm on bare 8 in. silicon wafers. The deposition was carried out with applied materials Centura PECVD equipment using an organo-silane (Rn SiH4 n ), an oxidizer, as the precursors. The temperature of wafers during the deposition was around 350 °C. As depicted in Ref. [8], the formed film, BD, is a kind of low density silicon dioxide-like material, which is achieved by introducing network terminating species into Si–O matrix. Some of the film’s properties can be found in [7,8]. The deposition recipe has been optimized to achieve the stress of BD films on silicon as low as possible. The thickness of films could be measured using Therma Wave OptiProbe, which is a kind of commercial advanced ellipsometer. The stress measurement of the films was conducted using a commercial FSM 7800TC system, with which the stress was obtained based on the
measurement of the change in radius of curvature of the wafers. Stoney’s equation [9], rf ¼ Es ts2 =6ð1 ms Þtf R, was used and programmed in the machine to calculate the residual stress in deposited films. Where Es and ms were Young’s modulus and Poisson’s ratio of silicon wafer, respectively, ts and tf represented the thickness of the silicon wafer and deposited film, respectively, and R was the measured radius of curvature. The tested residual stress with film’s thickness is shown in Fig. 1. It is found, with the observation under a microscope, that the films are easy to crack when the thickness is over 4 lm. The thicker the film is, the more severe the crack will be as the thickness larger than 4 lm. That is because of the larger tensile stress in thick film than in thin one. The result is consistent with the report from the Ref. [5], in which the recommended film thickness should be less than 3 lm in practice. Combining the results of stress testing and the crack observation, it is found that the BD film will crack after a critical value of tensile stress that is around 35 MPa. It is obvious to achieve a BD film with 4 lm or thicker thickness needs to find a way to reduce the residual stress in the film. Normally, there are two possible ways to change the stress of film. One is to re-construct the film through a high temperature anneal, which is limited by the enduring temperature of interconnect process. Another method is to use a film with compressive stress to compensate the tensile stress of bulk BD film, which is described by Ref. [10]. The reference shows that dielectric film with tensile stress and dielectric film with compressive stress are alternately deposited on a substrate to form a stress-adjusted stack film, which can reduce the bowing of wafer and crack of the film. Because BloKe presents a high compressive stress on silicon and has been used as an etch-stop layer in CMOS Cu/BD multi-level interconnection [5], therefore, BloKe has been chosen and inserted in thick BD layer to reduce the tensile stress of BD in this study. However, the thickness of compensated BD in conventional inter-
Fig. 1. Residual stress as a function of film thickness for BD on silicon.
G. Lihui et al. / Microelectronics Reliability 44 (2004) 581–585
connection is about 0.5 lm and, it will be over 2 lm in this study. The stress compensating effectiveness of BloKe needs to be researched for thick BD layer. The BloKe is deposited in the same PECVD machine as BD under temperature about 350 °C. The inserted BloKe in thickness. Fig. 2 shows the stress layers are 500 A change with the growth of stack film. And, the stress of relevant BD thickness without BloKe insertion is also given in Fig. 2 as a comparison. The final stack’s stress may be explained by the introduced force originated from the mismatching at the interfaces of silicon/BD, silicon/BloKe and BD/BloKe. It can be found that the residual stress in 2 lm BD film drops about 6 MPa when a thin BloKe is deposited on it. That is because the compressive stress of BloKe to silicon partially compensates the tensile stress of BD to silicon. However, the residual tensile stress returns back to a higher level as the second 2 lm BD film is subsequently deposited on the stack. Comparing with 4 lm BD without insertion of BloKe, the stress reduction of 4 lm BD with the insertion is not large, only about 2 MPa. It may be be is too thin to cause that the inserted BloKe, 500 A, balance the tensile stress introduced by 4 lm BD film. When the second BloKe covers on the existing stack, there is no pulling back of the stress. It may be interpreted as the distance between the silicon and the second BloKe is large, therefore, the compensative impact of BloKe to final tensile stress of BD film will be weak. Moreover, the stress of whole stack has a little increment in tensile because BD should show a tensile stress to BloKe too. As the third layer of 2 lm BD is added on the second BloKe, the residual stress goes up further. However, the final residual stress of the stack is still less than that of 6 lm BD without insertion, even the reduction is not large. Since the residual stress is still very high, such stack film with 6 lm BD is easy to crack in the process as we observed. As it is well known that the chip will be alloyed at the final process stage, therefore, the thermal stress evolution of the film was conducted. The sample wafers were heated up to 350 °C and cooled down to room tem-
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Fig. 3. Residual thermal stress of stacks after alloying (–d–) BLoK). and before alloying (M). ( 2 lm BD, 500 A
perature. The stress was measured in situ. It was found that both BD and BloKe appeared large compressive stress at this high temperature. 700 MPa compressive stress was observed for a 1 lm BD layer on silicon and, BloKe layer on silicon, respectively. 16 GPa for a 500 A A similar result was also obtained in previous study [11]. The large compressive stress of BD and BloKe at high temperature means that both films have high coefficient of thermal expansion (CTE) compared to silicon. When the films cooled down to room temperature, for a BD without BloKe insertion, the stress turned back to tensile and the value was larger than that before alloying. That might be caused by the deformation of film. For stack film, the residual tensile stress was different with that in a single layer of BD on silicon, as shown in Fig. 3. The stress values before alloying are also predicated in the figure in isolated dots. It is not difficult to find that the coverage of BloKe on BD can remit a little in residual thermal stress. It may be interpreted as the CTE of BloKe is larger than BD and silicon and, the residual stress of BloKe after a thermal cycle may tend to be more compressive than that before alloying. However, such influence is still limited by the volume fraction of BloKe in the stack. As the result of stress study, 4 lm BD with a suitable BloKe insertion was chosen as the top IMD for topmetal-layer in interconnect integration. No cracking was found in such BD/BloKe stack film. 3. Integration of passive component and results
Fig. 2. Residual stress of film stacks of BD with insertion BLoK), and corBLoK (–d–, 2 lm BD, 500 A responding thickness of BD without insertion on BLoK (M).
The structure of integration is shown in Fig. 4. The top-metal-layer was designed in metal-4 layer. The fabrication was carried out on an 8 in. CMOS interconnect line in the Institute of Microelectronics (IME), Singapore. After three metal layers and the via-3 had been completed, 4 lm BD with a BloKe insertion was deposited on the top of via-3 layer. Then, the metal-4 layer was processed with damascene consequent process loop, which included the trench etch of BD/BloKe stack layer, barrier/seed layer deposition, copper filling
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Fig. 4. Structure of integrated inductor in metal-4 layer with 4 lm BD IMD ( Cu, USG, BD).
using electro–chemical plating (ECP) and chemical– mechanical polishing (CMP). Finally, a passivation layer, silicon nitride, was covered on chip. Spiral inductors were integrated in the metal-4 layer (4 lm thickness) and metal-3 layer (0.5 lm thickness). The coil traces of inductors in two layers were connected through via-3 layer as shown in Fig. 4. The underpass of inductors was in metal-2 layer. The RF testing of spiral inductors with two ports was conducted with HP 8510C network analyzer. Effective inductance, Leff , and Q value of inductors were deduced from the measured S parameters in a conventional procedure as following:
Fig. 5. Comparison of two 5-turn inductors with 4 lm/BD (d) and 1 lm/USG (M), respectively.
(1) After de-embedding procedure, y11 was extracted from two times measured S parameters [12]; and (2) Leff and Q were achieved with the formulae, Leff ¼
imageð1=y11 Þ 2pf
Q¼
imageð1=y11 Þ realð1=y11 Þ
As a comparison, Fig. 5 shows the inductance and Q value of two 5-turn inductors with 4 lm BD and 1 lm USG as metal-4 layer, respectively. The metal-4 layer with 1 lm USG is fabricated by a baseline CMOS interconnect process developed in IME. Since the structures under the metal-4 layer are same for both two inductors, with 4 lm BD and 1 lm USG, the difference of Q value of two inductors should be induced by the evolution of top metal-4 layer. It can be found that the Q value of inductor with 4 lm BD metal-4 layer increases nearly 50% comparing with that with 1 lm USG metal-4 layer at frequency 2–3 GHz, where most important RF applications are applied. This improvement mainly comes from the thick metal-4 layer, with which ohmic loss in inductor’s coils can be reduced. And, it also benefits from the usage of BD as IMD instead of USG. The dielectric constant of BD is about 2.8, which is lower
Fig. 6. Comparison of the maximum Q value (Qmax ) and the resonate frequency (Fres ) between inductors with 4 lm/BD (d) and 1 lm/USG (M).
G. Lihui et al. / Microelectronics Reliability 44 (2004) 581–585
than that of USG, about 4.0. It leads to a reduction of parasitic capacitance between inductor’s coils and, therefore, an enhancement of Q value. The reduction of the parasitic capacitance can be proved by the curve of effective inductance, Leff; in Fig. 5. The curve of Leff , corresponding to the inductor with 4 lm BD, moves to right, which means the resonant frequency increases because of the reduce of the parasitic capacitance. Besides the inductor with 5-turn coil, other inductors from 1- to 8-turn coil show a jump of Q value when metal-4 is changed from conventional 1 lm USG to 4 lm BD. Fig. 6 depicts the comparisons of resonate frequency and maximum Q value between two sets of inductors, which are fabricated with two different metal-4 schemes. When the turn of inductors is equal or less than 3, the resonate frequency will be larger than 20 GHz.
4. Conclusion The stress of thick Black Diamonde (BD) on silicon has been studied. The threshold value of residual stress for BD film cracking is about 35 MPa in tensile. BloKe shows a compressive stress on silicon, which can be used to compensate the tensile stress in BD. Insertion of BloKe layer(s) in thick BD can remit the residual stress. But the impact on the final stack’s stress is not large if the thickness of BloKe is small and is far from the silicon. However, the insertion can effectively prevent cracking to develop in the film stack. Adding a BloKe capping layer on BD can be used to reduce the thermal residual stress in BD to some extent also. Inductors have been incorporated in metal-4 layer with 4 lm BD as IMD. Comparing with conventional 1 lm USG metal-4 layer, new developed 4 lm BD metal-4 layer can provide inductors high Q value and good resonate frequency. The improvement in Q value comes mainly from the reduction of ohmic loss because of the thickness increment of metal-4 copper layer.
Acknowledgements The authors would like to thank Mr. The Choong Long and Ms. Zhu Hong for their help in stress test, and
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engineers in Semiconductor Process Technology Laboratory of IME who provided supports in preparation of samples.
References [1] Naik M, Parikh S, Li P, Educato J, Cheung D, Hashim I, et al. Process integration of double level copper-low k (k ¼ 2:8) interconnect. In: Interconnect Technology, 1999, IEEE International Conference, 24–26 May 1999. p. 181– 183. [2] Lihui G, Mingbin Yu, Dow FP. RF inductors and capacitors integrated on silicon chip by CMOS compatible Cu interconnect technology. Microelectron Reliability 2003;43:367–70. [3] Jenei S, Decoutere S, Maex K, Nauwelears B. Add-on Cu/ SiLKe module for high Q inductors. IEEE Electron Device Lett 2002;23(4):173–5. [4] Nguyen VH, Kranenburg HV, Woerlee PH. Copper for advanced interconnect. In: Proceedings of the 3rd International Workshop on Materials Science (IWOMS’99), Hanoi, November 2–4, 1999. [5] Ruelke H, Streck C, Hohage J, Ngo M, You L, Telford SW, et al. Manufacturing implementation of low k dielectrics for copper damascene technology. In: Advanced Semiconductor Manufacturing 2002 IEEE/SEMI Conference and Workshop, 2002. p. 356–361. [6] Xu G, Andideh E, Bielefeld J, Scherban T. Cohesive strength characterization of brittle low k films. In: Interconnect Technology Conference, 2002. Proceedings of the IEEE 2002 International, 3–5 June 2002. p. 57–59. [7] Lee PW, Lang C-I, Dian S, Xia L-Q, Gotuaco M, Yieh E. Multi-generation CVD low k films for 0.13 lm and beyond. In: Solid-state and Integrated-Circuit Technology, 6th International Conference, 2001;1:358–363. [8] Pang B, Yau W, Lee P, Naik M. A new CVD process for damascene low k applications. In: Semiconductor Fabtech. 10th ed. 1999. p. 285–289. [9] Stoney GG. Proc R Soc London Ser A 1909;82:172. [10] Nishimoto Y, Maeda K. Interlayer Insulating Film Forming Method. In: Semiconductor Device and Method of Manufacturing the Same, US Patent, US2001/0023125 A1. [11] Lau SH, Huang S, Koo A. Characterize low k and copper film in-situ. Semicond Int 7/1/2000 (www.e-insite.net/semiconductor/). [12] Pozar DM. Microwave Engineering [Chapter 5, Section 5.6] Addison-Wesley Publishing Company; 1993.
Integrating thick copper/Black Diamonde layer in CMOS interconnect process for RF passive components Guo Lihui, Zhang Yibin *, Su Yong Jie Jeffrey Semiconductor Process Technology Laboratory, Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, 117685 Singapore, Singapore Received 29 August 2003; received in revised form 1 December 2003
Abstract Thick copper (Cu)/Black Diamonde (BD) layer up to 4 lm has successfully been integrated in CMOS interconnect process to improve the quality of on-chip RF passive components. It is shown that BD film is easy to crack when its thickness is up to 4 lm. However, by inserting one or few layers of dielectric material, BloKe, the stress in the entire dielectric film stack can be reduced. Although the reduction of the tensile stress of the stack is insignificant, the inserted BloKe layer effectively prevents cracking from happening in the film stack. Spiral inductors have been integrated in developed Cu/BD (4 lm) top-metal-layer. Both Q value and resonate frequency of developed inductors are improved comparing to the inductors fabricated in previous top-metal-layer with 1 lm Cu/SiO2 stack. Ó 2003 Elsevier Ltd. All rights reserved.
1. Introduction Along with the development of CMOS technology the relevant interconnect process migrates from aluminum (Al)/SiO2 (USG) scheme for 0.18 lm technology node and before towards Copper (Cu)/low k or ultra low k scheme for 0.13 lm technology node and beyond. The reason is to reduce the RC delay and power dissipation caused by metal traces and dielectric layers that compose CMOS interconnect layers of chips. Black Diamonde (BD) is one of the candidates of low k dielectrics formed with CVD carbon doped silicon oxides (SiOC) for 0.13 lm technology node and beyond. It has a k value of about 2.8 and matches well thermally with copper. BloKe is a silicon carbide (SiC) type of material and has been proved a good copper diffusion barrier and etchstop layer for BD in integration process. Both BD and BloKe can be deposited by conventional PECVD methods using the same organo-silane precursor. Integration of Cu/BD damascene structure was demon-
*
Corresponding author. Tel.: +65-6770-5771; fax: +65-67731914/1714. E-mail address: [email protected] (Z. Yibin).
strated in Ref. [1], in which 25% reduction in intra-lead capacitance comparing with conventional oxide integration could be realized. On the other hand, one must consider the integration of RF passives, e.g. inductors, in interconnect top-metallayer as interconnect process and technology progressing forward. However, with upgrading of technology node, the thickness of interconnect layers is getting thinner, e.g. it is less than 0.4 lm for 0.13 lm technology node. The thinner metal layer is unfavorable to RF passive components since it will enhance the ohmic loss. In order to compensate such loss, an extra thick metal layer is introduced to thicken the top-metal-layer [2,3]. The extra thick metal layer can be formed with an additional process loop after accomplishing whole interconnect process; therefore, an additional cost will be counted for that. In order to improve the quality of passive components as well as to lower the fabrication cost, it is necessary to develop a process with which a thick topmetal-layer can be directly formed without additional thickening processes. However, this will introduce great challenges in process technology, such as thick film deposition, deep trench etch and metallization. Specially, very thick dielectric film may crack because of the film stress, which makes the process impossible.
0026-2714/$ - see front matter Ó 2003 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2003.12.006
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In this work, the top-metal-layer with 4 lm BD has been developed and integrated with conventional CMOS interconnect layers without additional top added process. In the development, the stress of thick BD has been studied, which is essential to achieve a thick layer without cracking. And, the characterization results of integrated inductors incorporated in 4 lm BD show much better RF performance than those fabricated using conventional interconnect technology.
2. Stress in thick BD film Unlike the Al/SiO2 scheme served for 0.18 lm technology node and before, the copper/low k scheme served for 0.13 lm technology node and beyond is formed by so called damascene technology [4]. In damascene process, copper traces are formed by several steps. Those are deposition of intermetal dielectric (IMD), trench etch of IMD, copper filled in trench area by electrical– chemical plating (ECP) method and chemical–mechanical polishing (CMP) of copper. Therefore, to achieve a thick BD layer as IMD is essential for achieving thick copper layer. However, it is found in our practice that the BD layer is much easy to crack than USG in integration process. It is caused by film stress. It has been known that USG film deposited on silicon with PECVD has compressive stress, therefore, is relatively not easy to crack. However, the BD film shows tensile stress [5], 4E þ 8 8E þ 8 dyne/cm2 on silicon, which makes it difficult to achieve a thick BD layer since it may induce a film crack. There are some research papers on properties of BD, but most of which deal with stress on the thermal expansion incorporating with copper to study the adhesion or Cu electromigration in damascene structure [6,7]. A few of published papers discusses the stress issue for achieving thick BD film. To research the relation between stress and film cracking of BD film, a set of samples was deposited with different thickness of BD films up to 6 lm on bare 8 in. silicon wafers. The deposition was carried out with applied materials Centura PECVD equipment using an organo-silane (Rn SiH4 n ), an oxidizer, as the precursors. The temperature of wafers during the deposition was around 350 °C. As depicted in Ref. [8], the formed film, BD, is a kind of low density silicon dioxide-like material, which is achieved by introducing network terminating species into Si–O matrix. Some of the film’s properties can be found in [7,8]. The deposition recipe has been optimized to achieve the stress of BD films on silicon as low as possible. The thickness of films could be measured using Therma Wave OptiProbe, which is a kind of commercial advanced ellipsometer. The stress measurement of the films was conducted using a commercial FSM 7800TC system, with which the stress was obtained based on the
measurement of the change in radius of curvature of the wafers. Stoney’s equation [9], rf ¼ Es ts2 =6ð1 ms Þtf R, was used and programmed in the machine to calculate the residual stress in deposited films. Where Es and ms were Young’s modulus and Poisson’s ratio of silicon wafer, respectively, ts and tf represented the thickness of the silicon wafer and deposited film, respectively, and R was the measured radius of curvature. The tested residual stress with film’s thickness is shown in Fig. 1. It is found, with the observation under a microscope, that the films are easy to crack when the thickness is over 4 lm. The thicker the film is, the more severe the crack will be as the thickness larger than 4 lm. That is because of the larger tensile stress in thick film than in thin one. The result is consistent with the report from the Ref. [5], in which the recommended film thickness should be less than 3 lm in practice. Combining the results of stress testing and the crack observation, it is found that the BD film will crack after a critical value of tensile stress that is around 35 MPa. It is obvious to achieve a BD film with 4 lm or thicker thickness needs to find a way to reduce the residual stress in the film. Normally, there are two possible ways to change the stress of film. One is to re-construct the film through a high temperature anneal, which is limited by the enduring temperature of interconnect process. Another method is to use a film with compressive stress to compensate the tensile stress of bulk BD film, which is described by Ref. [10]. The reference shows that dielectric film with tensile stress and dielectric film with compressive stress are alternately deposited on a substrate to form a stress-adjusted stack film, which can reduce the bowing of wafer and crack of the film. Because BloKe presents a high compressive stress on silicon and has been used as an etch-stop layer in CMOS Cu/BD multi-level interconnection [5], therefore, BloKe has been chosen and inserted in thick BD layer to reduce the tensile stress of BD in this study. However, the thickness of compensated BD in conventional inter-
Fig. 1. Residual stress as a function of film thickness for BD on silicon.
G. Lihui et al. / Microelectronics Reliability 44 (2004) 581–585
connection is about 0.5 lm and, it will be over 2 lm in this study. The stress compensating effectiveness of BloKe needs to be researched for thick BD layer. The BloKe is deposited in the same PECVD machine as BD under temperature about 350 °C. The inserted BloKe in thickness. Fig. 2 shows the stress layers are 500 A change with the growth of stack film. And, the stress of relevant BD thickness without BloKe insertion is also given in Fig. 2 as a comparison. The final stack’s stress may be explained by the introduced force originated from the mismatching at the interfaces of silicon/BD, silicon/BloKe and BD/BloKe. It can be found that the residual stress in 2 lm BD film drops about 6 MPa when a thin BloKe is deposited on it. That is because the compressive stress of BloKe to silicon partially compensates the tensile stress of BD to silicon. However, the residual tensile stress returns back to a higher level as the second 2 lm BD film is subsequently deposited on the stack. Comparing with 4 lm BD without insertion of BloKe, the stress reduction of 4 lm BD with the insertion is not large, only about 2 MPa. It may be be is too thin to cause that the inserted BloKe, 500 A, balance the tensile stress introduced by 4 lm BD film. When the second BloKe covers on the existing stack, there is no pulling back of the stress. It may be interpreted as the distance between the silicon and the second BloKe is large, therefore, the compensative impact of BloKe to final tensile stress of BD film will be weak. Moreover, the stress of whole stack has a little increment in tensile because BD should show a tensile stress to BloKe too. As the third layer of 2 lm BD is added on the second BloKe, the residual stress goes up further. However, the final residual stress of the stack is still less than that of 6 lm BD without insertion, even the reduction is not large. Since the residual stress is still very high, such stack film with 6 lm BD is easy to crack in the process as we observed. As it is well known that the chip will be alloyed at the final process stage, therefore, the thermal stress evolution of the film was conducted. The sample wafers were heated up to 350 °C and cooled down to room tem-
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Fig. 3. Residual thermal stress of stacks after alloying (–d–) BLoK). and before alloying (M). ( 2 lm BD, 500 A
perature. The stress was measured in situ. It was found that both BD and BloKe appeared large compressive stress at this high temperature. 700 MPa compressive stress was observed for a 1 lm BD layer on silicon and, BloKe layer on silicon, respectively. 16 GPa for a 500 A A similar result was also obtained in previous study [11]. The large compressive stress of BD and BloKe at high temperature means that both films have high coefficient of thermal expansion (CTE) compared to silicon. When the films cooled down to room temperature, for a BD without BloKe insertion, the stress turned back to tensile and the value was larger than that before alloying. That might be caused by the deformation of film. For stack film, the residual tensile stress was different with that in a single layer of BD on silicon, as shown in Fig. 3. The stress values before alloying are also predicated in the figure in isolated dots. It is not difficult to find that the coverage of BloKe on BD can remit a little in residual thermal stress. It may be interpreted as the CTE of BloKe is larger than BD and silicon and, the residual stress of BloKe after a thermal cycle may tend to be more compressive than that before alloying. However, such influence is still limited by the volume fraction of BloKe in the stack. As the result of stress study, 4 lm BD with a suitable BloKe insertion was chosen as the top IMD for topmetal-layer in interconnect integration. No cracking was found in such BD/BloKe stack film. 3. Integration of passive component and results
Fig. 2. Residual stress of film stacks of BD with insertion BLoK), and corBLoK (–d–, 2 lm BD, 500 A responding thickness of BD without insertion on BLoK (M).
The structure of integration is shown in Fig. 4. The top-metal-layer was designed in metal-4 layer. The fabrication was carried out on an 8 in. CMOS interconnect line in the Institute of Microelectronics (IME), Singapore. After three metal layers and the via-3 had been completed, 4 lm BD with a BloKe insertion was deposited on the top of via-3 layer. Then, the metal-4 layer was processed with damascene consequent process loop, which included the trench etch of BD/BloKe stack layer, barrier/seed layer deposition, copper filling
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G. Lihui et al. / Microelectronics Reliability 44 (2004) 581–585
Fig. 4. Structure of integrated inductor in metal-4 layer with 4 lm BD IMD ( Cu, USG, BD).
using electro–chemical plating (ECP) and chemical– mechanical polishing (CMP). Finally, a passivation layer, silicon nitride, was covered on chip. Spiral inductors were integrated in the metal-4 layer (4 lm thickness) and metal-3 layer (0.5 lm thickness). The coil traces of inductors in two layers were connected through via-3 layer as shown in Fig. 4. The underpass of inductors was in metal-2 layer. The RF testing of spiral inductors with two ports was conducted with HP 8510C network analyzer. Effective inductance, Leff , and Q value of inductors were deduced from the measured S parameters in a conventional procedure as following:
Fig. 5. Comparison of two 5-turn inductors with 4 lm/BD (d) and 1 lm/USG (M), respectively.
(1) After de-embedding procedure, y11 was extracted from two times measured S parameters [12]; and (2) Leff and Q were achieved with the formulae, Leff ¼
imageð1=y11 Þ 2pf
Q¼
imageð1=y11 Þ realð1=y11 Þ
As a comparison, Fig. 5 shows the inductance and Q value of two 5-turn inductors with 4 lm BD and 1 lm USG as metal-4 layer, respectively. The metal-4 layer with 1 lm USG is fabricated by a baseline CMOS interconnect process developed in IME. Since the structures under the metal-4 layer are same for both two inductors, with 4 lm BD and 1 lm USG, the difference of Q value of two inductors should be induced by the evolution of top metal-4 layer. It can be found that the Q value of inductor with 4 lm BD metal-4 layer increases nearly 50% comparing with that with 1 lm USG metal-4 layer at frequency 2–3 GHz, where most important RF applications are applied. This improvement mainly comes from the thick metal-4 layer, with which ohmic loss in inductor’s coils can be reduced. And, it also benefits from the usage of BD as IMD instead of USG. The dielectric constant of BD is about 2.8, which is lower
Fig. 6. Comparison of the maximum Q value (Qmax ) and the resonate frequency (Fres ) between inductors with 4 lm/BD (d) and 1 lm/USG (M).
G. Lihui et al. / Microelectronics Reliability 44 (2004) 581–585
than that of USG, about 4.0. It leads to a reduction of parasitic capacitance between inductor’s coils and, therefore, an enhancement of Q value. The reduction of the parasitic capacitance can be proved by the curve of effective inductance, Leff; in Fig. 5. The curve of Leff , corresponding to the inductor with 4 lm BD, moves to right, which means the resonant frequency increases because of the reduce of the parasitic capacitance. Besides the inductor with 5-turn coil, other inductors from 1- to 8-turn coil show a jump of Q value when metal-4 is changed from conventional 1 lm USG to 4 lm BD. Fig. 6 depicts the comparisons of resonate frequency and maximum Q value between two sets of inductors, which are fabricated with two different metal-4 schemes. When the turn of inductors is equal or less than 3, the resonate frequency will be larger than 20 GHz.
4. Conclusion The stress of thick Black Diamonde (BD) on silicon has been studied. The threshold value of residual stress for BD film cracking is about 35 MPa in tensile. BloKe shows a compressive stress on silicon, which can be used to compensate the tensile stress in BD. Insertion of BloKe layer(s) in thick BD can remit the residual stress. But the impact on the final stack’s stress is not large if the thickness of BloKe is small and is far from the silicon. However, the insertion can effectively prevent cracking to develop in the film stack. Adding a BloKe capping layer on BD can be used to reduce the thermal residual stress in BD to some extent also. Inductors have been incorporated in metal-4 layer with 4 lm BD as IMD. Comparing with conventional 1 lm USG metal-4 layer, new developed 4 lm BD metal-4 layer can provide inductors high Q value and good resonate frequency. The improvement in Q value comes mainly from the reduction of ohmic loss because of the thickness increment of metal-4 copper layer.
Acknowledgements The authors would like to thank Mr. The Choong Long and Ms. Zhu Hong for their help in stress test, and
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engineers in Semiconductor Process Technology Laboratory of IME who provided supports in preparation of samples.
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