RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications

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LETTER

RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications Marzieh Beheshti Asl, Mohammad Hossein Zarifi ∗ Department of Electrical Engineering, East Azerbaijan Science and Research Branch, Islamic Azad University, Tabriz, Iran

a r t i c l e

i n f o

Article history: Received 17 April 2014 Accepted 24 June 2014 Keywords: Complementary metal oxide semiconductor (CMOS) Power harvesting Power micro-converter Radio frequency (RF) Multistage rectifier

a b s t r a c t In this paper a radio frequency (RF) to direct current (DC) voltage converter with multi-stage rectifiers is reported for micro power conversion in RF power harvesting systems. The purpose of this paper is to select an appropriate structure for the micro power-converters, operating in high frequencies. The main idea is to convert RF range sinusoidal signals to a DC voltage to produce power for the rest of the electrical circuit or a system. The reported rectifier demonstrated an efficiency of 10% at large span of frequency for input signal of 350 mV. In the presented work, an analytical and numerical study of the micro powerconverters is reported for various applications. Different design parameters have been investigated for an efficient structure design including, number of MOSs, DC current of a known load, size of MOSFETs capacitors, and frequency of the operation. Consequently, optimized parameters have been reported in order to improve the RF to DC conversion efficiency. Reported circuits were designed and simulated in 180 nm twin-well CMOS process with low threshold metal-oxide semiconductor field-effect transistors (MOSFETS); this multistage rectifier occupied an area of 0.23 mm × 0.146 mm and it produced an output voltage of 2 V at its output. This output voltage can provide the supply voltage required to operate the RFID processing circuitry. Post layout simulations demonstrated that for thirteen stages of the rectifiers, the efficiency of 10% for a capacitive load of 10 pF has been achieved. © 2014 Elsevier GmbH. All rights reserved.

1. Introduction Micro power harvesting systems have been used for collecting energy from environment and converting that energy into DC voltage. These systems can power up many devices with efficient amount of battery usage. Lifetime and charging of the battery are two main issues in micro systems [1,2]. Power harvesting circuits provides adequate amount of power for the electronic section of a microsystems. Many sources are available in environment and can be used to extract the energy. RF signals and sources are playing critical roles for this purpose since they are all available in the medium in modern life [3]. An appropriate approach to replace power supply is utilizing power harvesters. Though they are promising alternatives for batteries, but they are suffering from complexity and expensiveness as a power supply [4–6]. There are many different energy sources such as mechanical vibration, heat fluctuation, and optical sources which can be used for power extraction and generation [7–11], but RF power

∗ Corresponding author. E-mail address: mohammad.h.zarifi@gmail.com (M.H. Zarifi).

harvesting systems have the advantage of providing power as well as enabling the simultaneous wireless communication opportunity to many RF devices. Devices built with this unique technology can be sealed, embedded within structures, or made mobile, thus eliminating additional service form a battery [12,13]. A RF to DC converter consists of different blocks and the main and the most important one is the rectifier and doubler block. Typically, several different approaches are used for generating a DC power for valid device operation. This paper presents a new architecture for RF-to-DC power conversion which it harvests RF power and produces DC power. A key subcomponent in RF-power harvester is the RF to DC converter. The RF to DC converter consists of different blocks where the main and the most important one is a rectifier and a doubler block. An efficient converter can produces high output voltages at low input power level; its performance is significantly determined by the threshold voltage requirement of the transistors, performing the conversion. Different methods and techniques have been introduced to increase the efficiency of the RF to DC converter block such as using Schottky diodes, External voltage compensators, passive threshold voltage reduction, and utilizing floating gate transistors [14–17]. Each of these techniques has advantage of increasing the efficiency of the power conversion in cost of increasing the complexity and fabrication cost of the system.

http://dx.doi.org/10.1016/j.aeue.2014.06.008 1434-8411/© 2014 Elsevier GmbH. All rights reserved.

Please cite this article in press as: Beheshti Asl M, Zarifi MH. RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.06.008

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In the doubler structure, AC to DC conversion was governed by the following equation (1): Vodc = ((Vin –Vds ) · n) −

Fig. 1. A doubler schematic for the multi-stage rectifier.

The input signal level for UHF–RFID communication system is only a few hundred millivolts at minimum sensitivity, in several meters of communication distance. Therefore single stage halfwave or full-wave diode rectifiers which typically are used in HF or very short range UHF applications cannot produce a sufficient DC voltage level to supply the integrated circuit part. This raises the requirement of multi-stage rectifier design and implementation. This paper presents a new architecture for RF-to-DC power conversion which it harvests RF power and produces DC power. This paper is organized as follows. The structure of a doubler circuit is depicted in Section 2. Section 3 illustrates the proposed RF to DC micro converter. Simulation and post-layout simulation results are furnished in Section 4. Finally, the conclusion is drawn in Section 5. 2. Structure of a doubler circuit In multistage rectifier structures, doubler plays an important and a key role since it highly involves in the output DC voltage creation. This composite circuit is built from MOSFETs and capacitors. Typically NMOSs transistors are preferred since they have higher electron mobility, smaller in size which leads to less parasitic capacitors and higher speed than PMOS counterparts. PMOS transistors provide low output DC voltages in comparison with structures utilizing NMOSs transistors. Therefore NMOS transistors were used to implement the rectifier circuit. A doubler circuit schematic is shown in Fig. 1. Two transistors with diode connection structure with output current and capacitive load. A diode connected MOS element represents a square law relationship between the device voltage and the current. Fig. 2 shows the IV curve of the transistors and presents its variation with gate-source voltage. For a diode connected transistor, the transistor will be in saturation or active region.

ILOAD V th · n Ccop · f

(1)

where Vin was the AC input voltage which its value varied from 0 to maximum input voltage amplitude, capacitor (Ccop), that was set at the input of circuit and was the coupling capacitor which was connected between voltage source and the first MOSFET in doubler input, Vodc is the DC output voltage which delivers the electrical power to other parts. Vth is the threshold voltage of the MOSFETs frequency, f, is the carrier signal frequency which is around 900 MHz, ILOAD is the amount of load current drawn by the output load, and n is the number of MOSFETs utilized in doubler structure. Based on Eq. (1), increasing the number of the stages would increase the output voltage amplitude; transistors with low threshold voltage would lead to high DC voltage as well. As a disadvantage increasing the number of stages increases the parasitic capacitors. The effect of increment in value of the parasitic capacitors could be included in increasing of the load current which reduced the output voltage and the conversion efficiency of the system. Drain source voltage depends on the threshold voltage; drain current as well as transistors’ sizes, Eq. (2) demonstrates the relation between these parameters under condition of negligible transistor channel modulation:



VDS =

2.ID.L + V th W.n.COX



  Vodc =

Vin −



˛ · ILOAD ·



−V th ·

(2)

L + V th Wn.COX

ILOAD .n Ccop.f

 ·n

(3)

Employing Eq. (2) in (1) leads to Eq. (3) which demonstrates the relation between transistors parameters and number of stages with output voltage of harvesting circuit, where ˛ is a coefficient ratio between ID and ILOAD . 3. Proposed RF to DC converter circuit To meet the requirements of a harvesting system, a multistage rectifier was designed to obtain a micropower with rectifiers and doublers with high energy efficiency. As mentioned in the previous section, large number of the voltage doubler can create higher output voltage, but will result in lower efficiency. In the proposed circuit, the power converter is composed of multistage rectifier which doubler is the basic block of that. The multistage structure was used to generate a voltage higher than 1 V at the frequency close to 900 MHz. Thirteen number of NMOS transistors have been used to implement the proposed rectifier. Fig. 3 demonstrates the rectifier circuit, an impedance of 50 ohms was considered as the output impedance of the previous stage (such as antenna). 4. Results and discussion

Fig. 2. Current of diode connected, ID according to voltage, VDS .

The proposed circuit was designed and simulated in Hspice, in 180 nm technology. Cadence was utilized to draw the layout of the circuit. Simulation results reported in this section are the post layout results for all simulations. This scheme has advantage of gaining a high output voltage with low level ripple. Results of simulation with optimization parameters are showed in Fig. 4. According to the time domain simulation results in output voltage of 2 V was

Please cite this article in press as: Beheshti Asl M, Zarifi MH. RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.06.008

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Fig. 3. Schematic of the multistage in the RF to DC converter.

obtained in a transition of approximately 38 ␮s. As a consequence of low bias current, slow response and high propagation delay in the output current simulation was observed (Fig. 5). Load capacitance of the converter (CLOAD ) plays an important role in determining the delay time of the circuit when the output reaches to its stable state. To have a circuit, efficiently designed, few parameters were investigated such as, number of the transistors, size of the transistors (width and length), process corners variation and load value variation. Fig. 6 shows the output voltage variation, vs. number of the transistors. According to the simulation increasing the number of transistors results in decreasing the output DC voltage. Variation in transistors width was studied in Fig. 7 and it illustrates for large values of the W, the circuit produces less voltage than 2 V which was achieved for moderate widths. Output current variation of the converter was another important factor. To perform this simulation, output resistor of 1 M was placed and swept from 100 k to 8 M. The results for this simulation demonstrated the increment in the load resistance increased the output voltage, which was the consequence of reduction in load current, drawn by the processing circuitry following this stage. Since the designed circuit was aiming the load resistance of 1 M,

Fig. 4. Time domain simulation results for output voltage.

Fig. 5. Time domain simulation results for output current.

Fig. 6. Simulation of the output voltage vs. number of the transistor.

Please cite this article in press as: Beheshti Asl M, Zarifi MH. RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.06.008

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Fig. 10. Simulation of output voltage against fabrication process corners.

Fig. 7. Simulation of the output voltage vs. transistors width.

Fig. 8. Simulation of output voltage vs. load.

therefore in original simulation RLOAD equal to 1 M was used. The simulation results for load resistance variation are presented in Fig. 8. Simulation of transistors’ length variation is presented in Fig. 9. Increasing the length of the transistors was result in output voltage reduction. This simulation showed high output voltage was obtained while the length of 180 nm was used. In a general conclusion, increasing the size of the transistors led to high parasitic

Table 1 Output voltage in different process corners. Output voltage

N/PMOS corner

1.35 V 1.5 V 2V 2.5 V 2.75 V

SS SF TT FS FF

capacitor which results in reduction at output voltage amplitude as a consequence. In CMOS fabrication, transistors characteristics are changing from one corner of the processed wafer to the other. Those variations in characteristics of transistors should be studied in circuit implementation. Simulation results for five different process corners are shown in Fig. 10. Table 1 summarizes the results of the process corner variation. A variation from 2.75 V in FF corner to 1.35 V in SS was observed. But in the worth case scenario the output voltage is better than 1.2 V, which is necessary to power up a CMOS circuit in emerging nanoscale technologies. Few adaptive techniques are available to reduce the effect of process variation in CMOS circuits. They can make the circuit robust against these variations but at the same time increase the complexity and add additional power dissipation or need external power sources which is not recommended for low-power small size power harvester and converter circuits. Table 2 presents the optimum values for the different parameters and their values in the designed circuit. Efficiency factor is the most important factor to compare the operation of the different rectifiers. To calculate that parameter, Eq. (4) was employed, with the following parameters: Pin = 0.4 ␮W, Vout = 2 V, Iout = 2 A



(1/T ) Vout ∗ Iout dt Pout DC power  ´ = = = Pin RF power (1/T ) Vin ∗ Iin dt

(4)

According to Eq. (4), an efficiency of about 10% was obtained. Layout of the purposed circuit is shown in Fig. 11. This circuit occupies an area of 230 ␮m × 146 ␮m. Table 2 Summary of optimal parameters achieved according to simulations.

Fig. 9. Simulation of output voltage vs. channel length.

Value

Parameters

Value

Parameters

900 MHz Pf 20 Pf 1 2V

Frequency CLOAD CCOP Vout

350 mv 50 2 ␮A M1

Vin Rin ILOAD RLOAD

Please cite this article in press as: Beheshti Asl M, Zarifi MH. RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.06.008

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[2]

[3]

[4]

[5]

[6] [7] [8] [9] [10]

Fig. 11. Layout of the proposed circuit drawn in cadence.

[11]

5. Conclusion

[12]

In this paper a RF to DC converter was presented for RF power harvesting applications with high efficiency. The proposed method employed multistage rectifier structure for DC voltage creation. Thirteen rectifier stages were used to generate a positive DC voltage. Output voltage variation was investigated for different parameters alteration, such as transistors’ channel length and width, load resistance, number of transistors, and process variation. The extracted results were compared and optimized to achieve an efficient circuit. The designed structure provided output voltage of 2 V from input voltage of 350 mv at 900 MHz.

[13]

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[14]

[15]

[16]

[17]

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Please cite this article in press as: Beheshti Asl M, Zarifi MH. RF to DC micro-converter in standard CMOS process for on-chip power harvesting applications. Int J Electron Commun (AEÜ) (2014), http://dx.doi.org/10.1016/j.aeue.2014.06.008