Reliability aspects of copper metallization and interconnect technology for power devices

MR-12142; No of Pages 10 Microelectronics Reliability xxx (2016) xxx–xxx

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Reliability aspects of copper metallization and interconnect technology for power devices Frank Hille a,⁎, Roman Roth b, Carsten Schäffer b, Holger Schulze b, Nicolas Heuck c, Daniel Bolowski c, Karsten Guth c, Alexander Ciliox c, Karina Rott a, Frank Umbach a, Martin Kerber a,1 a b c

Infineon Technologies AG, Am Campeon 1-12, D-85579 Neubiberg, Germany Infineon Technologies Austria AG, Siemensstr. 2, A-9500 Villach, Austria Infineon Technologies AG, Max-Planck-Str. 5, D-59581 Warstein, Germany

a r t i c l e

i n f o

Article history: Received 11 July 2016 Accepted 12 July 2016 Available online xxxx Keywords: IGBT Robustness validation Temperature stability Copper-silicide Diffusion barrier Wire bonding Die attach

a b s t r a c t The introduction of thick copper metallization and topside interconnects as well as a superior die attach technology is improving the performance and reliability of IGBT power transistor technologies significantly. The much higher specific heat capacity and higher thermal conductivity increases the short circuit capability of IGBTs, which is especially important for inverters for drives applications. This opens the potential to further optimize the electrical performance of IGBTs for higher energy efficiency. The change in metallization requires the introduction of a reliable barrier against copper diffusion and copper silicide formation. This requires the development of an efficient test method and reliability assessment according to a robustness validation approach. In addition, the new metallization enables interconnects with copper bond wires, which yield, together with an improved die attach technology, a major improvement in the power cycling capability. © 2016 Elsevier Ltd. All rights reserved.

1. Introduction The introduction of .XT technology [1] in silicon based insulated gate bipolar transistors (IGBTs) together with suitable free wheeling diodes (FWDs) is boosting the potential for higher energy efficiency and reliability of power modules. This technology comprises a copper front side metallization on a tungsten-based diffusion barrier introduced in the IGBT and the diode (cf. Fig. 1), copper wedge bonding as front side interconnect, and an advanced die attach by silver sintering. Higher energy efficiency of new inverter generations by increasing the power density is the key driver for technology development, being enabled mainly by two measures: First, by the reduction of power losses in the IGBT and the diode and therefore directly increasing the usable output power for a fixed maximum junction temperature. And second, by the increase of maximum junction temperature itself, allowing for even higher power losses and therefore also output power at identical cooling conditions. Both measures can be combined. They require however significant improvement in short circuit capability of the IGBTs as well as the reliability of interconnects. Part I of this work reviews how an improved thermal setup by employing a new die attach technology as well as a copper metallization ⁎ Corresponding author. E-mail address: frank.hille@infineon.com (F. Hille). 1 Present address: Dr. Martin Kerber, Schnann 65, A-6574 Pettneu am Arlberg.

serving as heat sink does improve the thermal short circuit capability significantly. This opens the potential for further electrical device optimization. Part II of this work focuses on the implementation of the copper metallization as well as the reliability aspects arising from it. The dynamics of copper silicide formation and the consequence for device operation are investigated. As a result, a highly reliable separation of copper from silicon by a diffusion barrier is required, since otherwise device destruction occurs. The failure mechanisms, the methodology for testing and the methodology for reliability assessment according to a robustness validation approach are discussed. Thick copper metallization enables the replacement of aluminum wedge bonds by much harder copper wedge bonds. Together with the improved die attach technology, the overall interconnect reliability with respect to power cycling is tremendously improved. Results for various module setups and explanations for the failure modes are discussed in part III. 2. Improvement of short circuit ruggedness Short circuit ruggedness is a requirement for many electrical drives. Due to a failure in operation – especially during commissioning or maintenance work – a shorting of the inductive load driven by the inverter can happen. As a consequence the output terminals of the IGBT are more or less directly connected to the DC link bus with high voltage.

http://dx.doi.org/10.1016/j.microrel.2016.07.119 0026-2714/© 2016 Elsevier Ltd. All rights reserved.

Please cite this article as: F. Hille, et al., Reliability aspects of copper metallization and interconnect technology for power devices, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.07.119

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Fig. 1. Schematic cross section of a) IGBT and b) FWD with .XT power copper metallization (picture from [6]).

The missing inductive load can no longer limit the current increase with time once the IGBT is turned on. Therefore, the IGBT has to limit its current under short circuit operation itself. Furthermore, the IGBT should be able to withstand this operation for a few to ten microseconds until this faulty operation mode is detected by the control circuit and to safely turn off afterwards. Short circuit operation means a considerable stress in terms of high currents and dissipated energy, hence a number of short destruction mechanisms are reported. An up to date review is found in [2]. In the present case, the thermal short circuit destruction mechanism is the relevant one [3,4]. In this destruction mode, the IGBT is able to withstand the short circuit operation and even safely turns off the load current after the gate is turned off. However, the device is destructed some hundreds of microseconds up to milliseconds after the short circuit pulse. A study including electro-thermal device simulation (cf. Fig. 2), taking into account the electrical and thermal setup, explains the failure mechanism and how an improved thermal setup can help [5]. The predictions for the improvements have been experimentally validated within this study for a 1200 V IGBT technology. During the short circuit pulse of only a few microseconds, heat dissipation takes place mainly in the drift region of the transistor. The temperature distribution is basically confined to the silicon volume of the chip, with a maximum temperature in the middle of the drift region. The front side MOS structure with its n-source and also the back side p-emitter are still close to the starting temperature before the short circuit pulse. The short circuit pulse is too short for considerable heat transport. After the short circuit pulse heat diffusion takes place into the region of n-source at the front side and p-emitter at the back side. As temperature increases at these junctions, thermally induced leakage currents

Fig. 2. Electro-thermal device model. Left picture: the collector emitter current (log scale) initially increases after the short circuit pulse and leads to device destruction if a critical energy is exceeded. Right picture: IGBT cell and mounting setup (picture from [5]).

occur: electron current from the n-source, hole current from the p-emitter. Electron and hole current are coupled to each other by pnp-amplification in case of an IGBT. Suppressing the temperature rise at one of the junctions helps to lower the self-heating after the short circuit pulse and delays thermal runaway. For the front side, the thin aluminum metallization is replaced by thick copper metallization, which needs to have considerable amount of the heat capacity of the silicon volume to act as temporary heat sink. Introducing this measure alone increases the critical short circuit energy by 20%–25% (cf. Fig. 3). For the back side, the heat transport out of the silicon into the copper coating of the ceramic substrate is limited by the low thermal conductivity of the soft solder die attach. Just by replacing it by a layer of much higher heat conductivity, as Ag sintering or diffusion soldering, the critical energy can also be increased by 20%–25%. The highest improvement is obtained if both measures, a thick copper metallization and a novel die attach, are employed simultaneously. Both junctions are kept as cool as possible, avoiding that a thermally induced electron/hole current from one side is leading to an increase of the respective hole/electron current from the other side by pnp-amplification, which is compromising the effectiveness of the single sided measures. As a consequence, the increase of 85% in critical short circuit energy well exceeds the sum of improvements of the single sided measures (cf. Fig. 3). Levers for increasing the power density can then be employed, all requiring an increase in short circuit ruggedness. First, the MOS cells may be designed for higher electron currents, leading to a better plasma distribution suitable for switching with lower electrical losses but increasing the short circuit current. Second, the drift region, which needs to be flooded with excess carriers and is therefore determining the electrical losses to a wide extent, may be reduced in thickness. This however simultaneously reduces the heat capacity of the silicon volume. Third, the maximum junction temperature may rise. This usually means a reduction of short circuit capability since the condition at which selfheating exceeds the cooling capability is reached sooner. 2.1. Novel copper metallization and its reliabilty aspects Copper is a very suitable heat sink for improved short circuit ruggedness due to its high thermal capacitance and conductivity. For the required copper thickness, electrochemical deposition is a very capable method. A wafer-metallization process benefits from the cost-efficient, stable and precise methods of a wafer fabrication at a very low defect density level. It is crucial that the thick metallization covers all cells of the IGBT or the complete anode area of the diode. The wafer metallization process enables a perfect alignment of the metallization on the chip, and provides a high degree of freedom concerning the layout of the metallization. The process is even suitable to fabricate the IGBTs

Fig. 3. Improvement potential of critical short circuit energy on a relative scale. The aluminum front side is represented as 0 μm copper. Error bars for the simulation results are caused by the discretization of gate voltages (picture from [5]).

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gate pads and the metal fieldplate structures of the edge termination with the same process steps. More details about the manufacturing process have been published in [6]. The copper metallization surface forms a robust and reliable interface to the copper wedge bond. The copper and tungsten metal stack is stable enough to withstand the extreme forces of the copper wedge bonding process and power cycling of the copper bond wire, which is much more rigid than an aluminum bond wire. Here, not only the mechanical properties of the metals are important, the interfaces between the metallization layers and to the silicon and oxide surface of the wafer have to be optimized for best adhesion [7,8]. Fig. 4 shows a cross section of a bond foot on an IGBT to illustrate the amount of deformation of the initially circular copper bond wire during the wedge bonding. 2.2. Copper-silicon reaction The direct reaction of copper with silicon leads to the formation of copper silicide. Interdiffusion and reaction have been studied and reported in previous works [9,10] showing that Cu3Si is the dominant phase and that Cu is the dominant diffusion species. In the temperature range of 200–260 °C the silicide growth follows a square root time dependency with an activation energy of 0.95 eV [9]. Investigations on the reaction kinetics at temperatures below 200 °C are not yet reported. In order to study the Cu3Si formation in this temperature range IGBT wafers were processed with Cu metallization without using a barrier layer. In order to avoid unwanted Cu3Si formation during processing the process temperature was kept low during Cu deposition (Cu seed layer sputtering) and wafer post processing. Subsequently the wafers were separated into pieces and the resulting samples were annealed in an oven step in air atmosphere. The thickness of the reacted Cu3Si zone was measured by cross section SEM analysis as depicted exemplarily in Fig. 5a. In the temperature range of 150 °C to 200 °C and for Cu3Si thicknesses below 600 nm a linear growth behavior could be observed (cf. Fig. 6). The growth velocity is following an Arrhenius model with an activation energy of 1.5 eV as depicted in the inset of Fig. 6. Above 600 nm Cu3Si thickness a change to slower growth rate and parabolic behavior was visible. Above 1200 nm a saturation tendency was found for T b 230 °C which could be caused by the local compressive stress in a contact hole due to the volume expansion of Cu3Si. Further strong growth of Cu 3Si (N2 μm) was typically present at temperatures ≥ 400 °C in combination with stress induced cracks in the BPSG layer as shown in Fig. 5b. To summarize, the experiments show a distinct reaction of Cu with Si and Cu3 Si growth in a contact even at temperatures far below 200 °C. As a consequence one cannot exclude further Cu3Si growth and severe damaging of the device during operation at typical junction temperatures between 75 °C and 150 °C.

Fig. 4. FIB image of a cross section of a bond foot on an IGBT pad metallization.

Fig. 5. SEM cross section of Cu3Si formation in a contact (Cu on Si without barrier layer, remaining Cu film was removed by mechanical take-off).

2.3. Reliability aspects In case of IGBTs and FWDs, the contact area, where the copper is separated from the chip silicon only by a thin barrier, is much larger than in other technologies with copper chip metallization. The unstructured anode contact of a FWD can have an area of N 1 cm2 per chip. Fabrication of barriers of this area is only possible in advanced cleanroom environment. Even then, there is a probability that a particle can disturb the barrier deposition process. Therefore, a defect-tolerant barrier design and a well-engineered screening concept are essential. In case of a barrier failure, the copper locally reacts with silicon, forming a Cu3Si particle at the interface. This particle is growing under strong volume expansion, causing a local destruction of the p/n junction of the device.

Fig. 6. Cu3Si thickness in a contact in dependence of annealing time and temperature. The inset is showing the Arrhenius plot of the Cu3Si growth velocity.

Please cite this article as: F. Hille, et al., Reliability aspects of copper metallization and interconnect technology for power devices, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.07.119

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Fig. 7. SEM pictures of Cu3Si fails after thermal treatment due to barrier defects, a) IGBT with Cu3Si formation in contact hole, b) diode fail with Cu3Si formation in anode (picture from [6]).

Fig. 7a shows the cross section of a Cu3Si particle, caused by a barrier defect in the contact hole of a trench IGBT. The columnar growth of the particle is caused by the confinement of the trench gate cell of the IGBT. Here, the top of the particle has already grown over the copper surface and the bottom has reached the position of the p/n junction. The MOS structure in the cell has been destroyed by mechanical stress. In the case of a FWD's unstructured Cu-barrier-Si interface, the Cu3Si particle is more lens-shaped (cf. Fig. 7b). Here, the copper and the barrier have been wet-chemically removed to make the localization of the defect easier. The Cu3Si particle has already penetrated the diodes p/n junction. As soon as it reaches close to the devices p/n junction or MOS structures, the Cu3Si particle causes a strong local leakage current. Since the reaction of copper and silicon to Cu3Si can be observed already at device operation temperatures, a Cu3Si particle might grow during operation of the device and cause a spontaneous increase of the leakage current, which can even lead to a fail device during operation. Therefore, the barrier quality has to be evaluated carefully.

ambient. Before, in between, and after these anneals electrical readouts have been done by measuring the leakage current of the devices. In case of a barrier failure and subsequent destruction of the IGBT cell or diode's p/n junction, this was detected by an increasing leakage current. To confirm the failure mechanism, the failure has been located by IR-lock-in-thermography and emission microscopy and a FIB cross section of the damaged barrier was made. Such kind of stress test is usually performed in a module or a discrete package. Additionally to package-level tests, the stress tests and readouts described in this paper were performed on wafer level, which has a lot of advantages. The wafer level tests allow accelerating the barrier development and evaluation process vastly in terms of speed and quantity. As much as possible, standard wafer fabrication equipment was used: A horizontal furnace for the thermal stress and an automated wafer prober for readout. Benefitting from efficient methods of the wafer fabrication, a lot more process variants have been evaluated in the initial phase of barrier development than it would have been possible if packaged chips were tested in a conventional laboratory environment. Without the sample built, a much faster feedback time was achieved. In each stress sequence, up to 100 wafers with approximately 250 IGBTs or 350 FWDs on each wafer were tested, providing a large amount of test data for statistical analysis. The wafer-level tests facilitate a correlation of the barrier reliability to process properties, e.g. to see the impact of process variations on a wafer or from wafer to wafer. Furthermore, a correlation of the barrier fails to defect locations, obtained from defect measurements performed at all critical process steps during wafer fabrication, is much easier. This has especially enabled a process optimization with respect to defect density. With subsequent improvement of barrier quality in later development stages, the focus of development shifted from defect density optimization to intrinsic end-of-life assessment. The barrier quality had become so high that the stress durations became too long for employing furnaces of wafer fabrication. Instead, dedicated furnaces in our reliability lab had to be used, limiting however the number of simultaneously stressed wafers to a number of ten, which is sufficient to address questions with respect to intrinsic barrier quality. Without the temperature limitations of the package, the chips can be stressed on wafer-level tests at higher temperatures, enabling to reach the barrier's end of life in a manageable time. For this purpose, the IGBTs and diodes have been adapted to avoid temperature degradable components of the device other than the diffusion barrier. 2.5. Intrinsic barrier lifetime determination The mechanism of the device failure is thought to happen in two subsequent steps: 1. Initial copper diffusion through the barrier mainly along grain boundaries of the barrier. Simultaneous or subsequent degradation of the barrier to such an extent that a massive reaction of copper and silicon can take place. This mechanism is expected to be highly depending on temperature, following an Arrhenius law for the temperature acceleration. 2. Subsequent copper silicide formation, shorting the pn-junctions of the devices and causing the electrically detectable failure by leakage current increase. This process is expected to be very fast according the study above (cf. Fig. 6) and takes place virtually instantaneously at the barrier stress temperatures of 300 °C to 500 °C once the barrier has degraded. The time to electrical failure is therefore identified as the time to diffusion barrier degradation.

2.4. Barrier development and reliability test method 2.6. Robustness validation To determine the long-time reliability of IGBTs and FWDs, stress tests have been performed at increased temperatures to accelerate the barrier degradation. Each of the chips has been stressed by a sequence of anneals at a constant plateau temperature in the range of 300 °C to 500 °C in inert

The main idea for reliability assessment of the diffusion barrier is to follow a robustness validation approach, which is briefly sketched here: A high number of devices are stressed in an accelerated way (higher

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temperature than operating temperature) until device failure [11]. Ideally the stress duration to failure is monitored for each device individually. For the fundamental intrinsic barrier degradation it is expected that all device fails are tightly distributed around a characteristic stress condition (end-of-life at stress temperature), which should be visible as steep increase in a plot of the cumulated density of failures versus cumulated stress load. Doing this at various temperatures should allow to develop an end-of-life model as function of temperature and to extrapolate it to the operating conditions according to the mission profile of the application. Under these conditions the extrapolation is compared to the quality requirement targets of the application. The chosen approach to stress full wafers at higher temperatures in a furnace however brings limitations in the implementation of the robustness validation approach. Monitoring the leakage current in the furnace is not possible: the thermal background current would be too high, the contacting extremely difficult. Hence the individual time of the device failure cannot be determined. Instead, the temperature stress in the furnace is interrupted for an electrical readout and only the number of cumulated fails at the end of the readouts is analyzed. This discretization is limiting the number of data points available for modelling the cumulative density of failure distribution to the number of readouts instead to the number of tested parts. Only devices on the wafer which are initially pass in the electrical end test of wafer production are considered as part of the sample for the reliability test, as chips failing right at the end of wafer production are meaning a yield loss, but are not further mounted in a product and therefore do not place a reliability risk. 2.7. Failure statistics The stress dependence (duration at temperature) of the cumulated density of failures (CDF) is analyzed in a Weibull plot. The Weibull scale [11] is mainly chosen because the two-parametric Weibull distribution F(t) "
F ðt Þ ¼ 1− exp −

t

β #

t 63

ð1Þ

can easily model the different regimes of the so called “bathtub curve” of the failure rate with its shape parameter β: • β b 1: the fails are early fails, most likely due to defects • β = 1: random fails • β N 1: regime of wear out, especially the end-of-life can be easily detected by a step increase of the CDF.

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The ranking mechanism [12] yields an estimation for the most likely fraction of fail parts F50% in our hypothetical infinite population of devices, from which a sample of n parts is taken and i fails are observed. Since a typical wafer contains N50 parts, the second approximation of mean ranking (Eq. (5)) applies for the presented case. Similarly, also the two sided lower and upper confidence intervals for F according to F low 2:5% ði; nÞ ¼ n−iþ1 i

1 F 2ðn−iþ1Þ;2i;1−α =2 þ 1

F up 97:5% ði; nÞ ¼ 1−

¼ Bp

1 1þ

i n−iþ1

F 2i;2ðn−iþ1Þ;1−α =2





1−α ; i; n−i þ 1 2

¼ 1−Bp



1−α ; n−i; i þ 1 2

ð6Þ 

ð7Þ

for a confidence level of α = 95% are calculated to assess the statistical significance of the limited number of fails i in our sample of size n. The first representation in Eqs. (6) and (7) bases on the Fisher distribution Fx,y,a [12], which can be expressed in the second notation by the inverse beta distribution Bp available in spread sheet tools. Note that with increasing number of fails the confidence intervals get narrower. They are represented as error bars in the plot. For readout times where no devices have failed (i = 0), entering a point into the log-scale-based Weibull plot for the CDF is not possible. To still account for the fact that no fail has been observed up to this point, the single sided upper confidence interval F up 95% ði ¼ 0; nÞ ¼ 1−Bpð1−α; n; 1Þ

ð8Þ

is plotted as error bar. It is obtained from Eq. (7) by adapting the expression for the percentile (1 − α)/2 by (1 − α) to account for the fact that now a single sided instead of double sided confidence interval needs to be employed and setting i = 0. For the temperature acceleration it is assumed that an acceleration according an Arrhenius law is valid for the characteristic Weibull scale parameter t63 according to
 Ea t 63 ðT Þ ¼ t 0 exp kT

ð9Þ

with Ea being the activation energy of barrier degradation, k being the Boltzmann constant, T the temperature, and t0 being a constant factor valid for the respective diffusion barrier [11]. A change in the Weibull shape parameter β with changing temperature would indicate a change in the degradation mechanism [11] and should not be observed. 2.8. Mission profile and quality targets

Since the Weibull plot is rescaling the x and y axis according to x ¼ ln ðt Þ

ð2Þ

y ¼ ln ð− ln ð1−F ÞÞ;

ð3Þ

a Weibull distribution is represented in the Weibull plot as straight line with the slope being the shape parameter β. The scale parameter t63 is the stress duration at which 63% of the devices have failed and the Weibull line intersects the corresponding grid line. The cumulated density of failures F at a specific readout time is obtained by calculating the ranking for i cumulated fail devices out of n initial pass devices according to: F med 50% ði; nÞ ¼

i−0:3 for nb50ðmedian rankingÞ n þ 0:4

ð4Þ

i for n ≥50 ðmean rankingÞ nþ1

ð5Þ

F mean 50% ði; nÞ ¼

The technology shall be able to operate in electrical drives for maximum junction temperatures of up to 175 °C. Useful lifetimes can reach 20 years. Mission profiles for some applications are available but usually treated as confidential by customers, therefore for the sake of simplicity it is assumed for this discussion that a constant operation at 175 °C over 20 years is required. An end-of-life might not happen within this time. 2.9. Initial stages and intermediate stages of barrier development The very first temperature stress tests had been carried out at 400 °C on wafers with the first versions of a fully integrated process for the fabrication of a power diode with a tungsten based diffusion barrier and copper metallization (cf. Fig. 8, red points). The most probable Weibull exponent of 1.5 was indicating only a small tendency into the direction of wear out. The likely explanation was that at this initial stage of development the diffusion barrier quality was not yet sufficient and still mainly governed by defect density, thus yielding not a clear end-oflife behavior. Also, a sufficient reliability was not yet clear. The activation energy for barrier degradation of this specific barrier was unknown.

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In a potential scenario, at the end of the useful life of 20 years at 175 °C, 8% of the chips would have been failed for the measured Weibull parameters t63 = 120 h and β = 1.5 if the activation energy turned out to be as low as 1.0 eV. With 24 chips being in a single product, it meant that every product ever delivered into the field would have been a potential field return. This result was alarming and indicated that further improvement of barrier quality was indispensable and the activation energy of barrier degradation should be determined. Further improvement of the diffusion barrier did yield typical bimodal Weibull-distributions (cf. Fig. 8, blue points) [11]. One branch of the Weibull distribution shows a clear end-of-life behavior with a high slope of β = 9 for the biggest portion of the chips of the wafer. However, also a branch with a shallow Weibull slope of β = 0.4 is clearly visibly. The population of chips of this wafer contains a considerable amount of devices showing a behavior of early fails due to the effect of defect density, which is critical. 2.10. Final stage of barrier development For the final and todays variant of the diffusion barrier a very high effort has been spent to reduce defect density and to even further harden the barrier in terms of intrinsic reliability. The tested wafers do not show any device fails for a stress duration of 2300 h at 500 °C (and 450 °C as well) (cf. Fig. 9, blue points). The single fail occurring and then again vanishing is basically a glitch of the leakage current measurement. Even if the thickness of the target barrier is reduced to 2/3 of its target thickness no end-of-life or extrinsic branch is visible (cf. Fig. 9, red points). Typical thickness variations of the diffusion barrier are much lower than 1/3 of the target value. The missing of a detectable end-of-life in practical stress durations unfortunately means that an end-of-life model for the acceleration of our target barrier cannot be derived. 2.11. Determination of activation energy A final attempt has been carried out to determine a typical activation energy for the tungsten-based diffusion barrier. On dedicated diode test

Fig. 8. Weibull distribution for the initial (red) and intermediate (blue) stage of the diffusion barrier. Stress temperature is 400 °C. Dashed lines are Weibull distributions with parameters as indicated fitting the measured distributions. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

Fig. 9. Weibull distribution for the target diffusion barrier. Stress temperature is 500 °C. Single fails are glitches of the leakage current measurement. No fails can be determined for the 230 chips per variant within 2300 h. (For interpretation of the references to colour in this figure, the reader is referred to the web version of this article.)

chips the diffusion barrier was deposited with roughly an order of magnitude smaller thickness than its target value and slightly changed barrier composition. The higher topology of an IGBT contact hole will not be covered sufficiently by this extremely thin barrier. Purpose of this variant is purely to shorten the end-of-life to make it detectable within reasonable test times and not to fabricate products from chips with this barrier. Therefore, the small extrinsic branch visible in the Weibull distribution (cf. Fig. 10) is uncritical. In fact, an end-of-life behavior with identical Weibull slopes (β = 5) for the two temperatures of 500 °C and 450 °C is observed. From the intrinsic branches also the Weibull time constants t63 for 500 °C and 450 °C are derived. From this an activation energy of 1.9–2.0 eV according to Eq. (9) is deduced. An extrapolation with this high activation energy of 1.9 eV to the target operating temperature of 175 °C now delivers an expected scale parameter t63 of 3.1e11 h = 35 Mio years. As illustration, the corresponding extrapolated Weibull distribution for the intrinsic reliability at 175 °C is plotted in Fig. 10, as it is done within the framework of robustness validation, and also extrapolated to a low density of failures: A fraction of fails of 0.1 ppm is reached after 1e10 h = 1.1 Mio years. The intrinsic reliability of this extremely thin barrier is well sufficient for even the most demanding quality targets for operation at 175 °C. This means that the target barrier which is roughly an order of magnitude thicker should even surpass this intrinsic reliability level. At 500 °C it does not show intrinsic barrier degradation for a time being 7 times larger than the Weibull scale parameter t63 = 320 h of the thin barrier. Comments on the methodology with respect to robustness validation: • Typical mission profiles for operation at a maximum junction temperature of 175 °C would lead to effective temperatures even a few degrees lower, meaning that the extrapolation to 175 °C continuous operation is conservative. The effective temperatures are calculated by weighting the durations at various temperatures of the mission profile with the acceleration they experience due to the Arrhenius law for the barrier degradation mechanism. • It would have been desirable to test at an at least third temperature to actually prove the acceleration by an Arrhenius law. However, lower

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Fig. 10. Weibull distribution for extremely thin diffusion barriers on diode test structures. This barrier is too thin for reliable IGBT fabrication. Stress temperature is 500 °C. (For interpretation of the references to colour in this figure, the reader is referred to the web version of this article.)

temperatures lead to not feasible test durations. Higher temperatures increase the risk of triggering different degradation mechanisms and also would have required taking the risk to operate the mission critical single furnace in the reliability lab at the limit of its temperature specification. • One could also argue whether the data might not be better fitted by a log-normal distribution, which would change the extrapolation of the intrinsic behavior to ppm-level a little. Given the extraordinary high intrinsic reliability, this however would not lead to a relevant change of the interpretation for the intrinsics. The required high number of data points can also not be generated by the selected technique, because an in situ monitoring of the leakage current is not possible in the furnace, as already stated. • It would have been especially very desirable to extend the measurement at 450 °C to also reach N63% of fails. However, the test at 450 °C had to be stopped after 1800 h due to practical limitations.

3. Reliability of interconnects The front side copper metallization does not only improve the short circuit ruggedness, it also acts as base-material for the top-side chip interconnection by copper wedge bonding. Combined with a new die attach technology, as well as an improved optional substrate-to-baseplate solder and ultrasonic-welded power terminal interconnects, a significant increase in lifetime is possible. 3.1. New packaging materials

2.12. Barrier reliability after bonding

Besides conventional passive thermal test procedures like thermal cycling (TC) or thermal-shock-tests (TST), the continued heating and cooling of power modules by a load current is the most important test procedure to assess the lifetime of a module technology under operating conditions (power cycling, PC). Thereby key test parameters like relative temperature swing ΔT, the maximum junction temperature Tjmax or the power-on-time ton define, which interconnect level is stressed most at which amount of mechanical load [13,17]. For standard technology concepts based on aluminum wire-bond top-side interconnects,

The wafer level stress tests were also used to evaluate the barrier after bonding. During the copper wedge bonding process, the deformation of the copper metallization transfers a high mechanical stress into the barrier structure. It has been shown by many cross sections of bond feet that these deformations do not extent into the much harder tungsten based barrier. To ensure that the reliability of the barrier does not suffer from the copper wedge bonding, wafer-level stress tests were performed additionally on bonded wafers. For this purpose, bond feet were placed on IGBT or FWD wafers by an adapted bonder, using the same bond parameters as for productive wire bonding. On each chip, an area on the pad was left without bond feet for contacting with the wafer prober at electrical measurement. The bond feet were bonded without wire loops to make automated electrical testing easier (cf. Fig. 11). The bonded wafers were stressed and tested with the same conditions and with the same equipment as the non-bonded wafers. Comparing the results of the stress test on non-bonded and bonded chips, we found the same amount of barrier fails per chip on both groups. In conclusion, the copper wedge bonding has no negative impact on the barrier reliability.

Fig. 11. Chips on a 200 mm IGBT5 test wafer with Cu wire bond feet for high temperature wafer-level stress test.

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soft-solder die-attach and copper-metalized substrates, the lifetime is limited by failure mechanisms like wire bond lift-off, heel cracks and solder degradation. In the most general sense the thermally induced mechanical stresses leading to an interconnect degradation are caused by a CTE mismatch between the different joint materials or by an inhomogeneous spatial temperature distribution. The amount of degradation and with it the time-to-failure of the interconnections are consequently defined by the mechanical properties of the interconnect materials themselves. The fatigue life of metallic materials exposed to cyclic mechanical loads is at temperatures up to 40% of the absolute melting temperature correlated with the amount of plastic deformation occurring during each cycle [14]; to provide an increase in fatigue life the cyclic deformation needs to be predominantly elastic. The well-known rules of Basquin (elastic deformation) and Coffin-Manson (plastic deformation) correlate the amount of elastic and plastic deformation to the total number of cycles to failure Nf.

Δεt ¼ Δεe þ Δεp ¼

K 1 c1  N f þ K 2  N cf2 E

ð10Þ

Here E is the Young's modulus of the stressed metal. The coefficient K1 corresponds to the nominal tensile strength, K2 is proportional to the failure strain. The Basquin exponent c1 is in the range of 0.05–0.12 for metallic materials while the fatigue ductility exponent c2 is between −0.5 and −0.7. At temperatures above approximately 40% of the melting temperature self-diffusion sets in and with it creeping effects cannot be neglected any longer. Thus deformation is not only dependent on the magnitude of the stress but also on its duration. Furthermore material recovery and grain growth gain importance; for practical purposes these effects in general lead to a stronger degradation of the material in dependence of the load frequency [14]. The implementation of the Cu chip metallization and the barrier-system designed for wire-bond processes with hard metals allows the introduction of thick wire bonds made from copper. Next to a higher electrical conductivity copper has a much higher yield and tensile strength as well as a significantly lower CTE compared to the conventional Al bonds. Therefore the amount of plastic deformation for a given temperature cycle is significantly lower compared to aluminum. In Table 1 the basic properties of copper in comparison to aluminum are listed. For the die attach novel technologies such as diffusion soldering or sintering of silver particles are employed. Diffusion soldered (DS) die attach layers consist exclusively of intermetallic compounds, which have higher melting points and higher mechanical strengths compared to conventional solder alloys [15]. The mechanical, thermal and electrical properties of sintered Ag die attach layers (low temperature joining technique, LTJT) are dependent on the porosity. For high performance purposes the porosity should be as low as possible. Compared to soft solders standard LTJT-layers benefit from an increased mechanical strength, moreover the high melting point of silver (1235 K) prevents from degradation due to creeping [16–19]. For the second level interconnection reliable power terminals can be realized by US-welding. For module types with baseplate the substrate-to-baseplate interconnect is realized by the introduction of a new solder technology, which

shows a higher reliability during active and passive temperature cycling [15–17].

3.2. Failure modes & lifetime In Fig. 12 the power cycling results of samples employing copper wire-bonding for the top-side interconnect and diffusion soldering or sintering for die attach are shown. In the diagram the PC results from samples with baseplate are marked in red while the samples without baseplate are green. To gain power cycling results within an acceptable timeframe, only tests with ΔT N 85 K were performed. In [16,17] the failure mechanisms of these samples were investigated in detail for setups with and without baseplate separately. For none of the investigated samples any degradation of a wire-bond interconnection could be found (cf. Fig. 13). For test samples employing a baseplate the degradation of the substrate-to-baseplate solder was the lifetime limiting failure mode in this Δ T-range. Thus no difference between modules with sintered or diffusion soldered die attach layer in lifetime could be identified (cf. Fig. 14a, b). Samples without baseplate fail due to degradation patterns that are related to the copper metallization of the DCB substrates. The delamination of the front-side DCB metallization combined with a degradation of the front-side metallization below the chip is observed for LTJT layers (cf. Fig. 14c, e); at the same time the formation of cracks within the LTJT layer becomes visible. Samples with DS die attach layers are limited by the degradation of the back-side copper of the DCB (cf. Fig. 14d). In order to create a first lifetime-model in [17] a detailed analysis of the lifetime in dependence of ΔT, ton and Tjmax was discussed and presented. Based on the lifetime-modelling approach from [13] and certain assumptions by grouping failure mechanisms to a) DCB related failures for baseplate-free samples and b) failures related to substrate-to-baseplate-solder, first lifetime models for .XT modules with and without baseplate could be derived. The lifetime of baseplate-free samples can be described by a simple power-law as a function of the temperature swing Δ T (cf. Fig. 15); an influence of the absolute temperature Tjmax and the power-on time ton could not be found within the investigated data. This is in good agreement with the expectations as time- and temperature-dependent degradation should not be significant as long as

Table 1 Physical properties of aluminum and copper.

Yield strength Re [N/mm2] CTE [1/K] Tensile strength Rm [N/mm2] Melting temp. Tm [°C]

Aluminum

Copper

20–50 23 ∗ 10−6 30–70 660

50–90 16 ∗ 10−6 210–250 1083

Fig. 12. Power cycling results of .XT samples w/ and w/o baseplate.

Please cite this article as: F. Hille, et al., Reliability aspects of copper metallization and interconnect technology for power devices, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.07.119

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Fig. 13. Microsection of a Cu wire-bond of a .XT test sample w/o baseplate and with LTJT die attach after 665 k cycles at ΔT = 130 K (picture from [20]).

low melting metals like soft-solder are not part of the stressed material stack. In contrast to that for samples with baseplate and the corresponding solder a dependency of ton as well as on Tjmax was found [17]. Thereby the ton dependency not only refers to a stronger material degradation but also to a shift of the maximum degradation within the baseplatesolder from below the chips to the edges of the DCB with increased ton. By decreasing ΔT, Tjmax and especially ton the stress within the baseplate-solder is reduced. A sample with ton = 2 s, Tjmax b 175 °C and

Fig. 15. Power cycling results and lifetime-curve of samples without baseplate for 85 K b ΔT b 140 K.

Δ T ≈ 100 K could prove a lifetime of N6 · 106 cycles. Thereby even the lifetime of baseplate-free samples could be exceeded. The analysis showed, that – even though the module still finally failed due to baseplate-solder degradation – first signs of degradation within the DCBtop-side-copper and the LTJT-layer could be found. At the same time no copper delamination from the DCB-ceramic was visible. It is known from passive testing, that the delamination of the DCB copper is hindered by the baseplate fixture. This leads to the assumption, that for test condition with low Δ T and ton the main failure mechanisms also for samples with baseplate are defined by the DCB-copper and the LTJT layer. From a mechanical point of view, it can be assumed that below a certain threshold for ΔT and ton the plastic deformation per cycle only has negligible impact on the samples lifetime. As a result, for very low ΔT and ton values, a major increase in reliability compared to the high ΔT- and ton-region could be expected. Current activities are focused on proving these assumptions. 4. Summary

Fig. 14. Power cycling failure mechanisms of test samples with .XT technologies (pictures from [7]): Degradation effects are marked by red arrows. Samples w/ baseplate (a, b) show degradation within the substrate-to-baseplate solder while samples w/o baseplate (c, d, e) reveal the main degradation within the DCB-copper or at the DCB interfaces. (e) Scanning acoustic microscopy (SAM) image of a sintered baseplate-free PC-sample. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

The .XT technology comprises copper wedge bonding on a thick copper metallization, separated by a tungsten-based diffusion barrier from silicon, and an improved die attach technique. Thick copper metallization and the improved die attach significantly improve the critical short circuit energy by up to 85% for a 1200 V technology, enabling further electrical performance optimization. A highly reliable diffusion barrier is required, since Cu3Si formation does happen already at room temperature and Cu3Si grains are shorting the pn-junctions of devices. An efficient test method to stress the diffusion barrier on full wafers in a highly accelerated way at temperatures in the range of 300 °C to 500 °C has been developed. This enabled the implementation of a robustness validation approach to model the failure statistics, create an end-of-life model and extrapolate the end-of-life model to the operating condition. Initial diffusion barriers did not show intrinsic behavior, intermediate stage barriers did show significant extrinsic branches. Further improvement of barrier quality hinders the observation of the end-of-life of the target diffusion barrier within 2300 h at 500 °C. A thin tungsten based diffusion barrier suitable only for test structures and derived from the target barrier shows intrinsic

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end-of-life behavior at 500 °C and 450 °C, allowing the determination of the activation energy for barrier degradation to 1.9 eV to 2.0 eV. The extrapolation to operation at 175 °C yields an intrinsic barrier lifetime of 1.1 Mio years for 0.1 ppm and 35 Mio years for 63% of these test structures. The intrinsic reliability for the thicker target barrier is expected to be even higher. Wafer level tests with copper bond wedges reveal no difference to wafers without bonds. The introduction of copper wire-bonds in combination with silversintering or diffusion soldering for die attach leads to a significant increase in lifetime for products with and without baseplate. The degradation mechanisms during power-cycling in power modules employing the .XT-technology are analyzed as a function of the test conditions and the module setup. While for modules employing a baseplate the degradation of the corresponding baseplate-solder is the lifetime-limiting failure mechanism, samples without baseplate fail by degradation related to the DCB-copper. For baseplate-free modules no dependence of the lifetime on ton or Tjmax could be found; the lifetime in the investigated range of ΔT and ton can be described by a regular power-law as a function of ΔT. It has to be emphasized, that the lifetime models for the diffusion barrier and the power cycling reliability given in this document shall in no event be regarded as a guarantee of conditions or characteristics of referred products, as e.g. presented in [21]. Acknowledgements The authors would like to acknowledge the contributions of and discussions with Matthias Müller, Ingo Österreicher, Sandra Krasel, Werner Robl, Kurt Pekoll, Wolfgang Apolloner, and Adriana Sanchez. References [1] A. Ciliox, J. Görlich, K. Guth, F. Hille, S. Krasel, D. Siepe, P. Szcupak, F. Umbach, New Module Generation for Higher Lifetime, PCIM, Nuremberg, Germany, 2010. [2] R. Baburske, H.J. Schulze, F.-J. Niedernostheide, F. Pfirsch, F. Hille, Modelling of effects in high power IGBTs and diodes at the edge of the safe operating area, Proc. ISPS2014, Praha, 2014.

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Please cite this article as: F. Hille, et al., Reliability aspects of copper metallization and interconnect technology for power devices, Microelectronics Reliability (2016), http://dx.doi.org/10.1016/j.microrel.2016.07.119