Advanced multilevel metallization technology

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appliect surface science ELSEVIER

Applied Surface Science 91 (1995) 1-11

Advanced multilevel metallization technology Takayuki Ohba * Fujitsu Limited, Process Development Division (M / S C851), 1015 Kamikodanaka, Nakahara-ku, Kawasaki 211, Japan Received 20 April 1995; accepted for publication 23 May t995

Abstract In order for ULSI manufacturing to minimize the COO (cost of ownership) aspect in the wiring process and realize fabricating over 256M bits DRAM, several wiring technologies have been proposed. The evidential criteria in choosing the most probable one are physical or material limitations (e.g. step-coverage and resistivity) and requirements from manufacturing (e.g. process complexity, reliability, throughput, and total cost). Therefore, a combination of metallurgy using chemical vapor deposition (CVD) with simplified multilevel interconnects has a high potential in overcoming those difficulties. In this paper, an integrated multilevel metallization (IMM) by considering the above criteria is discussed. Alternatives of improved W-CVD, TiN-CVD using diborane (B2H 6) and methylhydrazine (MH) reduction, selective W-CVD, and Cu wiring are described from our recent studies.

1. Introduction In giga-scale integrated (GSI) devices and circuits down to 0.1 /zm design rule, a number of metal interconnection problems have arisen. One is evidently the physical limitation such as the poor step coverage of sputtered aluminum (A1) wire, barrier metal (e.g. titanium nitride = TIN), and contact metal (e.g. Ti). In addition, these have a material limitation due to electromigration (EM), stress migration (SM), resistivity, and contact resistance to Si, respectively. This is the reason why tungsten (W), TiN, and copper (Cu) wiring by chemical vapor deposition (CVD) have been studied and developed. How to

combine sputtering with CVD (integrated multilevel metallization, IMM) is a key to fabricate GSI devices [1]. Another issue is how to reduce the process complexity and process cost, and how to integrate interconnects by selecting the appropriate alternatives and planarization techniques, whether the conventional or a use of chemical mechanical polishing (CMP). In this paper, the trend towards multilevel metallization for devices over 256M bits is discussed. We describe the simple and feasible IMM using W, TiN, and Cu-CVD based o n our recent studies.

2. Via-plug technologies for next generation

* Corresponding author. Tel.: + 81 44 754 2489; Fax: + 81 44 754 2723; E-mail: hch00561 @niftyserve.or.jp.

As to now, in general, four different contact and via-plug processes have been proposed (Fig. 1). Comparing a number of steps to be filled via-holes,

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the process complexity increases as follows: selective W-CVD, blanket TiN-CVD, sputtered A1 with reflow, and blanket W-CVD. A common process in these is the surface cleaning which must be carefully done and which is also a key technology for an ideal metallization with good electrical properties. Among these via-plug processes, the blanket W and sputtered A1 are limited by the poor step-coverage of the contact and barrier metal underlayers such as titanium (Ti) and TiN. This is because the degradation of the junction leakage current and void formation take place by the poor step-coverage [1]. One of the more serious problems is the thickness of the barrier metal. Since the barrier metal has to have an adequate thickness in order to prevent unexpected diffusion, via-holes will be consequently filled with the barrier metal in GSI with decreasing the feature size, as shown in Fig. 2. Due to such geometrical problems, the same thing would occur in Cu wiring. Therefore, before GSI generation, via-hole filling

Cleaning

Selective W

Sputter TiN

using blanket W-CVD and A1 sputtering will be used, and TiN-CVD and selective W-CVD or A1CVD will be adopted afterwards. On the other hand, the investigation of selective W-CVD would be appropriate for developing selective A1-CVD and Cu-CVD, because the selective W-CVD is a well-known example in the understanding of the surface cleaning and the reaction mechanism. The current chemical-mechanical polish (CMP) as an alternative planarization technique helps to reduce the difficulty of selectivity loss by polishingoff unexpected W particles formed on a dielectric surface. TiN-CVD, used as a barrier metal of W-CVD and A1, is used instead of the sputtering since some drawbacks such as, A1 corrosion due to chlorine (C1), trade-off of the lowering deposition temperature, and film resistance have been solved, e.g. a use of monomethyl hydrazine reduction chemistry. For contact metallization, a combination of collimated sputtered-Ti, plasma Ti-CVD, and other metals enough

Sputter AI

O -!

IX, I-(~laanlnn

C~n . T !

~n .TiM

Rlanlza~ W~tPh.h~k~nlltt~r

AI

O IZ O O _i

0 0

Fig. 1. Via-plugprocess using selectiveW-CVD,blanket W-CVD, A1 sputtering, and TiN-CVDfor 0.2 to 0.8 /xm size.

T. Ohba / Applied Surface Science 91 (1995) 1-11

64M to 256M bit DRAM

I

>IG bit DRAM I

¢z > 0 z I

I1

E

j O e" Oi

O I

I

I

Fig. 2. A use of TiN-CVD film for the underlayer of AI sputtering and blanket W-CVD and results from 64 Mbit to 256 Mbit DRAM wiring. An alternative technology will be required beyond 1 Gbit fabrication.

to achieve lower contact resistance for Si(n +) and Si(p +) would be necessary to realize GSI devices.

Fig. 4. This W layer consisted of B-phase or a-phase structure with some undefined structures such as WB crystal, as shown in Fig. 5.

3. L o w resistance W - C V D Most companies use blanket W - C V D processes to fabricate 16M and 64M bits D R A M s because of the productivity benefits [2]. At high current density, about 10 6 A / c m z, blanket W wire is used instead of A1 in order to prevent the open failure from electromigration (EM). High resistivity of W - C V D wires, however, may cause serious problems such as R C delay due to high wiring resistance and a high wiring capacitance due to the feature of a high aspect ratio. Recently, we found that blanket W - C V D using a diborane ( B z H 6 ) reduction achieves low resistance (e.g. 7.0 f t . cm at 440°C) rather than H 2 reduction as shown in Fig. 3 [3]. This difference can be explained from decreasing of fluorine (F) remaining in the W film (Fig. 4). Thus B2H 6 reduces W E 6 including intermediates of W F x (1 < x < 6) easier than that of H 2 reduction. The resistivity of the B2H6-Ha-reduced film is about 50% lower than those of H2-reduced film even at a thickness of 150 nm. At the low temperature region, the blanket W contained a high boron (B) concentration, as seen in

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100 200 300 400 500 600 700

Thickness (nm) Fig. 3. Resistivity of blanket W-CVD using H 2- and B 2 H~-reduction as a function of film thickness.

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200 250 300 350 400 450 Deposition Temperature (°C)

Fig. 4. Fluorine (F) and boron (B) concentration in blanket W as a function of deposition temperature.

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On the basis of poor adhesion and chemical etching by WE6,the blanket W must be used with a TiN underlayer with the condition of being thick enough to prevent peeling-off of the film and diffusion. Although the TiN-CVD has a capability of conformal deposition, there are some problems concerning resistivity (due to a residue of carbon or chlorine)

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Fig. 6. Film resistivity of blanket W as a function of gas flow rate of B2H 6.

4. Fig. 6 shows film resistivity as a function of B2H 6 flow rate. There was an optimum region giving low resistivity. B2H 6 with H 2 reduction achieved 100% of step-coverage at 0.6/xm in diameter and aspect ratio 1.4 without degrading resistivity, as shown in Fig. 7. This is because two kinds of effect such as high step-coverage in H 2 reduction and lowering impurities in B2H 6 reduction are simultaneously taking place, which may be followed by the so-called concerted reaction [4]. Using this B2H6-H2-reduced blanket W, similar electrical properties in contact resistance to TiSi 2 were obtained (Fig. 8), which proved the feasibility for practical devices.

1

B2H6 Flow Rate (sccm)

70

80

Fig. 5. High resolution X-ray diffraction pattern of B2H~-reduced blanket W formed at 250°C.

WF6-H2-B2H

6 Reaction

QH2/QB2.6

System

= 666.7

( S t e p c o v e r a g e = 100%) Fig. 7. SEM cross-sectional view of B2H6-H2-reduced blanket W at a contact hole of 0.6/xm in diameter and an aspect ratio 1.4.

T. Ohba /Applied Surface Science 91 (1995) 1-11

5

Type of S/D Diffusion Layer for TiSi 2 ]

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Fig. 8. Contact resistance of W to TiSi 2 formed on Si(n +) and Si(p +) s o u r c e / d r a i n ( S / D ) regions.

and trade-off for deposition temperature. Especially, TiN-CVD using the ammonia (NH 3) reduction [5-9] cannot be used for the via-plug process over the A1 wire, since its deposition temperature is higher than 600°C. TiN-CVD using a methylhydrazine (MH) reduction reaction of titanium-tetrachloride (TIC14) realized a low chlorine (C1) impurity in TiN films even at low temperatures ( < 500°C) [10,H]. Fig. 9 shows film resistivity of TiN using MH- and NH3-reduction as a function of deposition temperature. The decreasing resistivity with temperature is explained by the reactivity of MH to TiC14 as well as the B2H6-reduction as discussed above. Furthermore, the reaction kinetics in MH-NH3-reduction apparently changed with the flow-rate ratio of MH/TiC14 at a constant of NH 3, as shown in Fig. 10, approaching to the mass-transported reaction at MH/TiC14 = 0.15 and the rate-limited at no MH [12]. MH gas has an extra reaction to Ti prior to TiN deposition. Ti was nitrided by MH at low temperatures, as shown in Fig. 11 [13]. Thus, MH acts as a reduction gas for

TiC14 and nitrogen source for nitridation instead of NH 3 and N 2 at low temperatures. According to these reaction kinetics, high stepcoverage with low resistivity was achieved as shown in Fig. 12. Therefore, at via-holes below 0.2 /zm in

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400

500

600

700

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.>_. 200 u) (o m 100 n-' 0 m

300

800

Deposition Temperature (°C) Fig. 9. Resistivity of TiN-CVD film using NH 3- and MH-reduction of TiC14 as a function of deposition temperature.

6

T. Ohba/Applied Surface Science 91 (1995) 1-11

Deposition Temperature (°C) 1000

550

500

450

I E

700

TiCl4=10sccm I I NH3--~0sccm I [ Press.=100mTorrJ

R(MH/TiCI4)

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1000/T (l/K) Fig. 10. Arrhenius plot of MH-NH3-reduetion for various flow rate ratios of MH/TiC14 at constant NH 3.

diameter, blanket W or A1 plug is no longer necessary. Since MH-reduced TiN has high enough to prevent diffusion, the lowest junction leakage current at the Si contact holes was succeeded (Fig. 13) [14]. Also, an ideal contact resistance change was obtained down to 0.2 /xm in diameter as shown in Fig. 14 [15]. These electrical properties can be explained by the fine step-coverage as shown in Fig. 15. Therefore, a use of TiN contact plug would promise and solve semiconductor manufacturing beyond 256M bits D R A M without increasing the process complexity and the total cost in multilevel metallization.

Fig. 12. SEM cross-sectional view of a completely filled contact hole using MH-reduced TiN-CVD.

5. Selective tungsten plug Since via-holes are filled in one process step, selective W-CVD is very cost-effective when compared to other plug processes. Selective W-CVD can also fill Via-holes with no limitation for the hole size if the clean surface on the bottom of the via-holes is obtained. Thus, most studies in selective W-CVD have been focused on the cleaning being compatible

100

B-W/TiN/Ti/Si(n+)

,~= 151 tTemperature = 450oc ~ I~--~---~ --~"-

I IMH Pressure = 0.1Torr I I Treatment Time = 120s I

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Sputter-TiN A v = 2.34 nA

i

N ¢¢

40

M W MH-TiN I~ Av. = 0 . 3 n A

10 2 0 30 40 50 60 Sputtering T i m e (min)

Fig. 11. AES depth profile of sputtered Ti after MH treatment at 450 o C.

1.0

10

Leakage Current (nA) Fig. 13. Junction leakage current of blanket W / T i N / T i / S i ( n + ) using MH-reduction and conventional sputtering at parallel contact holes of 0.5 /~m in diameter each.

T. Ohba /Applied Surface Science 91 (1995) 1-11

7

A Comparison of CVD and PVD TiN Barrier/Adhesion Layer Wiring MH-TiN Sp.-TiN

10 4

"~ 1 0 ~

AI

; " " " " "'":::i:"

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0.2

0.~

0.5

1.0

2.0

Contact Diameter (urn) Fig. 14. Kelvin contact resistance of blanket W / T i N / T i / S i ( p + ) structure using MH-reduction and conventional sputtering as a function of contact diameter down to 0.5 ~ m .

with high selectivity. Such surface cleanness also has an effect on the contact resistance not only in selective W but in general metallization, so we should discuss the surface cleaning at the same time. Wet cleaning is no longer an adequate cleaning for the selective W-CVD. Highly adsorbed moisture tends to degrade selectivity as shown in Fig. 16. An alternative dry cleaning using nitrogen trifluoride (NF 3) and hydrogen (H 2) chemical cleaning allows sufficient W growth on Si and WSi 2 surfaces with high yield in practical devices (Fig. 17) [16,17]. RF plasma cleaning would damage the oxide surface but it can be reduced by halogen termination on the

B-W

.

.

.

.

.

.

.

.

.

.ii:!i~i~lJ"~~

:::!~!~!~~ , ' : . :: ~i~ . ~ , ' :

Fig. 15. Schematic diagram of electrical properties for a use of conformal TiN-CVD versus sputtered TiN in A1 and blanket-W.

oxide surface. A similar effect was seen in chlorine trifluoride (CIF 3) cleaning as shown in Fig. 18. The selectivity was improved with increasing fluorine (F) concentration on the SiO 2 surface. Using C1F3 cleaning, low contact resistance and high selectivity was achieved at the via-holes formed on the TiN/A1 wires on the entire 6 inch wafer surfaces (Fig. 19). On the other hand, we have another choice to avoid selectivity loss with a combination of the CMP technique, which is starting to be used for the global planarization of dielectrics [18]. A combination of selective W-CVD with CMP realizes a plane W

Fig. 16. SEM images of selectivity loss with no treatment (left) and after annealing (right).

8

T. Ohba/Applied Surface Science 91 (1995) 1-11 1.2

'O l ave. ,o =' , .,42

1.0 W e t (DHF)

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Selective W - p l u g

1

2

3 4 5 6 7 Contact Resistance ( ~ )

8

Fig. 19. Contact resistance of selective W deposited on TiN at 0.6 /xm via-holes using a 6 inch wafer.

Fig. 17. Device yield using selective W-CVD formed simultaneously on Si-S/D and WSiz contacts after DHF or DHF+NF3 cleaning.

plugs, even some selectivity loss and over filling take place as shown in Fig. 20. Although there are several solutions to overcome selectivity loss, an ideal deposition atmosphere is needed to achieve highly reproducibility with high throughput in the manufacturing. To reduce unexpected by-products and achieve ideal gas flow are important for controlling precise atomic level deposition even on 12 inch wafers being used in the next generation. W e are investigating a silane (Sill 4) reduction process [19,20] and have developed a low pressure CVD reactor as shown in Fig. 21. This

Fig. 20. SEM top-view of selective W-CVD over-filled above 1 /.~m after polished-offusing CMP. reactor provided a showerhead, so-called matrix showerhead, capable of no gas mixture within the showerhead when several gases were used. The ma-

Fig. 18. SEM images of selectivityloss at patterned SOG surface with no treatment(left) and after CIF3 cleaning(right).

T. Ohba / Applied Surface Science 91 (1995) 1-11

Pyrometer

9

(8-141~m)

Temperature 250

1 024

Matrix Showel

200

t

/

I

150 I

(°C)

100

50

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DamasceneCU 0.25p,m l ~ Conventional AI 0.8 prn 1 0 22 J=O.3-5.0x10 J~/crn 2

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. tt without passivation for teston Cusample

~/F6 ~.iH4

~ 1018 ~'~1016

O

(~_

~'~ 1016

~ N o Failure U within 30000s

W halogen lamp Fig. 21. Schematic diagram of a low pressure CVD reactor provided a matrix showerhead.

1 014 -

1.8

2.1

2.4 2.7 3.0 1000/T (K "1)

3.3

Fig. 23. Lifetime of open failure due to electromigrationfor 0.25 /~m DamasceneCu wire. trix shower head has no limitation for the wafer size. Using this matrix showerhead, we revealed that selectivity changed with gas flow and its velocity even under the same conditions of gas flow rate of W E 6 and S i l l 4 [21]. This suggested that we must carefully control the gas concentration on the wafer surfaces more than the gas flow rate of the mass flow controller (MFC). The reaction kinetics using partial pressure of gas is not enough to discuss practical deposition.

5.0

[ ] Damascene Cu Wire A

(1"=0.3pm) J=1,0-2.5 x 108A/cm =

E 4.0 0

~.~:L3.0 2.o

6. C u m e t a l l i z a t i o n Copper (Cu) metallization is one of the most attractive of the alternate choices for GSI devices because of its lowest resistivity among A1, W, and Au, and higher resistance to electromigration failure, as shown in Figs. 22 and 23 [22,23]. Higher reliability more than two orders of magnitude has been

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mm ~

m 1.o

o,0 o.o

0.2

0.4

0.6

Width

1.2

(pm)

Fig. 22. Resistivity of Damascene Cu formed by CVD as a function of Cu wire width.

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~ ~!. . . .

Fig. 24. Schematic diagram of wiring capacitance for AI (top) and Cu (bottom).

T. Ohba /Applied Surface Science 91 (1995) 1-11

I0

respectively, before sufficient Cu filling is established.

~~;~'~ self-aligned ~::~ CUwiril~': ....

~1"

~~ [ ~

Fig. 25. Damascene process and cross-sectionalview of 0.2 /~m Cu wires.

proved in Cu wiring compared to conventional AI even at a quarter-micron width. According to the lower resistivity, we can expect an aspect ratio of wire less than A1, and low wiring capacitance which reduces the R C delay(Fig. 24). Using a self-aligned wiring such as the Damascene method, a 0.2 /xm Cu wiring appropriate to GSI interconnects has been successful, as shown in Fig. 25. Damascene Cu wiring can be adopted alternatively to the conventional etching processe s, which have some drawbacks due to the high temperature process and corroSion. However, since Cu is easily oxidized and corroded, a sufficient barrier metal and its combination must be provided. For instance, a part of the Cu wire can consequently disappear as well as blanket W and AI, according to shrinking design rule of wires less than the total thickness of the barrier metal. Therefore, most of the concern in Cu wiring is the thin barrier metal, chemical-mechanical polish (CMP), and a high enough step-coverage to fill Cu into the groove and. via-hole. To reduce process complexity, a dual-Damascene method has been attempted since it needs only single step Cu deposition for wiring at the via-hole and interconnects simultaneously. Practically, it is worth developing the Damascene process using CVD and sputtering for vias and interconnects,

7. Summary By GSI generation, either blanket W-CVD or A1 combined with flow process will be used in via-plug and wiring. As BEH 6 reduction realized about 50% reduction of resistivity of W film, W local interconnects instead of A1 is appropriate. A single step process such as TiN-CVD and selective W-CVD can be used beyond 256M bits DRAMs because the thickness of TiN is being limited from barrier property in blanket W-CVD and A1. Thus TiN-CVD and selective W-CVD have to have sufficient step-coverage and selectivity, respectively. TiN-CVD using methylhydrazine reduction for Si contact holes down to 0.2 /xm is discussed, and surface cleaning using NF 3 and C1F3 proves that selectivity and device yield was improved. Use of tungsten CVD for practical multilevel interconnection has provided much information that will help to develop the worthwhile production processes of other CVD metals, such as for A1- or Cu-CVD interconnection. Since the resistivity of via-holes beyond GSI increases the total resistance of the interconnects, Cu wiring is the best candidate as compared to A1, TiN, and W. The Damascene method, an alternative to conventional patterning, an adequate Cu filling process, and thin barrier layer must be developed. For giga-bit device fabrication, production of worthy CVD metallization has great advantages over conventional sputter processing, but we must weigh the total metallization cost, including equipment cost, number of process steps, throughput, and reliability, against the process features described above.

Acknowledgements I wish to express my sincere thanks to all engineers in the multilevel metallization project of Fujitsu for processing, testing, and assisting experiment; and M. Yamada, Y. Yagi, Y. Furumura, and H. Tsuchikawa for their encouragement during this study.

T. Ohba /Applied Surface Science 91 (1995) 1-11

References [1] T. Ohba, in: Proc. Advanced Metallization for ULSI Applications, Eds. V.V.S. Rana, R.V. Joshi and I. Ohdomari (Materials Research Society, Pittsburgh, PA, 1992) p. 25. [2] For example, see: Y. Takata, A. Ishii, M. Matsuura, A. Ohsaki, M. Iwasaki, J. Miyazaki, N. Fujiwara, J. Komori, T. Katayama, S. Nakao and H. Kotani, in: Proc. 8th IEEE Int. VLSI Multilevel Interconnection Conf., June 11-12 (1991) p. 13. [3] T. Hara, T. Ohba, H. Yagi and H. Tsuchikawa, in: Proc. Advanced Metallization for ULSI Applications in 1993, Eds. D.P. Favreau, Y. Shachman-Diamond and Y. Horiike (Materials Research Society, Pittsburgh, PA, 1994) p. 353. [4] T. Ohba, H. lio, M. Higashimoto, T. Hara, K. Watanabe, H. Yagi and Y. Furumura, Extended Abstracts, The 42th Spring Meeting, 1995 (The Jpn. Soc. of Appl. Phys. and Related Soc.) 29aK-II-9. [5] F. Pintchovski, T. White, E. Travis, P.J. Tobin and J.B. Price, in: Proc. of Tungsten and Other Refractory Metals for VLSI Applications IV, Eds. R.S. Blewer and M.C. McConica (MRS, Pittsburgh, PA, 1989) p. 275. [6] N. Yokoyama, K. Hinode and Y. Homma, J. Electrochem. Soc. 136 (1989) 882. [7] A. Sherman, J. Electrochem. Soc. 137 (1990) 1892. [8] M.J. Buiting, A.F. Ottedoo and A.H. Montree, J. Electrochem. Soc. 138 (1991) 500. [9] J.T. Hillman, M.J. Rice, Jr., D. Srinivas, E.C. Eichman, W.M. Triggs, B. Sommer, M. Churley and C. Bell, in: Proc. Advanced Metallization for ULSI Applications, F_As.V.V.S. Rana, R.V. Joshi and I. Ohdomari (MRS, Pittsburgh, PA, 1992) p. 311. [10] T. Suzuki, T. Ohba, Y. Furumura and H. Tsuchikawa, IEEE IEDM Tech. Dig. 979 (1992). [11] T. Ohba, T. Suzuki, Y. Furumura and H. Tsuchikawa, in: Proc. 44th Symp. on Semiconductors and Integrated Circuits

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