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Advanced multilayer metallization schemes with copper as interconnection metal
Thin Solid Films, 236 (1993) 257-266
257
Advanced multilayer metallization schemes with copper as interconnection metal S. P. M u r a r k a
a n d R . J. G u t m a n n
Rensselaer Polytechnic Institute, Troy, N Y 12180 (USA)
A . E. K a l o y e r o s
and W. A. Lanford
University at Albany, Albany, N Y 12222 (USA)
Abstract Advanced metallization schemes are needed to take advantage of the miniaturization of microelectronic devices which are performing at increasingly high speeds. The demands on metallization center around (a) the increased resistance with lower cross-sectional areas and longer interconnect lengths and (b) stability with the surroundings during processing and use under high current densities and thin film stresses. A threefold attack is being pursued to solve these problems, which also duplicate the issues in packaging of these fast chips with large numbers of inputs and outputs: first is to make use of copper as the interconnection metal; second is to use a multilevel metallization scheme; finally there is a need for a low dielectric constant dielectric. In this paper we present a review of progress made in addressing the first two schemes together with a brief discussion of the third. Copper, a heretofore undesired metal in silicon integrated circuits, seems to show promise, with appropriate processing constraints, of fulfilling the projected needs of ultra-large-scale and giga-scale integration and perhaps even of packaging.
I. Introduction Continuing advances in the fields of very-large-scale integration (VLSI), ultra-large-scale integration (ULSI) and giga-scale integration (GSI), leading to the progressive development of smaller and smaller devices, have continually challenged the fields o f materials, processes and circuit designs. The existing metallization schemes for ohmic contacts, gate metal and interconnections are found to be inadequate for the ULSI and GSI era. Added to these concerns are the reliability of aluminum and its alloys as the current carrier and the relatively high resistivity of A1. Aluminum's use in two-dimensional networks has thus been considered to be inadequate because of unacceptably high values of the so-called interconnection or R C delay, especially in microprocessors and application-specific integrated circuits (ICs). Here R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the R C delay must be reduced to such a level that the contribution of R C to switching delays (access time) becomes a small fraction of the total, which is the sum of the inherent device delay associated with the semiconductor, device geometry and type and the R C delay.
0040-6090/93/$6.00
One can reduce the R C delay either b y reducing C associated with the dielectric or by reducing R. In this paper we address the latter. R can be reduced by reducing the resistivity p and the length L of the interconnection metal or by increasing the cross-sectional area of the interconnections, with geometry factors also affecting C. Increasing the interconnection area has little appeal, since (a) the area occupied by interconnection lines is already an extremely large fraction of the chip area and (b) the fabrication requirements limit the thickness of the metal. Advanced metallization schemes using so-called multilevel metallization ( M L M ) structures with a low resistivity metal such as Cu have thus been proposed to reduce both p and L. The lowering of L in such schemes is achieved by using vertical interconnections that span short horizontal distances on selected planar levels. Presently copper is being investigated as the interconnection metal. Copper, in spite of its low resistivity, has not found application in silicon ICs because of (a) its high diffusivity and deep levels in silicon, (b) its poor adhesion to SiO2 and (c) its reactivity with the environment [ 1]. In addition, dry etching of copper has proved extremely difficult. All published accounts have shown etching of Cu to be feasible at temperatures of about 250 °C where use of a suitable etch mask is difficult
© 1993-- Elsevier Sequoia. All rights reserved
258
S. P. Murarka et al. / Advanced multilayer metallization schemes
[2-5]. However, one can envision the use of a planarization technique in which inlaid metal interconnections (filling the vias and trenches precut in the dielectric) can be created using the so-called Damascene approach [6, 7]. This technique has recently been employed to build four-level W-A1 interconnection schemes [6, 8-10]. This paper reviews the use of copper as an interconnecfion metal, potential problems and concerns, the results published in the literature and possible solutions and suggestions to implement such a concept of using Cu in an MLM scheme. First a brief discussion of the properties and advantages of copper over other metals is given. This is followed by a discussion of potential problems and concerns. Finally the present state of knowledge is reviewed and potential solutions are considered.
a low resistivity (only about 5% higher than that of Ag), a low AT, ease of deposition, a high thermal conductivity, a lower thermal coefficient of resistance (TCR) than AI and W, a lower thermal expansion coefficient (TEC) than A1, the highest melting point except for W, and a slightly higher thermal stress per kelvin because of its higher Young modulus. It has a lower diffusivity in SiO2 as compared with Ag [ 13]. It will need an adhesion promoter, the development of a process to define the interconnection wiring, and protection against corrosive environments. Gold offers excellent corrosion resistance. However, gold is a major recombination-generation center in silicon, forms a low temperature (about 363 °C) eutectic with silicon and is very difficult to etch in dry ambients. Tungsten has been the choice metal for applications in integrated circuits, more recently as plugs and viafilling metal. Its higher resistivity, however, makes it questionable for planar interconnection applications and even for vias with dimension less than 0.25 grn. Selective tungsten growth by chemical vapor deposition (CVD), if proven reliable, does offer several advantages for the use of tungsten as a direct contact to silicon, but even in such applications the reliability of contacts has to be established. Of the five metals considered in Table 1, aluminum is the only one which meets practically all requirements. Its low melting point, however, raises concerns about (a) its interaction with shallow junctions during contact anneal or subsequent metal processing at temperatures as high as 450 °C and (b) its electromigration stability. Also, the aluminum which is being used today offers a
2. Copper as the interconnection metal
Table 1 compares copper with silver, gold, aluminum and tungsten, all of which have been suggested at one time or another for use as an interconnection metal. Also included are the values of the signal delays, calculated as the R C time constant [11]. The R C values were calculated for a conductor 1 mm long and 0.25 gm thick on an SiO2 plate capacitor 1 gm thick [12]. We have also compared the adiabatic tempeature rise (AT) associated with Joule heating in the conductor due to the passage of 1 A of current. Note that AT is calculated assuming no heat dissipation out of the conductor. Copper offers
TABLE 1. Comparison of properties of possible interlayer metals Property
Resistivity (i~ m) Young modulus x 10 .4 (MPa) TCR x 103 (K -1) Thermal conductivity ( W m - l) TEC x 106 (K -1) Melting point (K) Specific heat capacity (J kg -I K -l) Delay (ps mm -1) Thermal stress on Si (MPa K -l) Corrosion in air Adhesion to SiO2 Deposition Sputtering Evaporation CVD Etching Dry Wet
Metal Cu
Ag
Au
Al
W
0.0167 12.98 4.3 398 17 1358 386 2.2 2.5 Poor Poor
0.0159 8.27 4.1 425 19.1 1235 234 2.2 1.9 Poor Poor
0.0235 7.85 4 315 14.2 1337 132 3.2 1.2 Excellent Poor
0.0266 7.06 4.5 238 23.5 933 917 3.7 2.1 Good Good
0.0565 41.1 4.8 174 4.5 3660 138 7.8 0.8 Good Poor
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S. P. Murarka et al. / Advanced multilayer metallization schemes
3. Deposition of copper films
TABLE 2. Comparison of electromigration parameters a
AI in AI Cu in Cu
259
Z*
D o ( m 2 s -1)
Q (kJ mo1-1)
D (m 2 s-1) (at 100 °C)
~ 3 ~ 1
1.71 × 10 -4 0.78 x 10 -4
142.4 211.5
2 × 10 -24 2 × 10 -34
aMeasured values of Z* are different but are still in approximate ratio of 3:1 for AI to Cu.
resistivity that may not be low enough for ULSI and GSI circuits. Table 2 compares the electromigration-related parameters of A1 and Cu. It is apparent that Cu offers, at least theoretically, electromigration several orders of magnitude lower in bulk or single-crystal materials. Even with grain boundaries, which may dominate the diffusion in small grain polycrystalline copper films, one would expect significantly better electromigration lifetimes in Cu than in A1. Lastly one must mention the effect of metal interactions with silicon even if the metal is used on an insulator and not in direct contact with the silicon. Copper is reported to have acceptor levels in the silicon band gap at 0.24, 0.37 and 0.52 eV with respect to the valence band edge [14]. It also diffuses extremely fast in Si. Thus copper contamination of the active device regions in Si and in the fabrication facility becomes a real concern, since it may lead to unwanted degradation of the devices. As discussed later, the use of copper will be confined to forming interconnections not in direct contact with the silicon. A diffusion barrier-adhesionpromoter will further create isolation for such interconnections, even when used on the contact metal (usually a silicide such as CoSi2 or TiSi2) on silicon. Thus direct contamination of the active device regions is not of primary concern except in cases of uncontrolled processing. Indirect contamination due to etching, planarization and chip edges and back sides could be envisioned. However, such contamination also results from poor process control and diffusion to active device regions, which will occur only after considerable annealing treatment at high temperatures. In our opinion, copper contamination may not be a serious issue, since the industry has been using copperdoped aluminum in devices without any reliability problems related to copper. The first author has monitored deposited polysilicon films (on metal-oxidesemiconductor (MOS) gates) for about 10 years and recorded a copper contamination level of 10201022 m -3, which did not affect the devices. Note that in the latter case the polysilicon on gate oxides is subjected to several high temperature operations (about 1000 °C). After A1-Cu alloy deposition the devices are subjected to a few 400-450 °C anneals.
Recent copper research has focused on deposition employing physical and chemical vapor deposition (PVD and CVD) techniques [15-20] and electrochemical processes [21, 22], which can be electroless. Deposition of copper by evaporation is one of the oldest and easiest methods. More recently the partially ionized beam [23] and ion cluster beam [24] deposition techniques, where vaporized species are ionized by direct bombardment with electrons and then accelerated toward the substrate, have been employed. Both these relatively new techniques produce self-cleaning of the substrate surface, leading to excellent bonding with the substrate. Sputtering (r.f. or d.c.) is an easy PVD method of depositing copper. The sputtering yield of copper is among the highest of all the metals. At 600 V argon ion energy the sputtering yield (atoms of copper sputtered per ion of argon) of copper is reported to be 2.8, compared with 1.2 for AI and 0.6 for W [25]. For via filling and planarization using biased sputtering, such high sputtering yields could be advantageous. Recently there have been several publications on the CVD of copper using various types of copper organometallics, including 13-diketonate complexes of copper. Both Cu ÷ and Cu 2÷ precursors have been tried using either thermal or plasma-assisted CVD. In Cu ÷ precursors the valency of Cu is one, and on heating, a disproportionation reaction occurs leading to a free neutral copper atom and a Cu 2÷ material which vaporizes. Norman et al. [26] used Cu ÷ hexafluoroacetylacetonate trimethylvinylsilane (Cu÷(hfac)TMVS) to deposit copper by the reaction Cu÷(hfac)TMVS(g)
> 130 °C
, Cu°(s) + Cu2÷(hfac)(g) + 2TMVS(g)
(1)
In Cu 2÷ precursors the valency of Cu is two and the decomposition is caused by thermal or plasma effects leading to free copper and other decomposition products which are vapors and are pumped away. The most commonly used precursor is Cu2÷(hfac)2, which has been shown to yield excellent copper films [20]. More recently a new precursor, Cu2+(tdf)2, has been synthesized [27] and shown to have a significantly high vapor pressure, which will yield better deposition rates [27, 28]. The chemical forms and exact nomenclatures of these three precursors and the vapor pressure curves of the two Cu2÷ precursors are shown in Figs. 1 and 2 respectively. At 85 °C Cu 2÷ (tdf)2 has a vapor pressure of about 4kPa, compared with about 0.08 kPa for Cu2+(hfac)2 . The increase in vapor pressure is associated with the heavier fluorinated radicals replacing the lighter radicals, in agreement with the predictions of
S. P. Murarka et al. / Advanced multilayer metallization schemes
260 (a)
CH3
(1) Since a sensitizer is necessary to cause deposition, how are the necessary deposition and patterning of such a metal in vias on an dielectric surfaces to be achieved? (2) What are the contaminants (from the bath) incorporated in deposits and do they affect the properties of copper and its reliability? (3) How will the surfaces of electroless copper be passivated? (4) Will deposition occur reliably in small holes (contacts and vias), since surface tension effects may not permit the bath solution to reach the bottom of the holes? (5) Will an annealing step to optimize the properties of the deposit be required? We conclude that blanket film deposition technologies for copper are now established which can be incorporated depending on the need. However, the selective deposition of copper on desired regions (e.g. a metal or alloy in a window or via) needs significant research and development effort and reliability evaluation.
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Fig. 1. Chemical formulae of the three precursors for CVD: (a) copper hexafluoroacetylacetonate trimethylvinylsilane; (b) Cu(hfac)2 or bis(1,1,1,5,5,5-hexafluoroacetylacetonato) copper(II); (c) Cu(tdf)2 or bis( 1,1,1,2,2,3,3,7,7,8,8,9,9,9-tetradecatluorononane-4,6-dionato) copper(II).
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~
,
>
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I
2.6
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I
2.8 3.0 10 3 / T (K -1 )
I x
3
Fig. 2. Vapor pressure o f (a) Cu(hfac)2 and (b) Cu(tdf) 2 precursors.
Sievers and Sadlowski [29]. Using these precursors and thermal or plasma-assisted CVD, excellent copper films with a resistivity as low as 0.017 la~ m have been deposited on wafers as large as 0.2 m in diameter. Electroless deposition of copper offers a very simple, inexpensive and versatile technique when compatible with ULSI and GSI processing constraints. Electroplating and electroless deposition of copper are well known and several chemical baths and recipes are available [30]. Attempts are being made to utilize this technology to deposit metal selectively in contact holes [21, 22]. However, several key questions remain to be answered.
4. Patterning of copper interconnections The conventional approach to pattern generation is to reactively ion etch the material off the surfaces not protected by a photoresist mask. The use of such dry etching processes for Cu has been difficult owing to the lack of volatile copper species at temperatures relatively close to room temperature where the photoresist masks retain the geometrical shape. In spite of these difficulties, several attempts have been made to dry etch copper [2-5]. In all cases a special mask material such as amorphous carbon or a polyimide was first patterned using a photoresist. Such masks were then employed to generate patterns in copper films. Chlorine-containing s p e c i e s ( C C 1 4 , CC12F2, C12, SIC14 and BCI3 in argon or nitrogen) and substrate temperatures as high as 250 °C were employed in a reactive ion etch mode [2-5]. These results indicate that etching of copper at temperatures of 250 °C and above is possible. However, such high temperature processes are not very attractive because of the need for a useful and reliable mask material which remains stable during actual etching. Also, copper migration under plasma-induced biases and high temperatures is a serious concern. One can envisage the use of wet chemical etching of copper, which etches readily in a variety of chemicals. However, such etches are isotropic and would be limited to wider interconnection lines where undercutting due to isotopic etching can be tolerated and compensated in the mask definition. One can envision such etchings at upper-level multilevel interconnections. While wet etching of copper may find initial application in such cases, the widespread use of copper interconnect technology requires high aspect ratio patterning.
S. P. Murarka et al. / Advanced multilayer metallization schemes
(b)
si 0 2
Fig. 3. Concept of chemical-mechanical polishing used to generate inlaid Cu interconnections (vertical and horizontal as required) in SiO2: (a) schematic view of as-deposited Cu; (b) after CMP.
The Damascene process to generate inlaid copper interconnections [7] can be used to achieve such patternings. The concept is shown schematically in Fig. 3. The desired trenches and vias are etched in SiO2 by conventional reactive ion etching (RIE). The diffusion barrier-adhesion promoter followed by a thick layer of copper is deposited, leading to the cross-sectional view in Fig. 3(a). This structure is then chemically-mechanically polished, ending with the structure shown in Fig. 3(b). One can stop at the Ti layer as shown or continue to the SiO2 dielectric surface. Not only is a planarized surface achieved, but also the copper in vias or trenches is encapsulated by the diffusion barrier-adhesion promoter on all surfaces except the polished surface. Thus the need for etching the copper and diffusion barrieradhesion promoter is circumvented. The chemical-mechanical polishing (CMP) process consists essentially of two components: mechanical grinding and chemical etching. Suspended particles in the slurry impinge on the surface and cause dislocation and strain within it, sometimes even dislodging atoms or atom clusters from the surface. Chemicals in the slurry react with the dislodged materials (increased surface area) or the strained surface layers at accelerated rates and remove such material into the slurry. Chemicals could also play an important secondary role of passivating the surface being polished until mechanical grinding removes the passivated layer. The latter mechanism helps in reducing the topography on the surface [10]. The chemical phenomena occur at the metal surface, at the pad and at the slurry particle surface, leading to metal dissolution in the slurry removed. The mechanical phenomena also occur at the same surfaces and affect the physical shape of the grinding particles and the pad. The mechanical effects of the CMP process are controlled by physical parame-
261
ters such as pressure, pad velocity, sample rotation, area dependence, possible influences on the chemical activities and damage, and pad-related parameters such as pad type, pad reconditioning, slurry type, slurry particle size and possible influences on the chemical activities. The chemical effects of the process are related to material etch rate, slurry pH, oxidationreduction potential, selectivity to dielectric and barrier layer, effects on pad or machine, post-polishing residue removal, optimization of the abrasive and chemical combination, localized temperature, stress effects on chemical reactions, localized changes in the concentration of chemicals, and effects of increasing concentration of metal in the slurry. Since metals are generally softer and more ductile than glass or semiconductors whose surfaces are also prepared by use of this technique, it is more critical to strike an appropriate balance between the chemical and mechanical components of the polishing process through proper control of the numerous process variables described above. The polishing kinetics is generally given in terms of Preston's equation [31] AH L As At = Kp A At
(2)
where AH/At is the removal rate of the material in terms of change in height per unit time of polishing, L is the load imposed over a surface area A, As[At is the relative velocity of the pad to the sample and Kp is Preston's coefficient, which is weakly variable. The equation predicts that for a given L/A the weight loss of the polished material is proportional to the amount of travel and remains invariant with time. The polishing rate increases with increasing pressure (L/A) and velocity. One of the important implications of the above equation is that the removal rate is independent of the abrasive particle size in the slurry. Since Preston's equation is basically a mechanical model for the removal rate by a CMP process, the validity for CMP of copper and the variation in Kp with processing conditions need to be established. For the copper CMP Damascene process we have focused on developing a global planarization process to obtain a high selectivity of polishing rate between copper and the underlying diffusion barrier-adhesion promoter or dielectric. The four phenomena that determine the usefulness of a CMP process, namely nonuniformity, rounding, dishing and erosion [8-10], are being addressed. Copper is a relatively soft material and residual scratches that may result from mechanical grinding are of concern as well. Finally the post-planarization cleaning and passivation are being addressed so that a complete sequence of processes can be outlined to implement a Cu Damascene CMP process.
S. P. Murarka et al. / Advanced multilayer metallization schemes
262
Our initial findings [7] have successfully demonstrated the patterning of copper lines using this chemical-mechanical polish. Both narrow (1.0 ~tm) lines and large (100 ttrn x 100 ttm) bonding pads within close proximity of each other have been defined. Figure 4 shows a scanning electron microscopy (SEM) image of 1.5 and 1.0 lam lines recessed into trenches 1.5 ttm deep. Figure 5 shows an optical micrograph of various patterns. Clearly it is possible to use a CMP process to define copper structures of all dimensions. Considerably more research and development effort is needed to make the process reliable and manufacturable.
5. Diffusion of Cu in SiO2-based dielectrics and silicides Fig. 4. SEM cross-sections of copper interconnections after CMP. Samples were cleaved to show the depth.
McBrayer et al. [ 13] examined the diffusion of Cu in SiO 2 films and reported noticeable diffusion in SiO2, especially after Cu-on-SiOz samples were biased at temperatures as high as 400 °C. We have also examined the thermal diffusion and electrical-bias-aided diffusion of Cu in SiOz [32, 33]. Table 3 summarizes qualitatively the interactions of copper films on phosphorus (about 7wt.%) glass (PG), undoped oxide deposited using tetraethoxyorthosilicate as precursor (TEOS) and thermal oxide (SiO2) on annealing in argon and A r 3 v o l . % H z. Several conclusions can be made. (I) Copper interacts (diffuses) in PG more readily than in undoped oxides, indicating the possibility of phosphorus get tering of copper. (2) Copper was oxidized in the absence of hydrogen, possibly owing to the presence of contamination and oxidizing species in argon. (3) Even when oxidation of copper occurred, detectable amounts of Cu diffused in all oxides at temperatures in the range 300-400 °C for 30 min anneals. (4) Hydrogen present
Fig. 5. Optical micrograph o f copper interconnections and pads generated by CMP.
T A B L E 3. Interactions of copper with phosphorus glass, TEOS and thermal oxide Annealing gas
Sample
200 °C
300 °C
400 °C
500 °C
Ar
Cu - P G
__ a
Noticeable diffusion
Cu-TEOS
.
Considerable diffusion Diffusion
Cu-SiO 2 (thermal)
--a
--~
Significant diffusion Noticeable diffusion Significant diffusion
Cu-PG
a
Noticeable diffusion
Diffusion
Cu-TEOS
--~
Noticeable diffusion . . .
Cu_SiO 2 (thermal)
a
__a
Ar + 3% H 2
aNo detectable interaction or change observed.
.
.
.
.
__a
Diffusion
Possibly a hint of diffusion Some diffusion
S. P. Murarka et aL/ Advanced multilayer metallization schemes
in the annealing environment suppressed both the oxidation of copper and its diffusion in undoped oxides, leading to at least a 100 °C increase in temperature, at which detectable amounts of copper were seen after a 30 min anneal. Also investigated were (a) the metaloxide-semiconductor (MOS) characteristics of C u SiO2-p-Si MOS capacitors after annealing at various temperatures and (b) the minority carrier lifetime in silicon after diffusion anneals of Cu-100 nm SiO2-Si samples [34]. The results indicate that there is no measurable effect of Cu (if any) in SiO2 at temperatures below 500 °C in hydrogen-containing ambients. However, when the MOS capacitors were annealed under a bias of 150 M V m -1 (up to temperatures of 300 °C), copper did diffuse in SiO2, affecting its electrical properties [33, 35]. These results are in agreement with the findings of McBrayer et al. [ 13] and ShachamDiamond et al. [36] and thus clearly show that a diffusion barrier that will stop bias-induced Cu migration is necessary. The results of Table 3 also show that (a) when annealed in argon, the diffusion barrier effectiveness of SiO2 is reduced to temperatures lower than 400 °C and (b) phosphorus glass is not a suitable barrier even at 300 °C in pure argon or Ar-H2 ambients. Copper diffusion in silicides which may form electrical contacts to silicon or polysilicon has also been investigated. CoSi2 and TiSiz are two self-aligned silicides that are being used for such applications. Thermal diffusion studies of Cu on these silicides show no observable Cu migration, at least up to 500 °C for anneals up to 30 min [37, 38]. In the case of Cu on CoSi2, the stability of Schottky diodes formed on n-Si was also examined as a function of the annealing temperature. The results of these measurements and Rutherfordbackscattering spectroscopy (RBS) analyses indicate that Cu on CoSi2-Si is stable for at least up to 30 min at 600 °C when annealed in Ar-H2 ambients.
6. Adhesion promoter and diffusion barrier Copper will not reduce S i O 2 and is therefore expected not to adhere well to SiO2 surfaces. Copper films sputtered in commercial equipment that pumps down to about 10-5 Pa pressure prior to sputtering show reasonable adhesion to both SiO2 and polymer films. Most of them pass the Scotch tape peel test in the as-deposited condition but peel off on heating to higher temperatures (and cooling). The latter effect is related to thermal stress generated by the difference in thermal expansion coefficients of SiO2 and Cu. Similar adhesion failures are observed for evaporated films. However, recently reported results for copper films sputtered under very high purity conditions in equipment pumped down to 10-6-10 -7 Pa on oxides that have been heated to des-
263
orb water molecules off the surface show that such films adhere extremely well to SiO2 surfaces [15, 16]. Copper films deposited on polymers by the partially ionized beam technique also show excellent adhesion [23]. Similar results of copper adhesion on Teflon surfaces were reported for films deposited by the ionized cluster beam method [24]. These dearly indicate that copper will pass adherence requirements when deposited on clean and moisture-free surfaces. Of the various techniques used to enhance the adhesion between the dielectric (SiO2 or polymer) and copper, three seem most attractive: (a) use of adhesion promoters; (b) increased temperature of deposition or providing energy to ionize (depositing) species; (c) surface pretreatment, especially plasma oxidation of polymers, sputter damage of metal surfaces or use of ion implantation near the polymer or metal surface. We are concerned with the use of adhesion promoters which could also act as diffusion barriers at higher process temperatures. Adhesion promoters must form excellent bonding with both the dielectric and the metal. In addition, they should not allow the diffusion of metal atoms in the dielectric. Titanium, T i - W and TiN have been most frequently used because of titanium's excellent chemical reactivity with oxygen, carbon, nitrogen, fluorine, etc. Recent results indicate that copper interacts with all of them at temperatures as low as 300 °C when annealed in an inert or vacuum ambient. However, when annealed in ambients containing hydrogen, pure titanium forms a hydride and the T i - C u structure is stable to 400-450 °C. The hydride passivates the fast diffusive paths and the interface between metals and inhibits interdiffusion at low temperatures. Other adhesion promoters that are being investigated presently are Cr, Ta, A1 and Mg. The ultimate objective of finding a diffusion barrier that will also perform as an adhesion promoter between Cu and the insulator (SiO2 or polymer) is to identify an electrically stable Cu-diffusion barrier-insulator or Cu-diffusion barrier-contact silicide system. Thus with the advent of sub-0.25 Ixm geometries, where the thickness of the barrier-adhesion layer may shrink to less than 10 nm and the metallurgical stability may not be guaranteed, one must look for an electrically stable and reliable barrier layer that may or may not be metallurgically sacrificial. An investigation of thin A1 films as an adhesion promoter-diffusion barrier between copper and SiO2 has been carried out [39]. MOS capacitors of (A) pure Cu on SiO2, (B) pure A1 on SiO2 and (C) Cu-A1 on SiO2 were subjected to thermal annealing and bias-temperature-stress (BTS) aging. Both metallurgical and electrical stabilities were investigated. It was found that although aluminum reacted readily with copper, its presence between SiO2 and Cu provided the
S. P. Murarka et al. / Advanced multilayer metallization schemes
264
1.0
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O
N
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Z
Z
®
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@ BTS (250"C. 5 MIN) ~ ) 8TS (250°C. ~0 MIN) ~'0
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Bias (V)
Fig. 6. C - V characteristics of 130 nm SIO2-500 nm Cu MOS capacitor sample electrically (about 1 5 0 M V m -t) stressed at 250 °C for various times.
required electrical stability. For all samples the asdeposited C - V plots show flat-band voltages near - 1 0 V due to processing-induced interface states. After a 5 rain anneal at 250 °C the effect o f these states is eliminated and flat-band voltages between - 2 and - 3 V are achieved for all samples. These curves are then used as the "zero point" for all comparisons to determine any metal impurity movement into the silicon. Sample A with 500 nm of copper directly on SiO2 starts to show movement of the flat-band voltage after 30 min of BTS aging at 250 °C. After 1 h, the curve moves down even further and shows a change in curve shape reminiscent of a possible increase in dopant concentration (Fig. 6). This change is due to copper permeating the S i O 2 , perhaps distributing itself across the oxide and entering the silicon substrate [40]. By contrast, sample B with only 500 nm of aluminum on oxide shows no movement under the same BTS conditions and exposure times (Fig. 7). Both these results confirm published data that have led to the maturation of aluminum technology and the abandonment of copper in VLSI fabrication. These samples were used as controls for the results from those of type C (50 nm A1 on 500 nm Cu). According to the C - V plots presented in Fig. 8, the A1-Cu bilayers show characteristics identical to those of aluminum under the given conditions. There is no net movement of the flat-band voltage or shape change after the BTS anneals. The obvious conclusion is that there is no net movement of electrically active species from copper into the oxide or to the Si-SiO2 interface; thus aluminum, which may have oxidized at the SiO2-AI interface, is acting as an effective diffusion barrier. These results support the known electrical stability of A I - C u alloys used as interconnections on and between SiO2 layers.
.io
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Fig. 7. C - V characteristics o f 130 nm SiO 2 -500 nm AI MOS capacitor sample electrically (about 150 MV m -1) stressed at 250 °C for various times.
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Bias (V)
Fig. 8. C - V characteristics of 130 nm SIO2-50 nm AI-500 nm Cu MOS capacitor sample electrically (about 1 5 0 M V m - t ) stressed at 250 °C for various times.
We believe that for ULSI and GSI devices such electrically stable barriers of thickness less than 100/~ are necessary. In this respect A1 is better, since it is known to form a self-limiting A l - o x i d e (or A 1 - O x Siy) layer at the interface. On the other hand, in a similar use Ti is known to consume SiO2 on continued annealing [41] and may thus be harmful if the gate sidewall oxide thickness is small (less than 10 nm). Also, dissolved AI in Cu increases the resistivity by only about 0 . 0 1 ~ m a t . % -1 A1 in Cu, which can be compared with about 0.110.161 ~ Q m a t . % - ~ T i in Cu. Mg is another possible barrier element which when dissolved in Cu changes its resistivity by less than 0.01 laf~mat.% -1 Mg in Cu [11].
S. P. Murarka et al. / Advanced multilayer metallization schemes
7. Passivation of Cu surfaces exposed to dielectric deposition or atmosphere
Passivation o f copper surfaces is of utmost importance to make copper interconnection technology become manufacturable and not just a research curiosity. As discussed above, copper surfaces do not bond with SiO: and copper diffuses into SiO: under electrical bias, affecting the electrical properties of the dielectric. Also, copper corrodes readily in ambients containing oxidizing agents and sulphur. Thus etched or polished copper surfaces must be passivated to prevent interactions with SiO2 and the environment. Ideally one would like to passivate all exposed surfaces in one treatment. Such treatments would include dipping in liquid or gaseous surrounds. Cabrera et aL [42] and Hymes et al. [43] have exposed copper surfaces to silane in the temperature range 300-400 °C to form a silicided surface. Figure 9 shows the sheet resistance ratio (post-oxidation anneal/ pre-anneal after silicide is formed for the anneals of 10 min in silane) as a function of time and temperature of oxidation in air. It is clearly demonstrated that the silicided surfaces provided corrosion protection in air even at 350 and 400 °C.
4.00 350°C/10 min/Silone .0 rr
3.50 3.00
"i 2.50 112 ~ 2.00
265
Ding et al. [44] have shown that implanted b o r o n and aluminum passivate copper surfaces. Boron in concentrations as low as 0.01% is known to provide corrosion resistance to copper [45]. It is also a common ion implantation species used to provide a p-type doping profile in Si. SiO2 films are used as masks to prevent implantation and diffusion in undesirable regions of Si. Thus boron implantation is a natural choice to provide passivation of copper surfaces. If copper interconnections are defined using the Damascene (CMP) approach described earlier, the implantation of exposed copper surfaces provides the necessary passivation without affecting the surrounding oxide surfaces. However, this technique leads to a gaussian depth profile of boron in copper, leaving the top layers of the metal with depleted or zero boron concentration. Such surfaces oxidize until the boron-rich regions (deeper in the metal) are met by the oxidized layers. Oxidation then stops. Thus a process is needed to place boron directly on the surface of copper. It may be pointed out that a considerable amount of research is needed to establish the usefulness of silicide or boron passivation process. Also, the electrical and mechanical stabilities of these passivated surfaces when in contact with the top insulating layers must be established. Passivation of copper can also be achieved by alloying the top layers. Li et al. [46] have shown that the compounds Cu3Ti, Cu3Pd and CuAI: are stable in ozidizing ambients. However, alloying surfaces of copper selectively is difficult if not impossible and use of these alloys to replace copper is self-defeating because of the very high resistivities.
g 1.50 1.00-0
8. Conclusions 5
10
(a)
15
20
25
30
T i m e (min)
5.5 o
5
325°C/10 min/Silane
4.5
~c 4 -~ -3.5
~ 3 ~ 2.5
g~ 2 1.5 --300
(b)
m 350
400
450
500
550
T e m p e r a t u r e (°C)
Fig. 9. (a) Sheet resistanceratio Rs(post-anneal)/Rs(pre-anneal ) as a function of annealing time for 400, 450 and 500 °C anneals in air after 350 °C, 10 min silane exposure to form copper silicide on surface. (b) Sheet resistanceratio Rs(post-anneal)/Rs(pre-anneal ) as a function of annealing temperature for 5, 10 and 20rain anneals in air after 325 °C, 10 min silane exposure to form copper silicide on surface.
This paper has reviewed the present state of knowledge regarding the use of copper in a multilevel scheme. To create an M L M structure, the following scheme appears to be attractive, although a considerable amount of research is needed to prove its viability and reliability. (1) Etch vias and trenches in a planarized dielectric to form vertical and horizontal interconnections. (2) Deposit 10 nm or less of AI or Ti by CVD or deposit 10 nm or less of AI or Ti by sputtering followed by a thin (about 10-50 nm) layer of copper. (3) Deposit required thickness of copper by CVD. Note that excess copper thickness is needed so that C M P can be used to planarize and form buried interconnections in oxide. (4) Chemically-mechanically polish copper (ending up with interconnections as shown in Fig. 3) and stop at A1 or Ti or at SiO2 surface. If stopped at AI or Ti,
266
S. P. Murarka et al. / Advanced multilayer metallization schemes
chemically etch A1 or Ti selectively without etching copper or its protection on sidewalls. Clean. (5) Passivate copper surface using silane or boron implantation. (6) Deposit new layer of insulator for next level and follow steps (1) -(5). The above sequence of process steps is possible and available information presented in this paper points to this effect.
Acknowledgments The authors would like to thank Sematech, SRC, Intel, IBM, Motorola, Watkins-Johnson and MKS Instruments for their support of this investigation on copper MLM technology and for the results presented here.
References 1 S. P. Murarka, in G. C. Smith and R. Blumenthal (eds.), Tungsten and Other Advanced Metals for VLSI Applications in1990, Materials Research Society, Pittsburgh, PA, 1991, p. 179. 2 G. C. Schwartz and P. M. Schaible, J. Electrochem. Soc., 130 (1983) 1777. 3 B. J. Howard and C. Steinbruchel, Appl. Phys. Lett., 59 (1991) 914. 4 B. J. Howard, S. K. Wolterman and C. Steinbruchel, M R S Syrup. Proc., 201 (1991) 129. 5 B. J. Howard and C. Steinbruchel, Proc. Conf. on Advanced Metallization for VLSI Applications, Tempe, AZ, October 1992, MRS, Pittsburgh, PA, 1993, p. 391. 6 R. R. Uttecht and R. Geffken, Proc. 8th VLS1 Multilevel InterConnection Conf., IEEE, New York, 1991, p. 20. 7 S. P. Murarka, J. Steigerwald and R. J. Gutmann, MRS Bull., XVIII (1993) 46. 8 C. W. Kaanta, W. J. Cote, J. E. Cronin, J. S. Landis, W. Hill and G. J. Ryan, Proc. 8th VLSI Multilevel Interconnection Conf., IEEE, New York, 1991, p. 144. 9 W. J. Patrick, W. L. Guthrie, C. L. Standley and P. M. Schiable, J. Electrochem. Soc., 138 (1991) 1778. 10 F. B. Kaufman, D. B. Thompson, R. E. Broadie, M. A. Jaso, W. L. Guthrie, D. J. Pearson and M. B. Small, J. Electrochem. Soc., 138 (1991) 460. 11 S. P. Murarka, in Metallization- Theory and Practice for VLSI and ULSI, Butterworths, Boston, MA, 1992. 12 S. M. Sze, personal communication, 1984. 13 J. D. McBrayer, R. M. Swanson and T. W. Sigmon, J. Electrochem. Soc., 133 (1986) 1243. 14 A. G. Milnes, Deep Impurities in Semiconductors, Wiley, New York, 1973. 15 T. Saito, T. Ohmi, T. Shibata, M. Otsuki and T. Nitta, Extended Abstracts 21st Conf. on Solid State Devices and Materials, Tokyo, 1989, p. 25. 16 T. Ohmi, T. Saito, M. Otsuki, T. Shibata and T. Nitta, J. Electrochem. Soc., 138 (1991) 1089.
17 C. Oehr and H. Suhr, Appl. Phys. A, 45 (1988) 151. 18 P. M. Jeffries and G. S. Girolami, Chem. Mater., I (1989) 8. 19 D. Temple and A. Reisman, J. Electrochem. Soc., 136 (1989) 3525. 20 A. E. Kaloyeros, A. Feng, J. Garhart, S. Ghosh, A. Saxena and F. Leuhrs, J. Electron. Mater., 19 (1990) 271. 21 C. H. Ting, in M. Paunovic and I. Ohno (eds.), Proc. Symp. on Electroless Deposition of Metals and Alloys, Proc. Vol. 88-12, Electrochemical Societies, Pennington, NJ, 1988, p. 223. 22 S. S. Wong, in P. W. J. Verhofstadt (ed.), SRC Topical Research Conf. on Interconnects, SRC Publ. P90007, SRC, Research Triangle Park, NC, 1990, p. 45. 23 P. Bai, G-R. Yang and T.-M. Lu, Appl. Phys. Lett., 56 (1990) 198. 24 T. Takagi, M R S Syrup. Proc., 27 (1984) 501. 25 L. I. Maissel and R. Glang (eds.), Handbook of Thin Film Technology, McGraw-Hill, New York, 1970. 26 A. T. Norman, A. Hochberg, C. A. Roberts, P. N. Dyer and B. A. Muratore, Proc. 8th VLSI Multilevel Interconnection Conf., IEEE, New York, 1991, p. 123. 27 P. J. Toscano, C. Dettelbacher, J. Waechter, N. P. Pavri, E. T. Eisenbraun, B. Zheng and A. E. Kaloyeros, J. Am. Chem. Soc., to be published. 28 E. T. Eisenbraun, B. Zheng, P. J. Toscano, D. Dettelbacher, N. P. Pavri, S. P. Murarka, M. A. Fury and A. E. Kaloyeros, Chem. Mater., in press. 29 R. S. Sievers and J. E. Sadlowski, Science, 201 (1989) 217. 30 E. A. Brandes and G. B. Brook (eds.), Smithels Metals Reference Book, Butterworths, Boston, MA, 7th edn., 1992. 31 L. Cook. J. Non-Cryst. Solids, 120 (1990) 460. 32 B. Arcot, Y. T. Shy, S. P. Murarka, C. Shepard and W. A. Lanford, M R S Symp. Proc., 203 (1991) 27. 33 Y.-T. Shy, Ph.D. Thesis, Rensselaer Polytechnic Institute, Troy, NY, 1993. 34 Y.-T. Shy, S. P. Murarka, K. Singh, J. G. Bhimnathwala and J. M. Borrego, Conf. Proc. UISI--VII, Materials Research Society, Pittsburg, PA, 1992, p. 433. 35 R. Nandan, S. P. Murarka, A. Pant, C. Shepard and W. A. Lanford, MRS Symp. Proc., 260 (1992) 929. 36 Y. Shacham-Diamond, D. Hoffstetter, J. Li and W. G. Oldham, Proc. SRC Techcon '90, SRC, Research Triangle Park, NC, 1990, p. 239. 37 Y.-T. Shy, S. P. Murarka, C. L. Shepard and W. A. Lanford, MRS Symp. Proc., 181 (1990) 537. 38 Y.-T. Shy, S. P. Murarka, A. R. Sitaram, P.-J. Ding and W. A. Lanford, MRS Symp. Proc., 260 (1992) 151. 39 R. Nandan, M.S. Thesis, Rensselaer Polytechnic Institute, Troy, NY, 1992. 40 N. N. Zemel (ed.), Non-destructive Evaluation of Semiconductor Materials and Devices, Plenum, New York, 1979, pp. 169-187. 41 S.-H. Ko, N. M. Devashrayee, S. P. Murarka, P. J. Ding and W. A. Lanford, M R S Symp. Proc., 260 (1992) 665. 42 A. L. Cabrera, J. F. Kirner and J. N. Armor, J. Mater. Res., 6 (1990) 71. 43 S. Hymes, S. P. Murarka, C. Shepard and W. A. Lanford, J. Appl. Phys., 71 (1992) 4623. 44 P. J. Ding, W. A. Lanford, S. Hymes and S. P. Murarka, M R S Symp. Proc., 260 (1992) 757. 45 Boron Deoxidized Copper 1170, Publ. TP-58, AnacondaAmerican Brass Co., 2nd edn., 1967. 46 J. Li, J. W. Mayer and E. G. Colgan, J. Appl. Phys., 70 (1991) 2820.
257
Advanced multilayer metallization schemes with copper as interconnection metal S. P. M u r a r k a
a n d R . J. G u t m a n n
Rensselaer Polytechnic Institute, Troy, N Y 12180 (USA)
A . E. K a l o y e r o s
and W. A. Lanford
University at Albany, Albany, N Y 12222 (USA)
Abstract Advanced metallization schemes are needed to take advantage of the miniaturization of microelectronic devices which are performing at increasingly high speeds. The demands on metallization center around (a) the increased resistance with lower cross-sectional areas and longer interconnect lengths and (b) stability with the surroundings during processing and use under high current densities and thin film stresses. A threefold attack is being pursued to solve these problems, which also duplicate the issues in packaging of these fast chips with large numbers of inputs and outputs: first is to make use of copper as the interconnection metal; second is to use a multilevel metallization scheme; finally there is a need for a low dielectric constant dielectric. In this paper we present a review of progress made in addressing the first two schemes together with a brief discussion of the third. Copper, a heretofore undesired metal in silicon integrated circuits, seems to show promise, with appropriate processing constraints, of fulfilling the projected needs of ultra-large-scale and giga-scale integration and perhaps even of packaging.
I. Introduction Continuing advances in the fields of very-large-scale integration (VLSI), ultra-large-scale integration (ULSI) and giga-scale integration (GSI), leading to the progressive development of smaller and smaller devices, have continually challenged the fields o f materials, processes and circuit designs. The existing metallization schemes for ohmic contacts, gate metal and interconnections are found to be inadequate for the ULSI and GSI era. Added to these concerns are the reliability of aluminum and its alloys as the current carrier and the relatively high resistivity of A1. Aluminum's use in two-dimensional networks has thus been considered to be inadequate because of unacceptably high values of the so-called interconnection or R C delay, especially in microprocessors and application-specific integrated circuits (ICs). Here R refers to the resistance of the interconnection and C to the total capacitance associated with the interlayer dielectric. For the fastest devices currently available and faster ones of the future, the R C delay must be reduced to such a level that the contribution of R C to switching delays (access time) becomes a small fraction of the total, which is the sum of the inherent device delay associated with the semiconductor, device geometry and type and the R C delay.
0040-6090/93/$6.00
One can reduce the R C delay either b y reducing C associated with the dielectric or by reducing R. In this paper we address the latter. R can be reduced by reducing the resistivity p and the length L of the interconnection metal or by increasing the cross-sectional area of the interconnections, with geometry factors also affecting C. Increasing the interconnection area has little appeal, since (a) the area occupied by interconnection lines is already an extremely large fraction of the chip area and (b) the fabrication requirements limit the thickness of the metal. Advanced metallization schemes using so-called multilevel metallization ( M L M ) structures with a low resistivity metal such as Cu have thus been proposed to reduce both p and L. The lowering of L in such schemes is achieved by using vertical interconnections that span short horizontal distances on selected planar levels. Presently copper is being investigated as the interconnection metal. Copper, in spite of its low resistivity, has not found application in silicon ICs because of (a) its high diffusivity and deep levels in silicon, (b) its poor adhesion to SiO2 and (c) its reactivity with the environment [ 1]. In addition, dry etching of copper has proved extremely difficult. All published accounts have shown etching of Cu to be feasible at temperatures of about 250 °C where use of a suitable etch mask is difficult
© 1993-- Elsevier Sequoia. All rights reserved
258
S. P. Murarka et al. / Advanced multilayer metallization schemes
[2-5]. However, one can envision the use of a planarization technique in which inlaid metal interconnections (filling the vias and trenches precut in the dielectric) can be created using the so-called Damascene approach [6, 7]. This technique has recently been employed to build four-level W-A1 interconnection schemes [6, 8-10]. This paper reviews the use of copper as an interconnecfion metal, potential problems and concerns, the results published in the literature and possible solutions and suggestions to implement such a concept of using Cu in an MLM scheme. First a brief discussion of the properties and advantages of copper over other metals is given. This is followed by a discussion of potential problems and concerns. Finally the present state of knowledge is reviewed and potential solutions are considered.
a low resistivity (only about 5% higher than that of Ag), a low AT, ease of deposition, a high thermal conductivity, a lower thermal coefficient of resistance (TCR) than AI and W, a lower thermal expansion coefficient (TEC) than A1, the highest melting point except for W, and a slightly higher thermal stress per kelvin because of its higher Young modulus. It has a lower diffusivity in SiO2 as compared with Ag [ 13]. It will need an adhesion promoter, the development of a process to define the interconnection wiring, and protection against corrosive environments. Gold offers excellent corrosion resistance. However, gold is a major recombination-generation center in silicon, forms a low temperature (about 363 °C) eutectic with silicon and is very difficult to etch in dry ambients. Tungsten has been the choice metal for applications in integrated circuits, more recently as plugs and viafilling metal. Its higher resistivity, however, makes it questionable for planar interconnection applications and even for vias with dimension less than 0.25 grn. Selective tungsten growth by chemical vapor deposition (CVD), if proven reliable, does offer several advantages for the use of tungsten as a direct contact to silicon, but even in such applications the reliability of contacts has to be established. Of the five metals considered in Table 1, aluminum is the only one which meets practically all requirements. Its low melting point, however, raises concerns about (a) its interaction with shallow junctions during contact anneal or subsequent metal processing at temperatures as high as 450 °C and (b) its electromigration stability. Also, the aluminum which is being used today offers a
2. Copper as the interconnection metal
Table 1 compares copper with silver, gold, aluminum and tungsten, all of which have been suggested at one time or another for use as an interconnection metal. Also included are the values of the signal delays, calculated as the R C time constant [11]. The R C values were calculated for a conductor 1 mm long and 0.25 gm thick on an SiO2 plate capacitor 1 gm thick [12]. We have also compared the adiabatic tempeature rise (AT) associated with Joule heating in the conductor due to the passage of 1 A of current. Note that AT is calculated assuming no heat dissipation out of the conductor. Copper offers
TABLE 1. Comparison of properties of possible interlayer metals Property
Resistivity (i~ m) Young modulus x 10 .4 (MPa) TCR x 103 (K -1) Thermal conductivity ( W m - l) TEC x 106 (K -1) Melting point (K) Specific heat capacity (J kg -I K -l) Delay (ps mm -1) Thermal stress on Si (MPa K -l) Corrosion in air Adhesion to SiO2 Deposition Sputtering Evaporation CVD Etching Dry Wet
Metal Cu
Ag
Au
Al
W
0.0167 12.98 4.3 398 17 1358 386 2.2 2.5 Poor Poor
0.0159 8.27 4.1 425 19.1 1235 234 2.2 1.9 Poor Poor
0.0235 7.85 4 315 14.2 1337 132 3.2 1.2 Excellent Poor
0.0266 7.06 4.5 238 23.5 933 917 3.7 2.1 Good Good
0.0565 41.1 4.8 174 4.5 3660 138 7.8 0.8 Good Poor
,/ ,/' ,/
J ,/ ?
J J ?
J ,/ V?
J J V
? J
? J
? J
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,/ J
S. P. Murarka et al. / Advanced multilayer metallization schemes
3. Deposition of copper films
TABLE 2. Comparison of electromigration parameters a
AI in AI Cu in Cu
259
Z*
D o ( m 2 s -1)
Q (kJ mo1-1)
D (m 2 s-1) (at 100 °C)
~ 3 ~ 1
1.71 × 10 -4 0.78 x 10 -4
142.4 211.5
2 × 10 -24 2 × 10 -34
aMeasured values of Z* are different but are still in approximate ratio of 3:1 for AI to Cu.
resistivity that may not be low enough for ULSI and GSI circuits. Table 2 compares the electromigration-related parameters of A1 and Cu. It is apparent that Cu offers, at least theoretically, electromigration several orders of magnitude lower in bulk or single-crystal materials. Even with grain boundaries, which may dominate the diffusion in small grain polycrystalline copper films, one would expect significantly better electromigration lifetimes in Cu than in A1. Lastly one must mention the effect of metal interactions with silicon even if the metal is used on an insulator and not in direct contact with the silicon. Copper is reported to have acceptor levels in the silicon band gap at 0.24, 0.37 and 0.52 eV with respect to the valence band edge [14]. It also diffuses extremely fast in Si. Thus copper contamination of the active device regions in Si and in the fabrication facility becomes a real concern, since it may lead to unwanted degradation of the devices. As discussed later, the use of copper will be confined to forming interconnections not in direct contact with the silicon. A diffusion barrier-adhesionpromoter will further create isolation for such interconnections, even when used on the contact metal (usually a silicide such as CoSi2 or TiSi2) on silicon. Thus direct contamination of the active device regions is not of primary concern except in cases of uncontrolled processing. Indirect contamination due to etching, planarization and chip edges and back sides could be envisioned. However, such contamination also results from poor process control and diffusion to active device regions, which will occur only after considerable annealing treatment at high temperatures. In our opinion, copper contamination may not be a serious issue, since the industry has been using copperdoped aluminum in devices without any reliability problems related to copper. The first author has monitored deposited polysilicon films (on metal-oxidesemiconductor (MOS) gates) for about 10 years and recorded a copper contamination level of 10201022 m -3, which did not affect the devices. Note that in the latter case the polysilicon on gate oxides is subjected to several high temperature operations (about 1000 °C). After A1-Cu alloy deposition the devices are subjected to a few 400-450 °C anneals.
Recent copper research has focused on deposition employing physical and chemical vapor deposition (PVD and CVD) techniques [15-20] and electrochemical processes [21, 22], which can be electroless. Deposition of copper by evaporation is one of the oldest and easiest methods. More recently the partially ionized beam [23] and ion cluster beam [24] deposition techniques, where vaporized species are ionized by direct bombardment with electrons and then accelerated toward the substrate, have been employed. Both these relatively new techniques produce self-cleaning of the substrate surface, leading to excellent bonding with the substrate. Sputtering (r.f. or d.c.) is an easy PVD method of depositing copper. The sputtering yield of copper is among the highest of all the metals. At 600 V argon ion energy the sputtering yield (atoms of copper sputtered per ion of argon) of copper is reported to be 2.8, compared with 1.2 for AI and 0.6 for W [25]. For via filling and planarization using biased sputtering, such high sputtering yields could be advantageous. Recently there have been several publications on the CVD of copper using various types of copper organometallics, including 13-diketonate complexes of copper. Both Cu ÷ and Cu 2÷ precursors have been tried using either thermal or plasma-assisted CVD. In Cu ÷ precursors the valency of Cu is one, and on heating, a disproportionation reaction occurs leading to a free neutral copper atom and a Cu 2÷ material which vaporizes. Norman et al. [26] used Cu ÷ hexafluoroacetylacetonate trimethylvinylsilane (Cu÷(hfac)TMVS) to deposit copper by the reaction Cu÷(hfac)TMVS(g)
> 130 °C
, Cu°(s) + Cu2÷(hfac)(g) + 2TMVS(g)
(1)
In Cu 2÷ precursors the valency of Cu is two and the decomposition is caused by thermal or plasma effects leading to free copper and other decomposition products which are vapors and are pumped away. The most commonly used precursor is Cu2÷(hfac)2, which has been shown to yield excellent copper films [20]. More recently a new precursor, Cu2+(tdf)2, has been synthesized [27] and shown to have a significantly high vapor pressure, which will yield better deposition rates [27, 28]. The chemical forms and exact nomenclatures of these three precursors and the vapor pressure curves of the two Cu2÷ precursors are shown in Figs. 1 and 2 respectively. At 85 °C Cu 2÷ (tdf)2 has a vapor pressure of about 4kPa, compared with about 0.08 kPa for Cu2+(hfac)2 . The increase in vapor pressure is associated with the heavier fluorinated radicals replacing the lighter radicals, in agreement with the predictions of
S. P. Murarka et al. / Advanced multilayer metallization schemes
260 (a)
CH3
(1) Since a sensitizer is necessary to cause deposition, how are the necessary deposition and patterning of such a metal in vias on an dielectric surfaces to be achieved? (2) What are the contaminants (from the bath) incorporated in deposits and do they affect the properties of copper and its reliability? (3) How will the surfaces of electroless copper be passivated? (4) Will deposition occur reliably in small holes (contacts and vias), since surface tension effects may not permit the bath solution to reach the bottom of the holes? (5) Will an annealing step to optimize the properties of the deposit be required? We conclude that blanket film deposition technologies for copper are now established which can be incorporated depending on the need. However, the selective deposition of copper on desired regions (e.g. a metal or alloy in a window or via) needs significant research and development effort and reliability evaluation.
CH3
N/ /'\,_~
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ella
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O
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(b) CF3\
/CF3 C--O
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/
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(c)
/
C--O
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/
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,,
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"CF2CF2CF 3
Fig. 1. Chemical formulae of the three precursors for CVD: (a) copper hexafluoroacetylacetonate trimethylvinylsilane; (b) Cu(hfac)2 or bis(1,1,1,5,5,5-hexafluoroacetylacetonato) copper(II); (c) Cu(tdf)2 or bis( 1,1,1,2,2,3,3,7,7,8,8,9,9,9-tetradecatluorononane-4,6-dionato) copper(II).
100.0
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i
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111 ~
i
T (°C) 84 I
I
"-\
40
"'..Cu(tdf) 2 xx x
r~
I
"'. ",
X
60 I
%%
Cu(hfac)2~ ~ 0.t
~
,
>
0.01
I
I
2.6
I
I
[
I
2.8 3.0 10 3 / T (K -1 )
I x
3
Fig. 2. Vapor pressure o f (a) Cu(hfac)2 and (b) Cu(tdf) 2 precursors.
Sievers and Sadlowski [29]. Using these precursors and thermal or plasma-assisted CVD, excellent copper films with a resistivity as low as 0.017 la~ m have been deposited on wafers as large as 0.2 m in diameter. Electroless deposition of copper offers a very simple, inexpensive and versatile technique when compatible with ULSI and GSI processing constraints. Electroplating and electroless deposition of copper are well known and several chemical baths and recipes are available [30]. Attempts are being made to utilize this technology to deposit metal selectively in contact holes [21, 22]. However, several key questions remain to be answered.
4. Patterning of copper interconnections The conventional approach to pattern generation is to reactively ion etch the material off the surfaces not protected by a photoresist mask. The use of such dry etching processes for Cu has been difficult owing to the lack of volatile copper species at temperatures relatively close to room temperature where the photoresist masks retain the geometrical shape. In spite of these difficulties, several attempts have been made to dry etch copper [2-5]. In all cases a special mask material such as amorphous carbon or a polyimide was first patterned using a photoresist. Such masks were then employed to generate patterns in copper films. Chlorine-containing s p e c i e s ( C C 1 4 , CC12F2, C12, SIC14 and BCI3 in argon or nitrogen) and substrate temperatures as high as 250 °C were employed in a reactive ion etch mode [2-5]. These results indicate that etching of copper at temperatures of 250 °C and above is possible. However, such high temperature processes are not very attractive because of the need for a useful and reliable mask material which remains stable during actual etching. Also, copper migration under plasma-induced biases and high temperatures is a serious concern. One can envisage the use of wet chemical etching of copper, which etches readily in a variety of chemicals. However, such etches are isotropic and would be limited to wider interconnection lines where undercutting due to isotopic etching can be tolerated and compensated in the mask definition. One can envision such etchings at upper-level multilevel interconnections. While wet etching of copper may find initial application in such cases, the widespread use of copper interconnect technology requires high aspect ratio patterning.
S. P. Murarka et al. / Advanced multilayer metallization schemes
(b)
si 0 2
Fig. 3. Concept of chemical-mechanical polishing used to generate inlaid Cu interconnections (vertical and horizontal as required) in SiO2: (a) schematic view of as-deposited Cu; (b) after CMP.
The Damascene process to generate inlaid copper interconnections [7] can be used to achieve such patternings. The concept is shown schematically in Fig. 3. The desired trenches and vias are etched in SiO2 by conventional reactive ion etching (RIE). The diffusion barrier-adhesion promoter followed by a thick layer of copper is deposited, leading to the cross-sectional view in Fig. 3(a). This structure is then chemically-mechanically polished, ending with the structure shown in Fig. 3(b). One can stop at the Ti layer as shown or continue to the SiO2 dielectric surface. Not only is a planarized surface achieved, but also the copper in vias or trenches is encapsulated by the diffusion barrier-adhesion promoter on all surfaces except the polished surface. Thus the need for etching the copper and diffusion barrieradhesion promoter is circumvented. The chemical-mechanical polishing (CMP) process consists essentially of two components: mechanical grinding and chemical etching. Suspended particles in the slurry impinge on the surface and cause dislocation and strain within it, sometimes even dislodging atoms or atom clusters from the surface. Chemicals in the slurry react with the dislodged materials (increased surface area) or the strained surface layers at accelerated rates and remove such material into the slurry. Chemicals could also play an important secondary role of passivating the surface being polished until mechanical grinding removes the passivated layer. The latter mechanism helps in reducing the topography on the surface [10]. The chemical phenomena occur at the metal surface, at the pad and at the slurry particle surface, leading to metal dissolution in the slurry removed. The mechanical phenomena also occur at the same surfaces and affect the physical shape of the grinding particles and the pad. The mechanical effects of the CMP process are controlled by physical parame-
261
ters such as pressure, pad velocity, sample rotation, area dependence, possible influences on the chemical activities and damage, and pad-related parameters such as pad type, pad reconditioning, slurry type, slurry particle size and possible influences on the chemical activities. The chemical effects of the process are related to material etch rate, slurry pH, oxidationreduction potential, selectivity to dielectric and barrier layer, effects on pad or machine, post-polishing residue removal, optimization of the abrasive and chemical combination, localized temperature, stress effects on chemical reactions, localized changes in the concentration of chemicals, and effects of increasing concentration of metal in the slurry. Since metals are generally softer and more ductile than glass or semiconductors whose surfaces are also prepared by use of this technique, it is more critical to strike an appropriate balance between the chemical and mechanical components of the polishing process through proper control of the numerous process variables described above. The polishing kinetics is generally given in terms of Preston's equation [31] AH L As At = Kp A At
(2)
where AH/At is the removal rate of the material in terms of change in height per unit time of polishing, L is the load imposed over a surface area A, As[At is the relative velocity of the pad to the sample and Kp is Preston's coefficient, which is weakly variable. The equation predicts that for a given L/A the weight loss of the polished material is proportional to the amount of travel and remains invariant with time. The polishing rate increases with increasing pressure (L/A) and velocity. One of the important implications of the above equation is that the removal rate is independent of the abrasive particle size in the slurry. Since Preston's equation is basically a mechanical model for the removal rate by a CMP process, the validity for CMP of copper and the variation in Kp with processing conditions need to be established. For the copper CMP Damascene process we have focused on developing a global planarization process to obtain a high selectivity of polishing rate between copper and the underlying diffusion barrier-adhesion promoter or dielectric. The four phenomena that determine the usefulness of a CMP process, namely nonuniformity, rounding, dishing and erosion [8-10], are being addressed. Copper is a relatively soft material and residual scratches that may result from mechanical grinding are of concern as well. Finally the post-planarization cleaning and passivation are being addressed so that a complete sequence of processes can be outlined to implement a Cu Damascene CMP process.
S. P. Murarka et al. / Advanced multilayer metallization schemes
262
Our initial findings [7] have successfully demonstrated the patterning of copper lines using this chemical-mechanical polish. Both narrow (1.0 ~tm) lines and large (100 ttrn x 100 ttm) bonding pads within close proximity of each other have been defined. Figure 4 shows a scanning electron microscopy (SEM) image of 1.5 and 1.0 lam lines recessed into trenches 1.5 ttm deep. Figure 5 shows an optical micrograph of various patterns. Clearly it is possible to use a CMP process to define copper structures of all dimensions. Considerably more research and development effort is needed to make the process reliable and manufacturable.
5. Diffusion of Cu in SiO2-based dielectrics and silicides Fig. 4. SEM cross-sections of copper interconnections after CMP. Samples were cleaved to show the depth.
McBrayer et al. [ 13] examined the diffusion of Cu in SiO 2 films and reported noticeable diffusion in SiO2, especially after Cu-on-SiOz samples were biased at temperatures as high as 400 °C. We have also examined the thermal diffusion and electrical-bias-aided diffusion of Cu in SiOz [32, 33]. Table 3 summarizes qualitatively the interactions of copper films on phosphorus (about 7wt.%) glass (PG), undoped oxide deposited using tetraethoxyorthosilicate as precursor (TEOS) and thermal oxide (SiO2) on annealing in argon and A r 3 v o l . % H z. Several conclusions can be made. (I) Copper interacts (diffuses) in PG more readily than in undoped oxides, indicating the possibility of phosphorus get tering of copper. (2) Copper was oxidized in the absence of hydrogen, possibly owing to the presence of contamination and oxidizing species in argon. (3) Even when oxidation of copper occurred, detectable amounts of Cu diffused in all oxides at temperatures in the range 300-400 °C for 30 min anneals. (4) Hydrogen present
Fig. 5. Optical micrograph o f copper interconnections and pads generated by CMP.
T A B L E 3. Interactions of copper with phosphorus glass, TEOS and thermal oxide Annealing gas
Sample
200 °C
300 °C
400 °C
500 °C
Ar
Cu - P G
__ a
Noticeable diffusion
Cu-TEOS
.
Considerable diffusion Diffusion
Cu-SiO 2 (thermal)
--a
--~
Significant diffusion Noticeable diffusion Significant diffusion
Cu-PG
a
Noticeable diffusion
Diffusion
Cu-TEOS
--~
Noticeable diffusion . . .
Cu_SiO 2 (thermal)
a
__a
Ar + 3% H 2
aNo detectable interaction or change observed.
.
.
.
.
__a
Diffusion
Possibly a hint of diffusion Some diffusion
S. P. Murarka et aL/ Advanced multilayer metallization schemes
in the annealing environment suppressed both the oxidation of copper and its diffusion in undoped oxides, leading to at least a 100 °C increase in temperature, at which detectable amounts of copper were seen after a 30 min anneal. Also investigated were (a) the metaloxide-semiconductor (MOS) characteristics of C u SiO2-p-Si MOS capacitors after annealing at various temperatures and (b) the minority carrier lifetime in silicon after diffusion anneals of Cu-100 nm SiO2-Si samples [34]. The results indicate that there is no measurable effect of Cu (if any) in SiO2 at temperatures below 500 °C in hydrogen-containing ambients. However, when the MOS capacitors were annealed under a bias of 150 M V m -1 (up to temperatures of 300 °C), copper did diffuse in SiO2, affecting its electrical properties [33, 35]. These results are in agreement with the findings of McBrayer et al. [ 13] and ShachamDiamond et al. [36] and thus clearly show that a diffusion barrier that will stop bias-induced Cu migration is necessary. The results of Table 3 also show that (a) when annealed in argon, the diffusion barrier effectiveness of SiO2 is reduced to temperatures lower than 400 °C and (b) phosphorus glass is not a suitable barrier even at 300 °C in pure argon or Ar-H2 ambients. Copper diffusion in silicides which may form electrical contacts to silicon or polysilicon has also been investigated. CoSi2 and TiSiz are two self-aligned silicides that are being used for such applications. Thermal diffusion studies of Cu on these silicides show no observable Cu migration, at least up to 500 °C for anneals up to 30 min [37, 38]. In the case of Cu on CoSi2, the stability of Schottky diodes formed on n-Si was also examined as a function of the annealing temperature. The results of these measurements and Rutherfordbackscattering spectroscopy (RBS) analyses indicate that Cu on CoSi2-Si is stable for at least up to 30 min at 600 °C when annealed in Ar-H2 ambients.
6. Adhesion promoter and diffusion barrier Copper will not reduce S i O 2 and is therefore expected not to adhere well to SiO2 surfaces. Copper films sputtered in commercial equipment that pumps down to about 10-5 Pa pressure prior to sputtering show reasonable adhesion to both SiO2 and polymer films. Most of them pass the Scotch tape peel test in the as-deposited condition but peel off on heating to higher temperatures (and cooling). The latter effect is related to thermal stress generated by the difference in thermal expansion coefficients of SiO2 and Cu. Similar adhesion failures are observed for evaporated films. However, recently reported results for copper films sputtered under very high purity conditions in equipment pumped down to 10-6-10 -7 Pa on oxides that have been heated to des-
263
orb water molecules off the surface show that such films adhere extremely well to SiO2 surfaces [15, 16]. Copper films deposited on polymers by the partially ionized beam technique also show excellent adhesion [23]. Similar results of copper adhesion on Teflon surfaces were reported for films deposited by the ionized cluster beam method [24]. These dearly indicate that copper will pass adherence requirements when deposited on clean and moisture-free surfaces. Of the various techniques used to enhance the adhesion between the dielectric (SiO2 or polymer) and copper, three seem most attractive: (a) use of adhesion promoters; (b) increased temperature of deposition or providing energy to ionize (depositing) species; (c) surface pretreatment, especially plasma oxidation of polymers, sputter damage of metal surfaces or use of ion implantation near the polymer or metal surface. We are concerned with the use of adhesion promoters which could also act as diffusion barriers at higher process temperatures. Adhesion promoters must form excellent bonding with both the dielectric and the metal. In addition, they should not allow the diffusion of metal atoms in the dielectric. Titanium, T i - W and TiN have been most frequently used because of titanium's excellent chemical reactivity with oxygen, carbon, nitrogen, fluorine, etc. Recent results indicate that copper interacts with all of them at temperatures as low as 300 °C when annealed in an inert or vacuum ambient. However, when annealed in ambients containing hydrogen, pure titanium forms a hydride and the T i - C u structure is stable to 400-450 °C. The hydride passivates the fast diffusive paths and the interface between metals and inhibits interdiffusion at low temperatures. Other adhesion promoters that are being investigated presently are Cr, Ta, A1 and Mg. The ultimate objective of finding a diffusion barrier that will also perform as an adhesion promoter between Cu and the insulator (SiO2 or polymer) is to identify an electrically stable Cu-diffusion barrier-insulator or Cu-diffusion barrier-contact silicide system. Thus with the advent of sub-0.25 Ixm geometries, where the thickness of the barrier-adhesion layer may shrink to less than 10 nm and the metallurgical stability may not be guaranteed, one must look for an electrically stable and reliable barrier layer that may or may not be metallurgically sacrificial. An investigation of thin A1 films as an adhesion promoter-diffusion barrier between copper and SiO2 has been carried out [39]. MOS capacitors of (A) pure Cu on SiO2, (B) pure A1 on SiO2 and (C) Cu-A1 on SiO2 were subjected to thermal annealing and bias-temperature-stress (BTS) aging. Both metallurgical and electrical stabilities were investigated. It was found that although aluminum reacted readily with copper, its presence between SiO2 and Cu provided the
S. P. Murarka et al. / Advanced multilayer metallization schemes
264
1.0
8 c 0
O
N
E
,=
Z
Z
®
(~) BTS (250°C. 5 MIN) ~ ) BTS (2fi0°C. 30 MIN) (~) 8TS (250°C. 60 MIN) 01
.20
'
-.:s
'
-,~
.~
@ BTS (250"C. 5 MIN) ~ ) 8TS (250°C. ~0 MIN) ~'0
~s
~,
Bias (V)
Fig. 6. C - V characteristics of 130 nm SIO2-500 nm Cu MOS capacitor sample electrically (about 1 5 0 M V m -t) stressed at 250 °C for various times.
required electrical stability. For all samples the asdeposited C - V plots show flat-band voltages near - 1 0 V due to processing-induced interface states. After a 5 rain anneal at 250 °C the effect o f these states is eliminated and flat-band voltages between - 2 and - 3 V are achieved for all samples. These curves are then used as the "zero point" for all comparisons to determine any metal impurity movement into the silicon. Sample A with 500 nm of copper directly on SiO2 starts to show movement of the flat-band voltage after 30 min of BTS aging at 250 °C. After 1 h, the curve moves down even further and shows a change in curve shape reminiscent of a possible increase in dopant concentration (Fig. 6). This change is due to copper permeating the S i O 2 , perhaps distributing itself across the oxide and entering the silicon substrate [40]. By contrast, sample B with only 500 nm of aluminum on oxide shows no movement under the same BTS conditions and exposure times (Fig. 7). Both these results confirm published data that have led to the maturation of aluminum technology and the abandonment of copper in VLSI fabrication. These samples were used as controls for the results from those of type C (50 nm A1 on 500 nm Cu). According to the C - V plots presented in Fig. 8, the A1-Cu bilayers show characteristics identical to those of aluminum under the given conditions. There is no net movement of the flat-band voltage or shape change after the BTS anneals. The obvious conclusion is that there is no net movement of electrically active species from copper into the oxide or to the Si-SiO2 interface; thus aluminum, which may have oxidized at the SiO2-AI interface, is acting as an effective diffusion barrier. These results support the known electrical stability of A I - C u alloys used as interconnections on and between SiO2 layers.
.io
.i
5
1"0
15
Bias (V)
Fig. 7. C - V characteristics o f 130 nm SiO 2 -500 nm AI MOS capacitor sample electrically (about 150 MV m -1) stressed at 250 °C for various times.
0
® ~ ) fiTS (250°C. S MtN) ~ ) BTS (250°C. 60 MIN) *20
-15
-10
-i
"s
~
,s
Bias (V)
Fig. 8. C - V characteristics of 130 nm SIO2-50 nm AI-500 nm Cu MOS capacitor sample electrically (about 1 5 0 M V m - t ) stressed at 250 °C for various times.
We believe that for ULSI and GSI devices such electrically stable barriers of thickness less than 100/~ are necessary. In this respect A1 is better, since it is known to form a self-limiting A l - o x i d e (or A 1 - O x Siy) layer at the interface. On the other hand, in a similar use Ti is known to consume SiO2 on continued annealing [41] and may thus be harmful if the gate sidewall oxide thickness is small (less than 10 nm). Also, dissolved AI in Cu increases the resistivity by only about 0 . 0 1 ~ m a t . % -1 A1 in Cu, which can be compared with about 0.110.161 ~ Q m a t . % - ~ T i in Cu. Mg is another possible barrier element which when dissolved in Cu changes its resistivity by less than 0.01 laf~mat.% -1 Mg in Cu [11].
S. P. Murarka et al. / Advanced multilayer metallization schemes
7. Passivation of Cu surfaces exposed to dielectric deposition or atmosphere
Passivation o f copper surfaces is of utmost importance to make copper interconnection technology become manufacturable and not just a research curiosity. As discussed above, copper surfaces do not bond with SiO: and copper diffuses into SiO: under electrical bias, affecting the electrical properties of the dielectric. Also, copper corrodes readily in ambients containing oxidizing agents and sulphur. Thus etched or polished copper surfaces must be passivated to prevent interactions with SiO2 and the environment. Ideally one would like to passivate all exposed surfaces in one treatment. Such treatments would include dipping in liquid or gaseous surrounds. Cabrera et aL [42] and Hymes et al. [43] have exposed copper surfaces to silane in the temperature range 300-400 °C to form a silicided surface. Figure 9 shows the sheet resistance ratio (post-oxidation anneal/ pre-anneal after silicide is formed for the anneals of 10 min in silane) as a function of time and temperature of oxidation in air. It is clearly demonstrated that the silicided surfaces provided corrosion protection in air even at 350 and 400 °C.
4.00 350°C/10 min/Silone .0 rr
3.50 3.00
"i 2.50 112 ~ 2.00
265
Ding et al. [44] have shown that implanted b o r o n and aluminum passivate copper surfaces. Boron in concentrations as low as 0.01% is known to provide corrosion resistance to copper [45]. It is also a common ion implantation species used to provide a p-type doping profile in Si. SiO2 films are used as masks to prevent implantation and diffusion in undesirable regions of Si. Thus boron implantation is a natural choice to provide passivation of copper surfaces. If copper interconnections are defined using the Damascene (CMP) approach described earlier, the implantation of exposed copper surfaces provides the necessary passivation without affecting the surrounding oxide surfaces. However, this technique leads to a gaussian depth profile of boron in copper, leaving the top layers of the metal with depleted or zero boron concentration. Such surfaces oxidize until the boron-rich regions (deeper in the metal) are met by the oxidized layers. Oxidation then stops. Thus a process is needed to place boron directly on the surface of copper. It may be pointed out that a considerable amount of research is needed to establish the usefulness of silicide or boron passivation process. Also, the electrical and mechanical stabilities of these passivated surfaces when in contact with the top insulating layers must be established. Passivation of copper can also be achieved by alloying the top layers. Li et al. [46] have shown that the compounds Cu3Ti, Cu3Pd and CuAI: are stable in ozidizing ambients. However, alloying surfaces of copper selectively is difficult if not impossible and use of these alloys to replace copper is self-defeating because of the very high resistivities.
g 1.50 1.00-0
8. Conclusions 5
10
(a)
15
20
25
30
T i m e (min)
5.5 o
5
325°C/10 min/Silane
4.5
~c 4 -~ -3.5
~ 3 ~ 2.5
g~ 2 1.5 --300
(b)
m 350
400
450
500
550
T e m p e r a t u r e (°C)
Fig. 9. (a) Sheet resistanceratio Rs(post-anneal)/Rs(pre-anneal ) as a function of annealing time for 400, 450 and 500 °C anneals in air after 350 °C, 10 min silane exposure to form copper silicide on surface. (b) Sheet resistanceratio Rs(post-anneal)/Rs(pre-anneal ) as a function of annealing temperature for 5, 10 and 20rain anneals in air after 325 °C, 10 min silane exposure to form copper silicide on surface.
This paper has reviewed the present state of knowledge regarding the use of copper in a multilevel scheme. To create an M L M structure, the following scheme appears to be attractive, although a considerable amount of research is needed to prove its viability and reliability. (1) Etch vias and trenches in a planarized dielectric to form vertical and horizontal interconnections. (2) Deposit 10 nm or less of AI or Ti by CVD or deposit 10 nm or less of AI or Ti by sputtering followed by a thin (about 10-50 nm) layer of copper. (3) Deposit required thickness of copper by CVD. Note that excess copper thickness is needed so that C M P can be used to planarize and form buried interconnections in oxide. (4) Chemically-mechanically polish copper (ending up with interconnections as shown in Fig. 3) and stop at A1 or Ti or at SiO2 surface. If stopped at AI or Ti,
266
S. P. Murarka et al. / Advanced multilayer metallization schemes
chemically etch A1 or Ti selectively without etching copper or its protection on sidewalls. Clean. (5) Passivate copper surface using silane or boron implantation. (6) Deposit new layer of insulator for next level and follow steps (1) -(5). The above sequence of process steps is possible and available information presented in this paper points to this effect.
Acknowledgments The authors would like to thank Sematech, SRC, Intel, IBM, Motorola, Watkins-Johnson and MKS Instruments for their support of this investigation on copper MLM technology and for the results presented here.
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