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GaAs PHEMTs under accelerated DC stresses
Microelectronics Reliability 46 (2006) 2025–2031 www.elsevier.com/locate/microrel
Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses Hou-Kuei Huang, Chou-Sern Wang, Mau-Phon Houng, Yeong-Her Wang
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Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan, ROC Received 7 September 2004; received in revised form 23 September 2005 Available online 17 April 2006
Abstract The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this. 2006 Elsevier Ltd. All rights reserved.
1. Introduction Pseudomorphic high electron mobility transistors (PHEMTs) have been widely used in both power and low-noise applications in the microwave and millimeter wave frequency range [1–3]. Since power PHEMTs are typically biased at high drain voltage, the reliability of devices operating under high electric fields requires in-depth examination. Although changes in the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs before and after hotelectron stresses have been extensively studied [4–8], the behavior of Schottky gate characteristics under hotelectron stresses has received far less attention. This paper investigates the DC characteristics and mechanisms for Schottky barrier variation before and after hot-electron stresses. A model related to the degradation of the image
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Corresponding author. Tel.: +886 6 2757575x62352; fax: +886 6 2080598. E-mail address: [email protected] (Y.-H. Wang). 0026-2714/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.02.013
force of the Schottky barriers is proposed to explain the mechanisms of the gate leakage current variation. The gate leakage current will be decreased after hotelectron stresses, due to the effects of hot-electron stresses on the Schottky diode characteristics. Shot noise is one of the major noise sources in HEMTs and related to the gate leakage current and the barrier control [9]. Consequently, the Schottky barrier related to gate leakage current plays an important role in low-noise applications, which requires further study. As mentioned above, improvement in noise performance is expected with decreasing gate leak current. The high electric field between the drain and the gate—that is, the drain voltage—is the essential factor for inducing the hot electrons and leads to impact ionization. However, the key parameter influencing impact ionization upon DC hot-electron stresses is the number of hot electrons relating to the drain current when the electric field between the drain and the gate is sufficiently high [10]. Two conditions are used to investigate the impact of hot-electron stresses on the gate leakage current: devices being stressed under the saturation drain
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current and devices being stressed under the maximum gate leakage current. Pre- and post-stress noise measurements under these two conditions have been done to demonstrate the effects of noise performance of AlGaAs PHEMTs after hot-electron stresses. 2. Experiments The devices used in this investigation are MBE-grown AlGaAs/InGaAs/GaAs pseudomorphic HEMTs, as shown in Fig. 1, with 0.25 lm gate length and 160 lm gate width. The PHEMT structure comprises an GaAs/Al0.25Ga0.75As/ GaAs buffer layer on (1 0 0) semi-insulating substrate, an undoped In0.15Ga0.85As channel layer, an undoped Al0.25Ga0.75As spacer layer, an n-type Al0.25Ga0.75As donor layer, an undoped Al0.25Ga0.75As Schottky layer and, finally, a heavily doped n-type GaAs cap layer. The Hall mobilities at room temperature and 77 K are 5170 and 18,700 cm2/V s, corresponding to the two-dimensional carrier densities 2.14 · 1012 and 1.98 · 1012 cm2, respectively. Devices were processed by conventional optical lithography techniques. There are three major processes in fabricating this AlGaAs PHEMT: device isolation, ohmic contact, and Schottky contact. The mesa was achieved by using HF/H2O2/H2O as the etching solution. Au/Ge/Ni was evaporated to form the source and the drain for ohmic contacts and then annealed at 420 C for 20 s on a hot plate. A HF/H2O2/H2O solution was used to remove the GaAs cap layer to fabricate the gate. Ti/Pt/Au was then deposited for the Schottky gate by lift-off processes. Finally, the devices were passivated by Si3N4. The minimum device breakdown voltage is 9 V, which is the voltage when IDG = 0.5 mA/mm when the source is floating. The maximum drain and gate voltages are 7 V and 3 V, respectively. The drain voltage and the stress current must be sufficient to excite the impact ionization, so a high drain voltage near the breakdown voltage, VDS = 7 V, and a drain current equivalent to the saturation
Fig. 1. Cross-sectional view of a PHEMT and the hot-electron phenomena in a schematic GaAs PHEMT structure.
current, VGS = 0 V, are used. The reliability study of the hot carriers is performed by stressing the devices for 60 min at room temperature. The variation of device DC parameters before and after hot-electron stresses, including drain current; IDS; transconductance, Gm; pinch-off voltage, Vp; gate current, IG; source and drain contact resistance, RS and RD; are also examined. Fig. 1 illustrates the hot-electron related phenomena in a schematic GaAs PHEMT structure. The impact ionization is triggered when the electron is hot enough to overcome the band gap; moreover, when hot-electron scattering occurs with a lattice atom, a valence band electron may gain sufficient energy to leap into the conduction band, creating a hole. Some of these holes may leap out of the valence band discontinuity and enter the donor layer. These holes may eventually be trapped in pre-existing traps or collected by the gate. The expected result is device degradation. Hot electrons and impact ionization thus represent a serious reliability concern for PHEMT. As a result, the measured gate leakage current can be used to predict the intensity of impact ionization. As described above, two conditions are used to stress these AlGaAs PHEMT devices, and the variations of gate leakage currents are measured before and after stresses. The devices are stressed under the saturation drain current, which can be realized by setting the bias on VGS = 0 V, and under the maximum gate leakage current, which is obtained from the extrapolation of the VGS bias by the bell-shaped curve of the gate leakage current, as shown in Fig. 6. Furthermore, the variations in noise performance are measured to identify the relationship between the noise performance and the gate leakage current. 3. Results and discussion 3.1. Gate-drain breakdown walkout Gate-drain breakdown (GDB) is the major limitation in the power handling capability of compound semiconductor heterostructure FETs, which are biased in the saturation region in most analog applications. Fig. 2 illustrates the
Fig. 2. The output characteristics of AlGaAs/InGaAs/GaAs PHEMTs under test before (solid line) and after (dashed line) stressing for 60 min at VDS = 7 V and VGS = 0 V.
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output characteristics of the PHEMTs being tested before and after 60 min of hot-electron stresses at VDS = 7 V and VGS = 0 V. Notably, the stresses significantly decreased the drain current, IDS, at higher drain voltages. This phenomenon is known as the breakdown walkout, and is attributed to the hot-electron effects reported by Menozzi et al. [11]. The gate-drain breakdown walkout is believed to be caused by the creation and filling of electron traps between the gate and the drain, leading to widening of the depletion region and reducing the electric field [12,13]. End resistance measurements [14] indicate that the drain-to-channel resistance, RD, will increase by approximately 12% after hot-electron stresses, while on the source side only a slight decrease in RS, 0.2%, is observed. The increase in RD is consistent with the hypothesis that the gate-drain depletion region is widened, and a slight decrease in RS indicates an increase of IDS in the saturation region resulting from the effect of threshold voltage shift, which will be discussed later. Notably, the gate-drain breakdown walkout is permanent—that is, after hotelectron stresses, the increase in RD and the decrease in RS cannot be reversed, even with long-term storage. 3.2. Existence of the kink A kink is observed at VDS near 2.5 V before and after hot-electron stresses, as shown in Fig. 2, indicating the occurrence of trapping–detrapping phenomena [15–17]. The kink position is notably shifted towards a higher VDS in accordance with the changing rates of the drain current vs. VDS, as shown in Fig. 3. The kink position shift is due to the decreased threshold voltage, which will be discussed below. Consequently, the value of the maximum electric field at the drain-to-gate area is lower in a stressed device than in an unstressed device under the same VGS [4]. 3.3. Increase of IDS in the saturation region After hot-electron stresses, most of the holes generated by the impact ionization are collected by the gate—that is, these holes are trapped under the gate, as shown in Fig. 1. Since most of the holes—that is, the positive
Fig. 3. The kink position is notably shifted towards a higher VDS due to the changing rates of the drain current vs. VDS after hot-electron stresses.
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Fig. 4. The transfer curve of AlGaAs/InGaAs/GaAs PHEMTs under test before and after stressing for 60 min at VDS = 7 V and VGS = 0 V.
charges—are accumulated under the gate, the threshold voltage shifts towards further negative VGS values. Consequently, the IDS in the saturation region will increase after hot-electron stresses. The other mechanism of the increased IDS is the reduction of the negative charges in deep traps and DX-centers, as illustrated in Fig. 4. If DIDS is only caused by the variation in the threshold voltage, DVT, then the correlation between DIDS and DVT can be explained via the following simple model: DIDS(VGS) = IDS(VGS DVT) IDS(VGS). Substituting for IDS(VGS DVT) with its first Taylor polynomial term yields IDS(VGS DVT) = IDS(VGS) Gm(VGS)DVT; thus Gm(VGS) = DIDS(VGS)/DVT [6]. When this simple model is used to fit the experimental data, significant deviations are observed, as shown in Fig. 5. This simply means that more interface undesired states, which can trap electrons, exist at the AlGaAs/InGaAs heterojunction generated by hot carrier bombardment, which reduces the channel carrier density due to the charge trapping. Hence, the effects of carriers trapped at an AlGaAs/ InGaAs heterojunction join with the effects of the threshold voltage shift, causing the stressed transfer curve to shift backward. After hot-electron stresses, the shape of Gm remained unchanged when VGS < 0.6 V, and the model perfectly fits the experimental data, as shown in Figs. 4 and 5. However, when VGS > 0.6 V, the opposite
Fig. 5. DIDS/DVT and Gm as a function of VGS. The DIDS and Gm have been calculated at VDS = 2 V.
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behavior is observed due to hot-electron stresses in the non-gate area [6], even though the model fits well with the experimental data in the low drain current range but not in the higher drain current range. The variations of RD and RS caused by the hot-electron stresses in the nongate area are negligible in the low drain current range but not in the higher drain current range. The key point is that the VT-shift analysis must be performed under the condition that the effects of hot-electron stresses in the non-gate area are negligible [6]. Consequently, when VGS > 0.6 V, the model cannot fit well with the experimental data after hot-electron stresses, as shown in Figs. 4 and 5. 3.4. Bell-shaped behavior of IG Fig. 6 illustrates IG as a function of VGS at various VDS from 5.5 to 7.5 V with 0.5 V increment. Moreover, IG represents the typical bell-shaped behavior previously noted in MESFET [18] and PHEMT [19]. In this paper, the bellshaped behavior of IG after hot-electron stresses is also discussed. After 60 min of hot-electron stress at VDS = 7 V and VGS = 0 V, jIGj decreases at all VGS with fixed VDS, as shown in Fig. 6. There are several possible explanations for this. First, the depletion region under the gate expands towards the drain after hot-electron stresses, and the widening of the depletion region reduces the maximum electric field [12,13], causing the ionization rate to decrease. Thus, jIGj decreases in the 1.2 V < VG < 0.5 V region after hot-electron stresses. Another explanation recognizes that the primary mechanisms causing reverse leakage current are (1) thermionic emission, (2) thermionic field emission, and (3) field emission. The reverse leakage current caused by thermionic emission is affected by the drop of the image-force barrier height; both thermionic field emission and field emission are tunneling mechanisms that depend on the Schottky barrier width and height [20]. The image-force barrier height lowering depends on the electric field at the metal– semiconductor interface [21]. As illustrated in Fig. 7, the electric field after hot-electron stresses, Em 0 , is smaller than
Fig. 6. Gate current versus gate bias measured at different VDS of AlGaAs/InGaAs PHEMTs before (solid line) and after (dashed line) stressing for 60 min at VDS = 7 V and VGS = 0 V.
Fig. 7. The behavior of image force height lowering after DC stress. W < W 0 ! Em > Em 0 ! DuB > DuB 0 ! jJrj (before stress) > jJrj (after stress).
the one before hot-electron stresses, Em, because the gatedrain depletion region after hot-electron stresses, W 0 , is wider than the one before hot-electron stresses, W. A smaller electric field results in a smaller image-force barrier height lowering, DuB (before stress) >DuB 0 (after stress). Therefore, the reverse leakage current also decreases, jJrj (before stress) > jJrj (after stress). Consequently, jIGj decreases in the VG < 1.2 V region as well as in the VG > 0.5 V region after hot-electron stresses. Finally, the resistance of the drain access region (RD) increases by approximately 12% after hot-electron stresses, which is consistent with the hypothesis regarding the widening of the gate-drain depletion region. Additionally, the reverse bias characteristics of the gate-drain diode with the source floating have also been measured, as shown in Fig. 8, to further establish that the gate-drain depletion region is widened by hot-electron stresses. Fig. 8 illustrates that the reverse current of the gate-drain diode with the source floating decreases after 60 min of hot-electron stresses at VDS = 7 V and VGS = 0 V. The result indicates that the image-force barrier height lowering decreases after hot-electron stresses, which is caused by widening of the gate-drain depletion region, as shown in Fig. 7. Thus, hot-electron stresses clearly widen the gate-drain depletion region. As shown in the inset of Fig. 8, the variations in the
Fig. 8. The reverse and forward (inset) bias characteristics of the gatedrain diode with the source floating and with the source and the drain shorted before and after stressing for 60 min at VDS = 7 V and VGS = 0 V.
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forward bias characteristics of the gate-drain diode with the source floating or with the source and the drain shorted are small enough to be ignored. Two major mechanisms influence the characteristics of the Schottky barrier height after hot-electron stresses. One is the widening of the depletion region, while the other is the trapping of the carriers under the gate. The widening of the depletion region under the gate reduces the peak of the electric field [12,13] and decreases the image-force barrier height lowering, leading to larger Schottky barriers. One possible explanation is that the reverse leakage current density decreases with larger Schottky barriers. Meanwhile, the trapping of carriers under the gate may cause an increase in the electric field at the metal–semiconductor interface, leading to a smaller Schottky barrier height due to the increase in image-force barrier-height lowering. Consequently, the phenomena of the reverse bias characteristics of the gate-drain diode with the source and the drain shorted are the opposite of those with the source floating, after hot-electron stresses, as shown in Fig. 8. There are two possible explanations. First, when the source is floating, the effect of the widening of the depletion region dominates the device characteristics, leading to a larger Schottky barrier height and a smaller reverse leakage current after hot-electron stresses, as illustrated in Fig. 8. Alternatively, when the source and the drain are shorted, the effect of trapping carriers becomes the dominant mechanism, leading to a smaller Schottky barrier height and a larger reverse leakage current after hot-electron stresses, as also shown in Fig. 8. 3.5. IG and noise performance after two different hot-electron stresses The effects of drain-to-gate reverse current after different hot-electron stresses with the source floating are shown in Fig. 9. Twenty devices from the same wafer were stressed with the first ten stresses at VDS = 7 V and VG = 0 V and
Fig. 9. The degradation of the gate leakage currents after two different stress conditions. (d) stressed for 60 min at VDS = 5 V and VGS = 0 V; (m) stressed for 60 min at VDS = 7 V and VG at the maximum gate leakage current. The range of IDSS: 45 to 55 mA. The range of the maximum gate leakage current: 156 to 225 lA.
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the other ten at VDS = 7 V and VG at the maximum gate leakage current stress. The circular notation indicates the IDG degradation ratio after stressing for 60 min at VDS = 7 V and VG = 0 V, i.e., IDS = IDSS. The average degradation ratio of IDG for these ten devices is 11%. The triangular notation indicates the IDG degradation ratio after stressing for 60 min at VDS = 7 V and VG at the maximum gate leakage current—that is, IDS < IDSS. The average degradation ratio of IDG is 13.47%. The ratio of the stressed current, IDS, to the saturation current, IDSS, for each sample ranges from 23% to 65%. The IDSS of these samples ranges from 48 to 53 mA. Meanwhile, the drain-to-gate current with a fixed VDG of 10 V ranges from 86 to 125 lA. Due to the higher degradation ratio of IDG, the stressed condition of the maximum gate leakage current, IDS < IDSS, becomes more severe. A higher degradation ratio of IDG is caused by a wider depletion region. The major sources of the noise of PHEMT have been attributed to (1) thermal noise; (2) shot noise related to the current controlled by a barrier; (3) generation–recombination noise induced by random transitions between the band and the traps, causing fluctuations of mobile electrons; and (4) hot-electron noise associated with the ultrafast kinetic processes of dissipation within the conduction band [9]. The last three sources of noise are essentially related to frequencies corresponding to the microwave and millimeter-wave ranges [9]. The major factor in the variations of noise performance after hot-electron stresses for these three noise sources is the carrier behaviors, which are related to trapping/detrapping phenomena. One of the effects of the hot-electron stresses is the degradation of the drain-to-gate reverse current, IGD–that is, the decrease of the gate leakage current, which is also related to trapping/detrapping phenomena. In other words, the reduction of generation-recombination phenomena can be expected after hot-electron stresses. Consequently, noise performance will improve. As mentioned above, the minimum noise figure, NFmin and the associated power gain, Ga, were measured to confirm the degradation of the drain-to-gate reverse current, IGD, and to show the improvement of the noise performance by subtracting NFmin (before stresses) from NFmin (after stresses). In Fig. 10, the circular and triangular notations indicate the NFmin improvement after stressing for 60 min at VDS = 7 V and VG = 0 V, and after stressing for 60 min at VDS = 7 V and VG at the maximum gate leakage current, respectively. The averages of these NFmin improvements are 0.0148 dB and 0.0074 dB, respectively. The NFmin of these samples ranged from 0.46 to 0.52 dB before stress. The average of variations of Ga is between 0.05 and +0.15 dB. The Ga of these samples ranged from 12.51 to 13.22 dB before stress. The experimental results indicate that the better improvement of NFmin under stresses is at VDS = 7 V and VG at the maximum gate leakage current. Compared with the stress condition of VDS = 7 V and VG = 0 V, the stress condition of VG at the maximum gate leakage current can excite a stronger
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Fig. 10. The improvement of the minimum noise figure by subtracting NFmin (before stress) from NFmin (after stress) under two different stress conditions. (d) stressed for 60 min at VDS = 5 V and VGS = 0 V; (m) stressed for 60 min at VDS = 7 V and VG at the maximum gate leakage current. The frequency is 12 GHz and the DC bias is VDS = 2 V and ID = 10 mA.
impact ionization. When the impact ionization is stronger during hot-electron stresses, the impact after hot-electron stresses will become stronger accordingly. Notably, the effectiveness of hot-electron stresses is not directly proportional to the drain current. This noise performance improvement corresponds with the decrease of the gate leakage currents previously discussed.
Fig. 11. (a) Stress time dependence of the current–voltage characteristics. (b) Greater resolution in drain current at high drain voltage region as VGS = 0.6 V.
3.6. Stressed time dependence of the DC characteristics The stressed time dependence of the current–voltage characteristics is shown in Fig. 11(a) and (b). The stressed time dependence of IG is revealed from the bell-shaped behaviors shown in Fig. 12. The stress times are 30, 60, 240 and 600 min The variations of the drain current and the gate leakage current can be explained as follows: (1) As mentioned in Section 3.3, the increased drain current is observed in the low drain voltage region. The shifting of the threshold voltage, which is caused by the trapped holes under the gate, can be used to explain the increase of the drain current. Since the trapped holes are almost saturated during the first 30 min of stressing, the shifting rate of the threshold voltage is the fastest. Moreover, the shifting values of threshold voltages are almost the same at the other stressed times. Consequently, the changing rate of the drain current is also the fastest during the first 30 min of stressing. However, when the stressed times are 60, 240 and 600 min, the variations of the drain current are negligible, as shown in Fig. 11(a). (2) As mentioned in Section 3.1, the decreased drain current is observed in the high drain voltage region—that is, the drain-to-gate voltage close to the breakdown voltage. The widening of the depletion region and the drop in the Schottky barrier height lowering effect can be used to explain the decrease in the drain current. The decreased gate leakage current is also related to the widening of the depletion region, which is caused by creating and filling
Fig. 12. Stressed time dependence of IG is revealed from the bell-shaped behaviors.
electron traps between the gate and the drain. The region affected by impact ionization between the gate and the drain is limited. The created and filling electron traps are almost saturated during the first 30 min of stressing; therefore, the widening rate of the depletion region is the fastest during the first 30 min of stressing. Consequently, the widening rate of the depletion region decreases at the other stressed times. As shown in Fig. 11(b), the longer the stressed time, the lower the drain current in the high drain voltage region. Similarly, as shown in Fig. 12, the longer the stressed time, the lower the maximum gate leakage current in the high drain voltage region. In other words, the impact ionization under high drain voltage bias will be reduced after hot-electron stresses.
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4. Conclusions This work has studied the most important mechanisms of hot-electron stresses on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs. The analytical results indicate that the trap-related phenomena can be divided into five major categories. (A) Filling and depletion of traps generated by hot carriers in the gate-drain region will expand the depletion region towards the drain and raise the breakdown voltage (breakdown walkout). (B) The existence of the kink phenomenon indicates that trapped electrons are compensated for by holes that result from the impact ionization. This kink phenomenon may cause the threshold voltage to shift and eventually leading to device instability. (C) The carriers trapped at the AlGaAs/InGaAs heterojunction cause additional surface scattering, which leads to decreased Gm and IDS. The variations in the drop of the image force barrier height caused by the trap-related phenomena or the variation of jIGj explains the behavior of the gate leakage current. (D) According to the reverse bias characteristics of the gate-drain diode with the source floating or the source shorted with the drain, there are two major degradation mechanisms, which are coexistent: (1) the degradation of the gate-drain access resistance due to hot-electron trapping when the source is floating, and (2) the decrease of the drop of the Schottky barrier height due to hot-electron trapping under the gate or on the source side when the source and the drain are shorted. The behavior of the gate leakage current demonstrates that the hot-electron stresses will affect AlGaAs/InGaAs/GaAs PHEMTs and should be considered in high-power applications as well as low-noise applications. (E) One of the essential conditions that will induce impact ionization is a sufficiently high drain voltage. Another important condition is a sufficiently high drain current—that is, a channel current. However, according to the experimental results in Section 3.5, the effects of impact ionization after hotelectron stresses is dependent on the intensity of the impact ionization, rather than the intensity of the drain current. In other words, when the impact ionization is stronger during hot-electron stresses, the impact after hot-electron stresses will become stronger accordingly.
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The work was supported in part by the National Science Council under contracts NSC91-2215-E-006-018 and NSC93-2215-E-006-008, and the MOE Program for Promoting Academic Excellent of Universities under grant number A-91E-FA08-1-4. The Foundation of Chen, Jieh-Chen scholarship, Tainan, Taiwan, is also acknowledged for its support during this work. References [1] Aust M, Wang H, Biedenbender M, Lai R, Streit DC, Liu PH, et al. A 94-GHz monolithic balanced power amplifier using 0.1-lm gate
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Hot-electron effects on AlGaAs/InGaAs/GaAs PHEMTs under accelerated DC stresses Hou-Kuei Huang, Chou-Sern Wang, Mau-Phon Houng, Yeong-Her Wang
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Department of Electrical Engineering, National Cheng-Kung University, Tainan 701, Taiwan, ROC Received 7 September 2004; received in revised form 23 September 2005 Available online 17 April 2006
Abstract The behavior of Schottky gate characteristics before and after hot-electron stress has been a relatively neglected topic. Thus, this paper discussed the effects of hot-electron accelerated stress on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs as they relate to Schottky gate characteristics. It also presents studies of reverse Schottky gate characteristics before and after hot-electron stresses, as related to two major mechanisms: (1) the widening of the depletion region under the gate; and (2) the impact of the carriers trapped under the gate. The former induces a larger Schottky barrier height with a smaller reverse leakage current density than the latter, while the latter induces the opposite. Two hot-electron conditions are used to investigate the impact of the hot-electron stress on the gate leakage current. The gate leakage current decreases after a hot-electron stress, due the effect of hot-electron stress on the Schottky diode characteristics. Moreover, improvement in the noise performance is expected, due to the decrease in the gate leakage current. Both pre- and post-stress noise measurements have been done to demonstrate this. 2006 Elsevier Ltd. All rights reserved.
1. Introduction Pseudomorphic high electron mobility transistors (PHEMTs) have been widely used in both power and low-noise applications in the microwave and millimeter wave frequency range [1–3]. Since power PHEMTs are typically biased at high drain voltage, the reliability of devices operating under high electric fields requires in-depth examination. Although changes in the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs before and after hotelectron stresses have been extensively studied [4–8], the behavior of Schottky gate characteristics under hotelectron stresses has received far less attention. This paper investigates the DC characteristics and mechanisms for Schottky barrier variation before and after hot-electron stresses. A model related to the degradation of the image
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Corresponding author. Tel.: +886 6 2757575x62352; fax: +886 6 2080598. E-mail address: [email protected] (Y.-H. Wang). 0026-2714/$ - see front matter 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.02.013
force of the Schottky barriers is proposed to explain the mechanisms of the gate leakage current variation. The gate leakage current will be decreased after hotelectron stresses, due to the effects of hot-electron stresses on the Schottky diode characteristics. Shot noise is one of the major noise sources in HEMTs and related to the gate leakage current and the barrier control [9]. Consequently, the Schottky barrier related to gate leakage current plays an important role in low-noise applications, which requires further study. As mentioned above, improvement in noise performance is expected with decreasing gate leak current. The high electric field between the drain and the gate—that is, the drain voltage—is the essential factor for inducing the hot electrons and leads to impact ionization. However, the key parameter influencing impact ionization upon DC hot-electron stresses is the number of hot electrons relating to the drain current when the electric field between the drain and the gate is sufficiently high [10]. Two conditions are used to investigate the impact of hot-electron stresses on the gate leakage current: devices being stressed under the saturation drain
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current and devices being stressed under the maximum gate leakage current. Pre- and post-stress noise measurements under these two conditions have been done to demonstrate the effects of noise performance of AlGaAs PHEMTs after hot-electron stresses. 2. Experiments The devices used in this investigation are MBE-grown AlGaAs/InGaAs/GaAs pseudomorphic HEMTs, as shown in Fig. 1, with 0.25 lm gate length and 160 lm gate width. The PHEMT structure comprises an GaAs/Al0.25Ga0.75As/ GaAs buffer layer on (1 0 0) semi-insulating substrate, an undoped In0.15Ga0.85As channel layer, an undoped Al0.25Ga0.75As spacer layer, an n-type Al0.25Ga0.75As donor layer, an undoped Al0.25Ga0.75As Schottky layer and, finally, a heavily doped n-type GaAs cap layer. The Hall mobilities at room temperature and 77 K are 5170 and 18,700 cm2/V s, corresponding to the two-dimensional carrier densities 2.14 · 1012 and 1.98 · 1012 cm2, respectively. Devices were processed by conventional optical lithography techniques. There are three major processes in fabricating this AlGaAs PHEMT: device isolation, ohmic contact, and Schottky contact. The mesa was achieved by using HF/H2O2/H2O as the etching solution. Au/Ge/Ni was evaporated to form the source and the drain for ohmic contacts and then annealed at 420 C for 20 s on a hot plate. A HF/H2O2/H2O solution was used to remove the GaAs cap layer to fabricate the gate. Ti/Pt/Au was then deposited for the Schottky gate by lift-off processes. Finally, the devices were passivated by Si3N4. The minimum device breakdown voltage is 9 V, which is the voltage when IDG = 0.5 mA/mm when the source is floating. The maximum drain and gate voltages are 7 V and 3 V, respectively. The drain voltage and the stress current must be sufficient to excite the impact ionization, so a high drain voltage near the breakdown voltage, VDS = 7 V, and a drain current equivalent to the saturation
Fig. 1. Cross-sectional view of a PHEMT and the hot-electron phenomena in a schematic GaAs PHEMT structure.
current, VGS = 0 V, are used. The reliability study of the hot carriers is performed by stressing the devices for 60 min at room temperature. The variation of device DC parameters before and after hot-electron stresses, including drain current; IDS; transconductance, Gm; pinch-off voltage, Vp; gate current, IG; source and drain contact resistance, RS and RD; are also examined. Fig. 1 illustrates the hot-electron related phenomena in a schematic GaAs PHEMT structure. The impact ionization is triggered when the electron is hot enough to overcome the band gap; moreover, when hot-electron scattering occurs with a lattice atom, a valence band electron may gain sufficient energy to leap into the conduction band, creating a hole. Some of these holes may leap out of the valence band discontinuity and enter the donor layer. These holes may eventually be trapped in pre-existing traps or collected by the gate. The expected result is device degradation. Hot electrons and impact ionization thus represent a serious reliability concern for PHEMT. As a result, the measured gate leakage current can be used to predict the intensity of impact ionization. As described above, two conditions are used to stress these AlGaAs PHEMT devices, and the variations of gate leakage currents are measured before and after stresses. The devices are stressed under the saturation drain current, which can be realized by setting the bias on VGS = 0 V, and under the maximum gate leakage current, which is obtained from the extrapolation of the VGS bias by the bell-shaped curve of the gate leakage current, as shown in Fig. 6. Furthermore, the variations in noise performance are measured to identify the relationship between the noise performance and the gate leakage current. 3. Results and discussion 3.1. Gate-drain breakdown walkout Gate-drain breakdown (GDB) is the major limitation in the power handling capability of compound semiconductor heterostructure FETs, which are biased in the saturation region in most analog applications. Fig. 2 illustrates the
Fig. 2. The output characteristics of AlGaAs/InGaAs/GaAs PHEMTs under test before (solid line) and after (dashed line) stressing for 60 min at VDS = 7 V and VGS = 0 V.
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output characteristics of the PHEMTs being tested before and after 60 min of hot-electron stresses at VDS = 7 V and VGS = 0 V. Notably, the stresses significantly decreased the drain current, IDS, at higher drain voltages. This phenomenon is known as the breakdown walkout, and is attributed to the hot-electron effects reported by Menozzi et al. [11]. The gate-drain breakdown walkout is believed to be caused by the creation and filling of electron traps between the gate and the drain, leading to widening of the depletion region and reducing the electric field [12,13]. End resistance measurements [14] indicate that the drain-to-channel resistance, RD, will increase by approximately 12% after hot-electron stresses, while on the source side only a slight decrease in RS, 0.2%, is observed. The increase in RD is consistent with the hypothesis that the gate-drain depletion region is widened, and a slight decrease in RS indicates an increase of IDS in the saturation region resulting from the effect of threshold voltage shift, which will be discussed later. Notably, the gate-drain breakdown walkout is permanent—that is, after hotelectron stresses, the increase in RD and the decrease in RS cannot be reversed, even with long-term storage. 3.2. Existence of the kink A kink is observed at VDS near 2.5 V before and after hot-electron stresses, as shown in Fig. 2, indicating the occurrence of trapping–detrapping phenomena [15–17]. The kink position is notably shifted towards a higher VDS in accordance with the changing rates of the drain current vs. VDS, as shown in Fig. 3. The kink position shift is due to the decreased threshold voltage, which will be discussed below. Consequently, the value of the maximum electric field at the drain-to-gate area is lower in a stressed device than in an unstressed device under the same VGS [4]. 3.3. Increase of IDS in the saturation region After hot-electron stresses, most of the holes generated by the impact ionization are collected by the gate—that is, these holes are trapped under the gate, as shown in Fig. 1. Since most of the holes—that is, the positive
Fig. 3. The kink position is notably shifted towards a higher VDS due to the changing rates of the drain current vs. VDS after hot-electron stresses.
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Fig. 4. The transfer curve of AlGaAs/InGaAs/GaAs PHEMTs under test before and after stressing for 60 min at VDS = 7 V and VGS = 0 V.
charges—are accumulated under the gate, the threshold voltage shifts towards further negative VGS values. Consequently, the IDS in the saturation region will increase after hot-electron stresses. The other mechanism of the increased IDS is the reduction of the negative charges in deep traps and DX-centers, as illustrated in Fig. 4. If DIDS is only caused by the variation in the threshold voltage, DVT, then the correlation between DIDS and DVT can be explained via the following simple model: DIDS(VGS) = IDS(VGS DVT) IDS(VGS). Substituting for IDS(VGS DVT) with its first Taylor polynomial term yields IDS(VGS DVT) = IDS(VGS) Gm(VGS)DVT; thus Gm(VGS) = DIDS(VGS)/DVT [6]. When this simple model is used to fit the experimental data, significant deviations are observed, as shown in Fig. 5. This simply means that more interface undesired states, which can trap electrons, exist at the AlGaAs/InGaAs heterojunction generated by hot carrier bombardment, which reduces the channel carrier density due to the charge trapping. Hence, the effects of carriers trapped at an AlGaAs/ InGaAs heterojunction join with the effects of the threshold voltage shift, causing the stressed transfer curve to shift backward. After hot-electron stresses, the shape of Gm remained unchanged when VGS < 0.6 V, and the model perfectly fits the experimental data, as shown in Figs. 4 and 5. However, when VGS > 0.6 V, the opposite
Fig. 5. DIDS/DVT and Gm as a function of VGS. The DIDS and Gm have been calculated at VDS = 2 V.
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behavior is observed due to hot-electron stresses in the non-gate area [6], even though the model fits well with the experimental data in the low drain current range but not in the higher drain current range. The variations of RD and RS caused by the hot-electron stresses in the nongate area are negligible in the low drain current range but not in the higher drain current range. The key point is that the VT-shift analysis must be performed under the condition that the effects of hot-electron stresses in the non-gate area are negligible [6]. Consequently, when VGS > 0.6 V, the model cannot fit well with the experimental data after hot-electron stresses, as shown in Figs. 4 and 5. 3.4. Bell-shaped behavior of IG Fig. 6 illustrates IG as a function of VGS at various VDS from 5.5 to 7.5 V with 0.5 V increment. Moreover, IG represents the typical bell-shaped behavior previously noted in MESFET [18] and PHEMT [19]. In this paper, the bellshaped behavior of IG after hot-electron stresses is also discussed. After 60 min of hot-electron stress at VDS = 7 V and VGS = 0 V, jIGj decreases at all VGS with fixed VDS, as shown in Fig. 6. There are several possible explanations for this. First, the depletion region under the gate expands towards the drain after hot-electron stresses, and the widening of the depletion region reduces the maximum electric field [12,13], causing the ionization rate to decrease. Thus, jIGj decreases in the 1.2 V < VG < 0.5 V region after hot-electron stresses. Another explanation recognizes that the primary mechanisms causing reverse leakage current are (1) thermionic emission, (2) thermionic field emission, and (3) field emission. The reverse leakage current caused by thermionic emission is affected by the drop of the image-force barrier height; both thermionic field emission and field emission are tunneling mechanisms that depend on the Schottky barrier width and height [20]. The image-force barrier height lowering depends on the electric field at the metal– semiconductor interface [21]. As illustrated in Fig. 7, the electric field after hot-electron stresses, Em 0 , is smaller than
Fig. 6. Gate current versus gate bias measured at different VDS of AlGaAs/InGaAs PHEMTs before (solid line) and after (dashed line) stressing for 60 min at VDS = 7 V and VGS = 0 V.
Fig. 7. The behavior of image force height lowering after DC stress. W < W 0 ! Em > Em 0 ! DuB > DuB 0 ! jJrj (before stress) > jJrj (after stress).
the one before hot-electron stresses, Em, because the gatedrain depletion region after hot-electron stresses, W 0 , is wider than the one before hot-electron stresses, W. A smaller electric field results in a smaller image-force barrier height lowering, DuB (before stress) >DuB 0 (after stress). Therefore, the reverse leakage current also decreases, jJrj (before stress) > jJrj (after stress). Consequently, jIGj decreases in the VG < 1.2 V region as well as in the VG > 0.5 V region after hot-electron stresses. Finally, the resistance of the drain access region (RD) increases by approximately 12% after hot-electron stresses, which is consistent with the hypothesis regarding the widening of the gate-drain depletion region. Additionally, the reverse bias characteristics of the gate-drain diode with the source floating have also been measured, as shown in Fig. 8, to further establish that the gate-drain depletion region is widened by hot-electron stresses. Fig. 8 illustrates that the reverse current of the gate-drain diode with the source floating decreases after 60 min of hot-electron stresses at VDS = 7 V and VGS = 0 V. The result indicates that the image-force barrier height lowering decreases after hot-electron stresses, which is caused by widening of the gate-drain depletion region, as shown in Fig. 7. Thus, hot-electron stresses clearly widen the gate-drain depletion region. As shown in the inset of Fig. 8, the variations in the
Fig. 8. The reverse and forward (inset) bias characteristics of the gatedrain diode with the source floating and with the source and the drain shorted before and after stressing for 60 min at VDS = 7 V and VGS = 0 V.
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forward bias characteristics of the gate-drain diode with the source floating or with the source and the drain shorted are small enough to be ignored. Two major mechanisms influence the characteristics of the Schottky barrier height after hot-electron stresses. One is the widening of the depletion region, while the other is the trapping of the carriers under the gate. The widening of the depletion region under the gate reduces the peak of the electric field [12,13] and decreases the image-force barrier height lowering, leading to larger Schottky barriers. One possible explanation is that the reverse leakage current density decreases with larger Schottky barriers. Meanwhile, the trapping of carriers under the gate may cause an increase in the electric field at the metal–semiconductor interface, leading to a smaller Schottky barrier height due to the increase in image-force barrier-height lowering. Consequently, the phenomena of the reverse bias characteristics of the gate-drain diode with the source and the drain shorted are the opposite of those with the source floating, after hot-electron stresses, as shown in Fig. 8. There are two possible explanations. First, when the source is floating, the effect of the widening of the depletion region dominates the device characteristics, leading to a larger Schottky barrier height and a smaller reverse leakage current after hot-electron stresses, as illustrated in Fig. 8. Alternatively, when the source and the drain are shorted, the effect of trapping carriers becomes the dominant mechanism, leading to a smaller Schottky barrier height and a larger reverse leakage current after hot-electron stresses, as also shown in Fig. 8. 3.5. IG and noise performance after two different hot-electron stresses The effects of drain-to-gate reverse current after different hot-electron stresses with the source floating are shown in Fig. 9. Twenty devices from the same wafer were stressed with the first ten stresses at VDS = 7 V and VG = 0 V and
Fig. 9. The degradation of the gate leakage currents after two different stress conditions. (d) stressed for 60 min at VDS = 5 V and VGS = 0 V; (m) stressed for 60 min at VDS = 7 V and VG at the maximum gate leakage current. The range of IDSS: 45 to 55 mA. The range of the maximum gate leakage current: 156 to 225 lA.
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the other ten at VDS = 7 V and VG at the maximum gate leakage current stress. The circular notation indicates the IDG degradation ratio after stressing for 60 min at VDS = 7 V and VG = 0 V, i.e., IDS = IDSS. The average degradation ratio of IDG for these ten devices is 11%. The triangular notation indicates the IDG degradation ratio after stressing for 60 min at VDS = 7 V and VG at the maximum gate leakage current—that is, IDS < IDSS. The average degradation ratio of IDG is 13.47%. The ratio of the stressed current, IDS, to the saturation current, IDSS, for each sample ranges from 23% to 65%. The IDSS of these samples ranges from 48 to 53 mA. Meanwhile, the drain-to-gate current with a fixed VDG of 10 V ranges from 86 to 125 lA. Due to the higher degradation ratio of IDG, the stressed condition of the maximum gate leakage current, IDS < IDSS, becomes more severe. A higher degradation ratio of IDG is caused by a wider depletion region. The major sources of the noise of PHEMT have been attributed to (1) thermal noise; (2) shot noise related to the current controlled by a barrier; (3) generation–recombination noise induced by random transitions between the band and the traps, causing fluctuations of mobile electrons; and (4) hot-electron noise associated with the ultrafast kinetic processes of dissipation within the conduction band [9]. The last three sources of noise are essentially related to frequencies corresponding to the microwave and millimeter-wave ranges [9]. The major factor in the variations of noise performance after hot-electron stresses for these three noise sources is the carrier behaviors, which are related to trapping/detrapping phenomena. One of the effects of the hot-electron stresses is the degradation of the drain-to-gate reverse current, IGD–that is, the decrease of the gate leakage current, which is also related to trapping/detrapping phenomena. In other words, the reduction of generation-recombination phenomena can be expected after hot-electron stresses. Consequently, noise performance will improve. As mentioned above, the minimum noise figure, NFmin and the associated power gain, Ga, were measured to confirm the degradation of the drain-to-gate reverse current, IGD, and to show the improvement of the noise performance by subtracting NFmin (before stresses) from NFmin (after stresses). In Fig. 10, the circular and triangular notations indicate the NFmin improvement after stressing for 60 min at VDS = 7 V and VG = 0 V, and after stressing for 60 min at VDS = 7 V and VG at the maximum gate leakage current, respectively. The averages of these NFmin improvements are 0.0148 dB and 0.0074 dB, respectively. The NFmin of these samples ranged from 0.46 to 0.52 dB before stress. The average of variations of Ga is between 0.05 and +0.15 dB. The Ga of these samples ranged from 12.51 to 13.22 dB before stress. The experimental results indicate that the better improvement of NFmin under stresses is at VDS = 7 V and VG at the maximum gate leakage current. Compared with the stress condition of VDS = 7 V and VG = 0 V, the stress condition of VG at the maximum gate leakage current can excite a stronger
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Fig. 10. The improvement of the minimum noise figure by subtracting NFmin (before stress) from NFmin (after stress) under two different stress conditions. (d) stressed for 60 min at VDS = 5 V and VGS = 0 V; (m) stressed for 60 min at VDS = 7 V and VG at the maximum gate leakage current. The frequency is 12 GHz and the DC bias is VDS = 2 V and ID = 10 mA.
impact ionization. When the impact ionization is stronger during hot-electron stresses, the impact after hot-electron stresses will become stronger accordingly. Notably, the effectiveness of hot-electron stresses is not directly proportional to the drain current. This noise performance improvement corresponds with the decrease of the gate leakage currents previously discussed.
Fig. 11. (a) Stress time dependence of the current–voltage characteristics. (b) Greater resolution in drain current at high drain voltage region as VGS = 0.6 V.
3.6. Stressed time dependence of the DC characteristics The stressed time dependence of the current–voltage characteristics is shown in Fig. 11(a) and (b). The stressed time dependence of IG is revealed from the bell-shaped behaviors shown in Fig. 12. The stress times are 30, 60, 240 and 600 min The variations of the drain current and the gate leakage current can be explained as follows: (1) As mentioned in Section 3.3, the increased drain current is observed in the low drain voltage region. The shifting of the threshold voltage, which is caused by the trapped holes under the gate, can be used to explain the increase of the drain current. Since the trapped holes are almost saturated during the first 30 min of stressing, the shifting rate of the threshold voltage is the fastest. Moreover, the shifting values of threshold voltages are almost the same at the other stressed times. Consequently, the changing rate of the drain current is also the fastest during the first 30 min of stressing. However, when the stressed times are 60, 240 and 600 min, the variations of the drain current are negligible, as shown in Fig. 11(a). (2) As mentioned in Section 3.1, the decreased drain current is observed in the high drain voltage region—that is, the drain-to-gate voltage close to the breakdown voltage. The widening of the depletion region and the drop in the Schottky barrier height lowering effect can be used to explain the decrease in the drain current. The decreased gate leakage current is also related to the widening of the depletion region, which is caused by creating and filling
Fig. 12. Stressed time dependence of IG is revealed from the bell-shaped behaviors.
electron traps between the gate and the drain. The region affected by impact ionization between the gate and the drain is limited. The created and filling electron traps are almost saturated during the first 30 min of stressing; therefore, the widening rate of the depletion region is the fastest during the first 30 min of stressing. Consequently, the widening rate of the depletion region decreases at the other stressed times. As shown in Fig. 11(b), the longer the stressed time, the lower the drain current in the high drain voltage region. Similarly, as shown in Fig. 12, the longer the stressed time, the lower the maximum gate leakage current in the high drain voltage region. In other words, the impact ionization under high drain voltage bias will be reduced after hot-electron stresses.
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4. Conclusions This work has studied the most important mechanisms of hot-electron stresses on the DC characteristics of AlGaAs/InGaAs/GaAs PHEMTs. The analytical results indicate that the trap-related phenomena can be divided into five major categories. (A) Filling and depletion of traps generated by hot carriers in the gate-drain region will expand the depletion region towards the drain and raise the breakdown voltage (breakdown walkout). (B) The existence of the kink phenomenon indicates that trapped electrons are compensated for by holes that result from the impact ionization. This kink phenomenon may cause the threshold voltage to shift and eventually leading to device instability. (C) The carriers trapped at the AlGaAs/InGaAs heterojunction cause additional surface scattering, which leads to decreased Gm and IDS. The variations in the drop of the image force barrier height caused by the trap-related phenomena or the variation of jIGj explains the behavior of the gate leakage current. (D) According to the reverse bias characteristics of the gate-drain diode with the source floating or the source shorted with the drain, there are two major degradation mechanisms, which are coexistent: (1) the degradation of the gate-drain access resistance due to hot-electron trapping when the source is floating, and (2) the decrease of the drop of the Schottky barrier height due to hot-electron trapping under the gate or on the source side when the source and the drain are shorted. The behavior of the gate leakage current demonstrates that the hot-electron stresses will affect AlGaAs/InGaAs/GaAs PHEMTs and should be considered in high-power applications as well as low-noise applications. (E) One of the essential conditions that will induce impact ionization is a sufficiently high drain voltage. Another important condition is a sufficiently high drain current—that is, a channel current. However, according to the experimental results in Section 3.5, the effects of impact ionization after hotelectron stresses is dependent on the intensity of the impact ionization, rather than the intensity of the drain current. In other words, when the impact ionization is stronger during hot-electron stresses, the impact after hot-electron stresses will become stronger accordingly.
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The work was supported in part by the National Science Council under contracts NSC91-2215-E-006-018 and NSC93-2215-E-006-008, and the MOE Program for Promoting Academic Excellent of Universities under grant number A-91E-FA08-1-4. The Foundation of Chen, Jieh-Chen scholarship, Tainan, Taiwan, is also acknowledged for its support during this work. References [1] Aust M, Wang H, Biedenbender M, Lai R, Streit DC, Liu PH, et al. A 94-GHz monolithic balanced power amplifier using 0.1-lm gate
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