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GaN MISFET with selective area-recessed floating gate
Solid-State Electronics 95 (2014) 42–45
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Letter
Normally-off dual gate AlGaN/GaN MISFET with selective area-recessed floating gate Ho-Kyun Ahn a,c,⇑, Zin-Sig Kim a, Sung-Bum Bae a, Hae-Cheon Kim a, Dong-Min Kang a, Sung-Il Kim a, Jong-Min Lee a, Byoung-Gue Min a, Hyoung-Sup Yoon a, Jong-Won Lim a, Yong-Hwan Kwon a, Eun-Soo Nam a, Hyung-Moo Park b, Hyun-Seok Kim b, Jung-Hee Lee c a
Convergence Components and Materials Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea The Division of Electronics and Electrical Engineering, Dongguk University, Seoul, Republic of Korea c The School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Republic of Korea b
a r t i c l e
i n f o
Article history: Received 23 November 2013 Received in revised form 28 February 2014 Accepted 21 March 2014 Available online 17 April 2014 The review of this paper was arranged by Prof. E. Calleja Keywords: GaN Normally off MISFET Floating gate Off-state performance On-state performance
a b s t r a c t This paper demonstrates normally-off dual gate AlGaN/GaN MISFETs with a selective area-recessed floating gate fabricated on the AlGaN/GaN-based heterostructure with an AlN insertion layer. For the fabrication of the dual gate structure, the AlGaN layer in the control gate region was fully recessed and then an Al2O3 layer as a gate dielectric was deposited by the atomic layer deposition method, which ensures the normally-off operation and greatly decreases the leakage current. An additional floating gate with selective area-recessed patterns, which is located between the control gate and the drain electrode, was employed to enhance the breakdown voltage. The fabricated normally-off dual gate AlGaN/GaN MISFET exhibited a threshold voltage of 2 V, a high ION/IOFF ratio of 3 108 at a drain voltage of 10 V, a maximum transconductance of 88 mS/mm at a gate voltage of 5.8 V, a drain current density of 364 mA/mm at a gate voltage of 8 V, and a breakdown voltage of 880 V. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Wide bandgap semiconductors like GaN and SiC are regarded as attractive candidate materials for high frequency and high power electronics applications owing to their excellent material properties such as a high critical electric field and a high saturation velocity. In particular, AlGaN/GaN heterostructure field effect transistor (HFET) with high two dimensional electron gas (2-DEG) carrier concentration exhibits not only high breakdown characteristics, but also low on-resistance and high switching speed. However, applying a positive voltage to the gate is limited below the turn-on voltage of the gate Schottky contact on the AlGaN barrier and hence the device usually operates in normally-on mode, which is undesirable for power electronics applications because the normally-on operation increases the static power loss and makes driving circuit very complicate. ⇑ Corresponding author at: RF Convergence Component Research Section, Convergence Components and Materials Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea. Tel.: +82 42 860 6135; fax: +82 42 860 6248. E-mail address: [email protected] (H.-K. Ahn). http://dx.doi.org/10.1016/j.sse.2014.03.005 0038-1101/Ó 2014 Elsevier Ltd. All rights reserved.
Many efforts have been given to realize a normally-off AlGaN/ GaN HFET since Khan et al. reported the first enhancement-mode AlGaN/GaN HFET in 1996, which can be usually realized by depleting the 2-DEG in the gate region [1–4]. The typical methods include the F plasma treatment for the gate region, the addition of a P-GaN gate layer on the AlGaN layer, and the recessed gate structure with an appropriate gate insulator to form a metal– insulator-semiconductor field effect transistor (MISFET) structure [5–10]. In this work, we have proposed a normally-off dual gate AlGaN/ GaN MISFET, which has a control gate formed on the fully recessed gate region and a selective area-recessed floating gate (SRFG) located between the control gate and the drain electrodes. Prior to the gate metal deposition, high quality Al2O3 layer as a gate insulator was deposited by atomic layer deposition (ALD) method after the gate recess. Most of this work was thus focused on the comparison of the breakdown voltage between devices with and without SRFG [11–13]. The fabricated AlGaN/GaN MISFET shows normally-off operation with a threshold voltage of 2 V, low leakage current of 9.4 107 mA/mm, high ION/IOFF ratio of 3 108, and enhanced blocking capability with breakdown voltage of 880 V.
H.-K. Ahn et al. / Solid-State Electronics 95 (2014) 42–45
43
Fig. 1. (a) Cross-sectional images of the selective area-recessed (along the line B–B0 ) and the non-recessed regions (along the line A–A0 ) of the fabricated device and (b) planar image of the fabricated device including the selective area-recessed floating gate.
2. Experiments The AlGaN/GaN heterostructure was grown on 2-in. sapphire substrates using metal–organic chemical vapor deposition (MOCVD), which consists of low-temperature initial nucleation layer, 2.7 lm-thick semi-insulating GaN buffer layer, 0.1 lm-thick GaN channel layer, 1 nm-thick AlN interfacial layer, and 20 nm-thick undoped AlGaN barrier layer in growth sequence. The proposed normally-off GaN MISFET was fabricated by depositing Al2O3 layer as a gate dielectric on the fully recessed gate region. Both the mesa and the gate recess etching were carried out using inductively coupled plasma (ICP) with a mixture of BCl3 and Cl2 gas. A 30 nm-thick Al2O3 gate dielectric was then deposited using ALD technique. For source and drain ohmic contact, Ti/Al/Ni/Au metal stack was evaporated using an e-beam evaporation and annealed at a temperature of 850 °C for 30 s in N2 ambient. Finally, the electrodes for the control and the floating gates were formed by depositing Ni/Au metals. Fig. 1(a) and (b) shows the schematic cross-sectional and planar images for the fabricated device, respectively. The gate length and the width of the fabricated device were 3 and 100 lm (50 lm 2 fingers), respectively. The distance between the control gate and the source electrode was 2 lm and the distance between the control gate and the drain electrode was 20 lm. The floating gate located at the distance of 3 lm from the control gate has selective area-recessed patterns with 3 3 lm2 square shapes. Two recessed patterns were overlapped with the mesa boundary at both
edges of the floating gate and others were located inside the mesaregion with a uniform spacing of 3 lm. The length and the width of the floating gate were 3.5 and 50 lm, respectively. The design and the role of the SRFG will be discussed later. The device characteristics of the fabricated normally-off AlGaN/GaN MISFET were measured using an HP4156B and a Sony A370 [14,15]. 3. Results and discussion Fig. 2(a) shows the normalized transfer characteristics with hysteresis of as low as 0.1 V and extrinsic transconductance (gm) at drain-to-source voltage of Vds = 10 V for the fabricated device and the inset in the figure represents the corresponding Ids–Vds characteristics for the device. The device exhibited a normally-off operation with a threshold voltage of 2 V, the maximum transconductance of 88 mS/mm, measured at Vds = 10 V and Vgs = 5.8 V, and the drain current of 364 mA/mm, measured at Vds = 10 V and Vgs = 8 V, respectively. The low hysteresis explains that the interfacial properties between the gate oxide and the recessed GaN were sufficiently good to form a low interface state density. Logarithmic transfer Ids–Vgs characteristic was shown in Fig. 2(b). The device also exhibited excellent off-state performances such as off-state leakage current of as low as 9.4 107 mA/mm at Vgs = 0 V with high ION/IOFF ratio of 3 108 and subthreshold slope (SS) of as low as 148 mV/dec. This low SS also is related to the low interface state density between the gate
Fig. 2. (a) The transfer curve of the fabricated device. The inset represents I–V characteristics. (b) Logarithmic scale of drain current at Vds = 10 V as a function of gate-to-source voltage. The inset represents the logarithmic scale of gate leakage current as a function of gate-to-source voltage.
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H.-K. Ahn et al. / Solid-State Electronics 95 (2014) 42–45
Fig. 3. (a) The breakdown characteristics and (b) The drain current at Vds = 10 V as a function of source-to-gate voltage for the fabricated normally-off AlGaN/GaN MISFET with SRFG and without any additional gate.
oxide and the recessed GaN surface [6]. The fabricated device exhibited a low gate leakage current less than 2 107 A/mm, as shown in inset of Fig. 2(b), which shows that the quality of the gate oxide itself is high. Fig. 3(a) shows the breakdown characteristics of the normallyoff AlGaN/GaN MISFETs with and without SRFG. The breakdown voltage of the device with SRFG was increased to 880 V from the value of 689 V for the device without SRFG. The breakdown voltage of 880 V obtained from our device is somewhat lower than previous results with a similar gate-to-drain distance [16]. This is probably due to the low resistance of the GaN buffer layer investigated in this work. If the resistance of the semiinsulating GaN buffer layer is not high enough, the device may suffer from relatively large buffer leakage current and hence experience lower breakdown voltage than expected. We believe that the breakdown voltage can be increased if a high resistance buffer layer is used. Careful investigation of the destroyed device after breakdown indicated that most breakdown failure was initiated at both edges of the control gate located at mesa boundaries (designated as weak point in Fig. 1). In spite of the apparent increase in breakdown voltage, however, the use of SRFG did not degrade the on-current of the device, as shown in Fig. 3(b), except at high gate voltages larger than 10 V. The decrease of the on-current is about only 5.4% at Vds = 10 V and Vgs = 12 V. The measured static on-resistance (Ron) for both devices were about 31.5 X mm regardless of the application of SRFG. Instead, the dynamic Ron, measured with pulse width of 0.5 ls, for the device with SRFG slightly increased from the value of 32.4 X mm for the device without SRFG, to 34.1 X mm of only
1.05 times higher Ron, which explains that the application of the SRFG results in negligible degradation of the Ron. The increase of the breakdown voltage of the device with SRFG is due to the decreased peak electric field at the control gate edge. The simulation results shown in Fig. 4 clearly explains that the use of the SRFG greatly decreases the electric field at both ends (weak points) of the control gate at the mesa boundary to effectively increase the breakdown voltage of the device. This simulation data was verified under the condition of Vds = 150 V and Vg = 4 V for three different cases, for the case without SRFG and the cases with SRFG both in the non-recessed and the recessed region. The peak value of the electric field at the drain side edge of the control gate electrode was 3.6 106 V/cm for the device when the floating gate was absent. After application of the SRFG, the peak value at the drain side edge of the control gate was slightly lowered to 3.5 106 V/cm along the line A–A’ (non-recessed), but the corresponding value along the line B–B’ (recessed) was greatly decreased to about 4.7 105 V/cm. It is believed that the greatly decreased peak electric field along the line B–B’ is responsible for the increase in the measured breakdown voltage of the device. Therefore, the proposed SRFG structure can improve the blocking capability of the normally-off AlGaN/GaN-based MISFET without degrading the on-state performances. 4. Conclusion A normally-off dual-gate AlGaN/GaN MISFET with a SRFG was proposed. The fabricated device exhibited a threshold voltage of 2 V, a high ION/IOFF ratio of 3 108 at a drain voltage of 10 V, a maximum transconductance of 88 mS/mm, and a drain current density of 364 mA/mm at a gate voltage of 8 V. With the SRFG, the fabricated device exhibited an enhanced blocking capability with a breakdown voltage of 880 V. The simulation results indicated that the increase of breakdown voltage for the device with the SRFG may be attributed to the lowered peak electric field at the drain side edge of gate electrode, especially at the mesa boundary of the control gate. References
Fig. 4. Electric field distribution between source and drain electrodes (for only control gate and dual gate along the line B–B0 including the recessed region of SRFG and along the line A–A0 including the non-recessed region of SRFG).
[1] Asif Khan M, Chen Q, Sun CJ, Yang JW, Blasingame M, Shur MS, et al. Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors. Appl Phys Lett 1996;68(4):514–6. [2] Cai Y, Zhou Y, Chen KJ, Lau KM. High performance enhancement-mode AlGaN/ GaN HEMts using fluoride-based plasma treatment. IEEE Electron Dev Lett 2005;26(7):435–7. [3] Saito W, Takada Y, Kuraguchi M, Tsuda K, Omura I. Recessed-gate structure approach toward normally-off high-voltage AlGaN/GaN HEMT for power electronics applications. IEEE Trans Electron Dev 2006;53(2):356–62.
H.-K. Ahn et al. / Solid-State Electronics 95 (2014) 42–45 [4] Wang R, Cai Y, Tang C-W, Lau KM, Kevin KJ. Enhancement-mode Si3N4/AlGaN/ GaN MISFETs. IEEE Electron Dev Lett 2006;27(10):793–5. [5] Corrion AL, Chen M, Chu R, et al., Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric. In: Proc. device research conf. 2011. p. 213-214. [6] Chu Rongming, Corrion A, Chen M, et al. 1200 V Normally-off GaN-on-Si fieldeffect transistors with low DYNAMIC on-resistance. IEEE Electron Dev Lett 2011;32(5):632–4. [7] Chen KJ. GaN Smart power chip technology. In: Proc. int. conf. electron device and solid-state circuits. 2009. p. 403-407. [8] Wong KY, Chen WJ, Chen KJ. Integrated voltage reference generator for GaN smart power chip technology. IEEE Trans Electron Dev 2010;57(4):952–5. [9] Uemoto Y, Hikita M, Ueno H, et al. Gate injection transistor (GIT)-A normallyoff AlGaN/GaN power transistor using conductivity modulation. IEEE Trans Electron Dev 2007;54(12):3393–9. [10] Hilt O, Brunner F, Cho E, et al. Normally-off high voltage p-GaN gate GaN HFET with carbon-doped buffer. In: Proc. int. symp. power semicond. devices and ICs. 2011. p. 239-242.
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[11] Saito W, Kakiuchi Y, Nitta T, et al. Field-plate structure dependence of current collapse phenomena in high-voltage GaN HEMTs. IEEE Electron Dev Lett 2010;31(7):659–61. [12] Okamoto Y, Ando Y, Nakayama T, et al. High-power recessed-gate AlGaN-GaN HFET with a field-modulating plate. IEEE Trans Electron Dev 2004;51(12):2217–22. [13] Lim J, Choi YH, Kim YS, et al. New AlGaN/GaN HEMTs employing both a floating gate and a field. Phys Scr 2010;T141:014009. [14] Kim DS, Ha JB, Kim SN, et al. Normally-off operation of Al2O3/GaN MOSFET based on AlGaN/GaN heterostructure with p-GaN buffer layer. In: Proc. int. symp. power semicond. devices and ICs. 2010. p. 229-231. [15] Im KS, Ha JB, Kim KW, et al. Normally-off GaN MOSFET based on AlGaN/GaN heterostructure with extremely high 2DEG density grown on silicon substrate. IEEE Electron Dev Lett 2010;31(3):192–4. [16] Corrion AL, Chen M, Chu R, et al. Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric DRC. 2011. p. 213-214.
Contents lists available at ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
Letter
Normally-off dual gate AlGaN/GaN MISFET with selective area-recessed floating gate Ho-Kyun Ahn a,c,⇑, Zin-Sig Kim a, Sung-Bum Bae a, Hae-Cheon Kim a, Dong-Min Kang a, Sung-Il Kim a, Jong-Min Lee a, Byoung-Gue Min a, Hyoung-Sup Yoon a, Jong-Won Lim a, Yong-Hwan Kwon a, Eun-Soo Nam a, Hyung-Moo Park b, Hyun-Seok Kim b, Jung-Hee Lee c a
Convergence Components and Materials Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea The Division of Electronics and Electrical Engineering, Dongguk University, Seoul, Republic of Korea c The School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Republic of Korea b
a r t i c l e
i n f o
Article history: Received 23 November 2013 Received in revised form 28 February 2014 Accepted 21 March 2014 Available online 17 April 2014 The review of this paper was arranged by Prof. E. Calleja Keywords: GaN Normally off MISFET Floating gate Off-state performance On-state performance
a b s t r a c t This paper demonstrates normally-off dual gate AlGaN/GaN MISFETs with a selective area-recessed floating gate fabricated on the AlGaN/GaN-based heterostructure with an AlN insertion layer. For the fabrication of the dual gate structure, the AlGaN layer in the control gate region was fully recessed and then an Al2O3 layer as a gate dielectric was deposited by the atomic layer deposition method, which ensures the normally-off operation and greatly decreases the leakage current. An additional floating gate with selective area-recessed patterns, which is located between the control gate and the drain electrode, was employed to enhance the breakdown voltage. The fabricated normally-off dual gate AlGaN/GaN MISFET exhibited a threshold voltage of 2 V, a high ION/IOFF ratio of 3 108 at a drain voltage of 10 V, a maximum transconductance of 88 mS/mm at a gate voltage of 5.8 V, a drain current density of 364 mA/mm at a gate voltage of 8 V, and a breakdown voltage of 880 V. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Wide bandgap semiconductors like GaN and SiC are regarded as attractive candidate materials for high frequency and high power electronics applications owing to their excellent material properties such as a high critical electric field and a high saturation velocity. In particular, AlGaN/GaN heterostructure field effect transistor (HFET) with high two dimensional electron gas (2-DEG) carrier concentration exhibits not only high breakdown characteristics, but also low on-resistance and high switching speed. However, applying a positive voltage to the gate is limited below the turn-on voltage of the gate Schottky contact on the AlGaN barrier and hence the device usually operates in normally-on mode, which is undesirable for power electronics applications because the normally-on operation increases the static power loss and makes driving circuit very complicate. ⇑ Corresponding author at: RF Convergence Component Research Section, Convergence Components and Materials Research Laboratory, Electronics and Telecommunications Research Institute, Daejeon, Republic of Korea. Tel.: +82 42 860 6135; fax: +82 42 860 6248. E-mail address: [email protected] (H.-K. Ahn). http://dx.doi.org/10.1016/j.sse.2014.03.005 0038-1101/Ó 2014 Elsevier Ltd. All rights reserved.
Many efforts have been given to realize a normally-off AlGaN/ GaN HFET since Khan et al. reported the first enhancement-mode AlGaN/GaN HFET in 1996, which can be usually realized by depleting the 2-DEG in the gate region [1–4]. The typical methods include the F plasma treatment for the gate region, the addition of a P-GaN gate layer on the AlGaN layer, and the recessed gate structure with an appropriate gate insulator to form a metal– insulator-semiconductor field effect transistor (MISFET) structure [5–10]. In this work, we have proposed a normally-off dual gate AlGaN/ GaN MISFET, which has a control gate formed on the fully recessed gate region and a selective area-recessed floating gate (SRFG) located between the control gate and the drain electrodes. Prior to the gate metal deposition, high quality Al2O3 layer as a gate insulator was deposited by atomic layer deposition (ALD) method after the gate recess. Most of this work was thus focused on the comparison of the breakdown voltage between devices with and without SRFG [11–13]. The fabricated AlGaN/GaN MISFET shows normally-off operation with a threshold voltage of 2 V, low leakage current of 9.4 107 mA/mm, high ION/IOFF ratio of 3 108, and enhanced blocking capability with breakdown voltage of 880 V.
H.-K. Ahn et al. / Solid-State Electronics 95 (2014) 42–45
43
Fig. 1. (a) Cross-sectional images of the selective area-recessed (along the line B–B0 ) and the non-recessed regions (along the line A–A0 ) of the fabricated device and (b) planar image of the fabricated device including the selective area-recessed floating gate.
2. Experiments The AlGaN/GaN heterostructure was grown on 2-in. sapphire substrates using metal–organic chemical vapor deposition (MOCVD), which consists of low-temperature initial nucleation layer, 2.7 lm-thick semi-insulating GaN buffer layer, 0.1 lm-thick GaN channel layer, 1 nm-thick AlN interfacial layer, and 20 nm-thick undoped AlGaN barrier layer in growth sequence. The proposed normally-off GaN MISFET was fabricated by depositing Al2O3 layer as a gate dielectric on the fully recessed gate region. Both the mesa and the gate recess etching were carried out using inductively coupled plasma (ICP) with a mixture of BCl3 and Cl2 gas. A 30 nm-thick Al2O3 gate dielectric was then deposited using ALD technique. For source and drain ohmic contact, Ti/Al/Ni/Au metal stack was evaporated using an e-beam evaporation and annealed at a temperature of 850 °C for 30 s in N2 ambient. Finally, the electrodes for the control and the floating gates were formed by depositing Ni/Au metals. Fig. 1(a) and (b) shows the schematic cross-sectional and planar images for the fabricated device, respectively. The gate length and the width of the fabricated device were 3 and 100 lm (50 lm 2 fingers), respectively. The distance between the control gate and the source electrode was 2 lm and the distance between the control gate and the drain electrode was 20 lm. The floating gate located at the distance of 3 lm from the control gate has selective area-recessed patterns with 3 3 lm2 square shapes. Two recessed patterns were overlapped with the mesa boundary at both
edges of the floating gate and others were located inside the mesaregion with a uniform spacing of 3 lm. The length and the width of the floating gate were 3.5 and 50 lm, respectively. The design and the role of the SRFG will be discussed later. The device characteristics of the fabricated normally-off AlGaN/GaN MISFET were measured using an HP4156B and a Sony A370 [14,15]. 3. Results and discussion Fig. 2(a) shows the normalized transfer characteristics with hysteresis of as low as 0.1 V and extrinsic transconductance (gm) at drain-to-source voltage of Vds = 10 V for the fabricated device and the inset in the figure represents the corresponding Ids–Vds characteristics for the device. The device exhibited a normally-off operation with a threshold voltage of 2 V, the maximum transconductance of 88 mS/mm, measured at Vds = 10 V and Vgs = 5.8 V, and the drain current of 364 mA/mm, measured at Vds = 10 V and Vgs = 8 V, respectively. The low hysteresis explains that the interfacial properties between the gate oxide and the recessed GaN were sufficiently good to form a low interface state density. Logarithmic transfer Ids–Vgs characteristic was shown in Fig. 2(b). The device also exhibited excellent off-state performances such as off-state leakage current of as low as 9.4 107 mA/mm at Vgs = 0 V with high ION/IOFF ratio of 3 108 and subthreshold slope (SS) of as low as 148 mV/dec. This low SS also is related to the low interface state density between the gate
Fig. 2. (a) The transfer curve of the fabricated device. The inset represents I–V characteristics. (b) Logarithmic scale of drain current at Vds = 10 V as a function of gate-to-source voltage. The inset represents the logarithmic scale of gate leakage current as a function of gate-to-source voltage.
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H.-K. Ahn et al. / Solid-State Electronics 95 (2014) 42–45
Fig. 3. (a) The breakdown characteristics and (b) The drain current at Vds = 10 V as a function of source-to-gate voltage for the fabricated normally-off AlGaN/GaN MISFET with SRFG and without any additional gate.
oxide and the recessed GaN surface [6]. The fabricated device exhibited a low gate leakage current less than 2 107 A/mm, as shown in inset of Fig. 2(b), which shows that the quality of the gate oxide itself is high. Fig. 3(a) shows the breakdown characteristics of the normallyoff AlGaN/GaN MISFETs with and without SRFG. The breakdown voltage of the device with SRFG was increased to 880 V from the value of 689 V for the device without SRFG. The breakdown voltage of 880 V obtained from our device is somewhat lower than previous results with a similar gate-to-drain distance [16]. This is probably due to the low resistance of the GaN buffer layer investigated in this work. If the resistance of the semiinsulating GaN buffer layer is not high enough, the device may suffer from relatively large buffer leakage current and hence experience lower breakdown voltage than expected. We believe that the breakdown voltage can be increased if a high resistance buffer layer is used. Careful investigation of the destroyed device after breakdown indicated that most breakdown failure was initiated at both edges of the control gate located at mesa boundaries (designated as weak point in Fig. 1). In spite of the apparent increase in breakdown voltage, however, the use of SRFG did not degrade the on-current of the device, as shown in Fig. 3(b), except at high gate voltages larger than 10 V. The decrease of the on-current is about only 5.4% at Vds = 10 V and Vgs = 12 V. The measured static on-resistance (Ron) for both devices were about 31.5 X mm regardless of the application of SRFG. Instead, the dynamic Ron, measured with pulse width of 0.5 ls, for the device with SRFG slightly increased from the value of 32.4 X mm for the device without SRFG, to 34.1 X mm of only
1.05 times higher Ron, which explains that the application of the SRFG results in negligible degradation of the Ron. The increase of the breakdown voltage of the device with SRFG is due to the decreased peak electric field at the control gate edge. The simulation results shown in Fig. 4 clearly explains that the use of the SRFG greatly decreases the electric field at both ends (weak points) of the control gate at the mesa boundary to effectively increase the breakdown voltage of the device. This simulation data was verified under the condition of Vds = 150 V and Vg = 4 V for three different cases, for the case without SRFG and the cases with SRFG both in the non-recessed and the recessed region. The peak value of the electric field at the drain side edge of the control gate electrode was 3.6 106 V/cm for the device when the floating gate was absent. After application of the SRFG, the peak value at the drain side edge of the control gate was slightly lowered to 3.5 106 V/cm along the line A–A’ (non-recessed), but the corresponding value along the line B–B’ (recessed) was greatly decreased to about 4.7 105 V/cm. It is believed that the greatly decreased peak electric field along the line B–B’ is responsible for the increase in the measured breakdown voltage of the device. Therefore, the proposed SRFG structure can improve the blocking capability of the normally-off AlGaN/GaN-based MISFET without degrading the on-state performances. 4. Conclusion A normally-off dual-gate AlGaN/GaN MISFET with a SRFG was proposed. The fabricated device exhibited a threshold voltage of 2 V, a high ION/IOFF ratio of 3 108 at a drain voltage of 10 V, a maximum transconductance of 88 mS/mm, and a drain current density of 364 mA/mm at a gate voltage of 8 V. With the SRFG, the fabricated device exhibited an enhanced blocking capability with a breakdown voltage of 880 V. The simulation results indicated that the increase of breakdown voltage for the device with the SRFG may be attributed to the lowered peak electric field at the drain side edge of gate electrode, especially at the mesa boundary of the control gate. References
Fig. 4. Electric field distribution between source and drain electrodes (for only control gate and dual gate along the line B–B0 including the recessed region of SRFG and along the line A–A0 including the non-recessed region of SRFG).
[1] Asif Khan M, Chen Q, Sun CJ, Yang JW, Blasingame M, Shur MS, et al. Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors. Appl Phys Lett 1996;68(4):514–6. [2] Cai Y, Zhou Y, Chen KJ, Lau KM. High performance enhancement-mode AlGaN/ GaN HEMts using fluoride-based plasma treatment. IEEE Electron Dev Lett 2005;26(7):435–7. [3] Saito W, Takada Y, Kuraguchi M, Tsuda K, Omura I. Recessed-gate structure approach toward normally-off high-voltage AlGaN/GaN HEMT for power electronics applications. IEEE Trans Electron Dev 2006;53(2):356–62.
H.-K. Ahn et al. / Solid-State Electronics 95 (2014) 42–45 [4] Wang R, Cai Y, Tang C-W, Lau KM, Kevin KJ. Enhancement-mode Si3N4/AlGaN/ GaN MISFETs. IEEE Electron Dev Lett 2006;27(10):793–5. [5] Corrion AL, Chen M, Chu R, et al., Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric. In: Proc. device research conf. 2011. p. 213-214. [6] Chu Rongming, Corrion A, Chen M, et al. 1200 V Normally-off GaN-on-Si fieldeffect transistors with low DYNAMIC on-resistance. IEEE Electron Dev Lett 2011;32(5):632–4. [7] Chen KJ. GaN Smart power chip technology. In: Proc. int. conf. electron device and solid-state circuits. 2009. p. 403-407. [8] Wong KY, Chen WJ, Chen KJ. Integrated voltage reference generator for GaN smart power chip technology. IEEE Trans Electron Dev 2010;57(4):952–5. [9] Uemoto Y, Hikita M, Ueno H, et al. Gate injection transistor (GIT)-A normallyoff AlGaN/GaN power transistor using conductivity modulation. IEEE Trans Electron Dev 2007;54(12):3393–9. [10] Hilt O, Brunner F, Cho E, et al. Normally-off high voltage p-GaN gate GaN HFET with carbon-doped buffer. In: Proc. int. symp. power semicond. devices and ICs. 2011. p. 239-242.
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[11] Saito W, Kakiuchi Y, Nitta T, et al. Field-plate structure dependence of current collapse phenomena in high-voltage GaN HEMTs. IEEE Electron Dev Lett 2010;31(7):659–61. [12] Okamoto Y, Ando Y, Nakayama T, et al. High-power recessed-gate AlGaN-GaN HFET with a field-modulating plate. IEEE Trans Electron Dev 2004;51(12):2217–22. [13] Lim J, Choi YH, Kim YS, et al. New AlGaN/GaN HEMTs employing both a floating gate and a field. Phys Scr 2010;T141:014009. [14] Kim DS, Ha JB, Kim SN, et al. Normally-off operation of Al2O3/GaN MOSFET based on AlGaN/GaN heterostructure with p-GaN buffer layer. In: Proc. int. symp. power semicond. devices and ICs. 2010. p. 229-231. [15] Im KS, Ha JB, Kim KW, et al. Normally-off GaN MOSFET based on AlGaN/GaN heterostructure with extremely high 2DEG density grown on silicon substrate. IEEE Electron Dev Lett 2010;31(3):192–4. [16] Corrion AL, Chen M, Chu R, et al. Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric DRC. 2011. p. 213-214.