High transconductance InP MISFET'S with double layer gate insulator

Physica 129B (1985) 399402 North-Holland, Amsterdam

399

HIGH TRANSCONDUCTANCE InP MISFET'S WITH DOUBLELAYERGATE INSULATOR P. DIMITRIOU, G. POST, A. SCAVENNEC, N. DUHAMEL C.N.E.T.,

196, rue de Paris - 92220 Bagneux - France.

M. LORANS S.A.T.,

86280 Saint Benoit - France

Enhancement-mode MISFETS on indium phosphide have been made using a double d i e l e c t r i c layer as a gate insulator. An effective mobility of 3800 cm2/Vs has been achieved which is the highest value reported to date. Due to charge injection, operation of the devices is restricted to frequencies above 10 Hz.

1. INTRODUCTION InP MISFETS are promising devices for

oriented semi-insulating (iron - doped) InP substrates. Source and drain regions are

high-speed microelectronics and

selectively implanted with Si 29+ ions at

optoelectronics applications. Both

190 KeV with a dose of 5 x 1014 atoms/cm3.

enhancement and depletion-mode MISFETS have

Annealing is carried out at 730°C in an argon-

been reported in the l i t e r a t u r e , Gate

hydrogen atmosphere, using a proximity cap of

insulators such as s i l i c a or alumina are

InP. Ohmic contacts are formed by vacuum

generally used 1,2.

evaporation and 350°C alloying of AuGe

Recently we presented preliminary results on

eutectic The sheet resistance of the implanted

devices with a native sulphide insulator

n+ layer is 25 Q and the contact r e s i s t i v i t y

grown on InP 3. A very high effective electron

is 10-5 ~ cm2. A thin sulphide layer (100 A)

mobility could be observed in the accumulation

is grown on InP in the channel region, by the

channel on semi-insulating substrate. This paper

surface reaction of saturated sulphur vapour

w i l l report on transistors prepared with a thin

with InP in an evacuated quartz ampoule at

native sulphide and a CVD silicon dioxide layer

330°C. XPS and Auger spectra indicate that the

as a gate d i e l e c t r i c . Well saturated IDS - VDS

composition of layers grown in similar

characteristics and low leakage currents were

conditions is close to In2S3. The refractive

obtained. The d r i f t behaviour of these devices

index at x = 6328 A is 2.3 and the d i e l e c t r i c

w i l l also be discussed.

constant at 1MHz is 12 ; the leakage current

2. DEVICEPREPARATION

at 0.5 MV/cm is 10-? A/cm2.

Transistors are fabricated on (100)

0378-4363/85/$03.30 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)

P. Dimitri~n~ el al. ,,' ttig'h tra..~'c~dztcta~zce I . P ,,141SH'/T'S

400

S i l i c o n d i o x i d e is then deposited to a thickness of 800 A on top of the s u l p h i d e , using s i l a n e and n i t r o u s oxide reactants at a substrate temperature of 200°C. The breakdown field

strength of the composite l a y e r is 1.5

MV/cm, w h i l e a value of 5 MV/cm is g e n e r a l l y observed on a s i n g l e SiO 2 l a y e r . The refractive

index of these SiO 2 f i l m s is 1.46

and the d i e l e c t r i c

constant is 4. Gate

e l e c t r o d e s are obtained by t i t a n i u m - g o l d e v a p a r a t i o n . The channel lengths of MISFETS are 10 or 20 microns and the gate lengths 30 or 40 microns, r e s p e c t i v e l y . 3. ELECTRICAL PROPERTIES Capacitance and conductance measurements

Fig. i : Drain c u r r e n t versus drain voltage c h a r a c t e r i s t i c s of a double l a y e r . InP MISFET : channel length 20 ~m. V e r t i c a l scale i m A / d i v , h o r i z o n t a l scale i V / d i v , gate voltage 0.5V/step.

have been done on MIS diodes f a b r i c a t e d on n-type InP, the composition and thickness of

typically

4.6 x 10-8 F/cm 2, the f i e l d

the d i e l e c t r i c s

mobilities

have been deduced from the l i n e a r

transistors.

being the same as f o r the

An annealing at moderate

effect

dependance of IDS on VG at small drain

temperature (250°C) in a notrogen ambient has

v o l t a g e , as well as from the IDS I/2 - VG

been found to reduce the i n j e c t i o n - t y p e

r e l a t i o n in the saturated region ( F i g . 2).

h y s t e r e s i s observed in C-V c h a r a c t e r i s t i c s .

Values from 2800 to 3800 cm2/Vs have been

Under accumulation b i a s , a l a r g e frequency

found c o n s i s t e n t l y on a large number of

d i s p e r s i o n of the capacitance and p a r a l l e l

devices with d i f f e r e n t

geometries.

conductance is observed in the frequency range I

of i n v e s t i g a t i o n (i00 Hz - i MHz). The leakage

I

I

c u r r e n t in the sulphide l a y e r is the main loss mechanism, masking any c o n t r i b u t i o n s from i n t e r f a c e traps : the high-frequency capacitance is determined by the series combination of the SiO 2 and sulphide l a y e r s , the low-frequency l i m i t

is the capacitance of

the s i l i c o n d i o x i d e l a y e r only. Transistor characteristics

displayed on a

curve t r a c e r at i00 Hz are h y s t e r e s i s free (Fig.i).

Devices can be driven i n t o s a t u r a t i o n I

and e x h i b i t low drain conductance. Threshold

1

voltage depends s t r o n g l y on the mean value of the drain and the gate bias applied to the device and may vary t y p i c a l l y

between - i and

+ 0.5 V o l t s . Using the known gate i n s u l a t o r capacitance,

Fig. 2: Ins An e f f e c t # v e is ~ e r r e d IDS~" = i/2

I

2 Vo ( V o l t s )

I

3

4

(V G) p l o t obtained from f i g u r e i . e l e c t r o n m o b i l i t y of 3850 cm2/Vs from ~ e f f (W/L) Ci (V G - VT) 2

401

P Dimitriou et al. / High transconductance I n P M I S F E T ' S

D e f i n i t l y the InP - native sulphide interface

electrical f i e l d under the gate has been found

is effective to provide such a high mobility

to be the worst-case condition for d r i f t

in the electron accumulation layer (devices

measurements. The drain current decays nearly

prepared with a single SiO2 layer f a l l off by

completely within 10 seconds, i t recovers very

almost an order of magnitude). The good

slowly at above 1000 seconds (Fig. 4a).

transport properties at the InP - sulphide

The i n i t i a l slope of the decay is 2 to 5 % in

interface may be related to the fact that the

10 milliseconds, which is s u f f i c i e n t l y low to

density of fast interface states is low.

make curve tracer results at 100 Hz appear to

Electron d i f f r a c t i o n patterns have shown that

be free from any hysteresis.

the sulphide grows nearly e p i t a x i a l l y on

On reference devices made with a single

indium phosphide "

SiO2 layer, no large transient of current has

A transconductance of 40 mS/mm has been

been found in the time scale of seconds. The

measured on devices with a gate length of 10

drain current of those devices starts off with

microns (Fig. 3).

a lower level corresponding to a low transconductance (Fig. 4b). The long-term increase of drain current is observed on both 10 2, <

X

AulSilicalSulphidelInP

X X

X

Iz uJ 10 clc rr

VD=0.5VoIt

X

VG= 1.1Volt ( s t e p )

X

x x

o z < nr o

x

x

4. DRIFT BEHAVIOUR As may be expected from the leaky nature of the sulphide charge transfer takes place

L0

SiO2 - sulphide interface. The accumulation charge transient has been monitored by measuring the drain current at a small drain bias, after applying a positive voltage step to the gate. The application of a homogeneous

1

xxxxX

X

I

10 2 TIME(s)

I

I

103

104

10 2 <

Au/Silica/InP V0=0.6Volt VG=l.5VoIt ( s t e p )

J--

z uJ rr rr

x

(.9 z

x x x

x xx

xxx

xx

x

xx

xx

x× x

xX

rr £3

between the electron accumulation layer and traps or bands inside the sulphide and at the

x Xx

10-1

Fig. 3: drain current versus drain voltage characteristics of an InP MISFET : the channel length is now lOpm, the gate width lO0~m. Vertical scale : 2mA/div, horizontal scale lV/div, gate voltage 1V/step. Gm = 40 mS/mm.

x x

x

1

x

)-1

I

I

1

10

I

10 2 TIME(s)

J

I

10 3

10 4

Fig. 4 : drain current d r i f t of InP MISFETs after application of a bias step on the gate, from OV to the indicated value. a) double layer d i e l e c t r i c , VD=O.5V, VG=I.lV b) SiO2 d i e l e c t r i c , VD=O.6V, VG=I.5V

P. Dimitriou et al. / ltigh transconductance htP MISI~E'T'S

402

kinds of devices, indicating that this may be

Acknowledgements

due to positive charge migration in the silicon dioxide. Small signal measurements at high frequency have been done on some devices at zero gate

The authors would l i k e to thank A. MIRCEA for continuous encouragement, M. FEUILLADE for mask making, and C. BACOT, C. BESOMBES, M.

bias only, since a stable operation at

CARRE, P. DROUET, P.

elevated drain current was d i f f i c u l t to obtain

valuable technical assistance.

KRAUZ, and M. TROTTE for

due to the d r i f t . At a sustained drain bias above 4V, the threshold voltage becomes

REFERENCES

negative and the FET is conducting. However the current, and the transconductance, are rather small. The cutoff frequency (150 MHz) typically inferred from S-parameters measurements, results from that low transconductance value (2mS) and the parasitic capacitance of the 20 ~m overlap of the gate metallisation over the source and drain.

i - K.P. PANDE, V.K.R. NAIR, J. Appl. Phys. 55 (1984)

3109.

2- T. SAWADA, H. HASEGAWA, H. OHNO, Thin Solid Films, 103 (1983)

107.

3- G. POST, P. DIMITRIOU, A. SCAVENNEC, N. DUHAMEL, A. MIRCEA, Electronics L e t t . 19 (1983)

459.

4- L. COT, B. DESCOUTS, M. DURAND, G. MERMANT, 5. CONCLUSION Enhancement-mode MISFETS on semi-insulating indium phosphide have been made. Effective channel m o b i l i t i e s up to 3800 cm2/Vs were achieved by using a thin layer of native sulphide beneath a s i l i c o n dioxide gate d i e l e c t r i c . The very good interface q u a l i t y of the InP - InP sulphide system has been demonstrated. However, more work remains to be done in order to improve the i n s u l a t i n g q u a l i t y of the sulphide to a s a t i s f a c t o r y level for p r a c t i c a l devices.

G. POST, A. SCAVENNEC, ESSDERC (1981)

203,