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High performance of ultralow temperature polycrystalline silicon thin film transistor on plastic substrate
Solid-State Electronics 75 (2012) 97–101
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
High performance of ultralow temperature polycrystalline silicon thin film transistor on plastic substrate Dong Jin Park a, Yong Hae Kim b, Byung Ok Park a,⇑ a b
Department of Electronic Materials Engineering, Kyungpook National University, 1370 Sankyuk-dong, Buk-gu, Daegu 702-701, Republic of Korea Digital Paper Technology Research Team, Electronics and Telecommunications Research Institute (ETRI), 138 Gajeong-ro, Yuseong-gu, Daejeon 305-700, Republic of Korea
a r t i c l e
i n f o
Article history: Received 8 June 2011 Received in revised form 6 December 2011 Accepted 1 April 2012 Available online 9 May 2012 The review of this paper was arranged by Dr. Y. Kuk Keywords: AMOLED Flexible display Poly-silicon SLS
a b s t r a c t A high performance ultralow temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) was obtained on a plastic substrate using the optimization of a triple layered buffer process for a suppression the damage on plastic substrate during laser dopant activation, the high quality SiO2 interface layer formation between the gate dielectric film and the poly-Si film using plasma oxidation, and a successful crystallization of large grain poly-Si films with a sequential lateral solidification (SLS) method. High performances with field effect mobilities of 180 and 62 cm2 V1 s1, threshold voltages of 1.4 and 1.6 V and sub-threshold swings of 0.78 and 0.92 V/decade were obtained for n-channel metal–oxidesemiconductor (nMOS) and p-channel metal–oxide-semiconductor (pMOS) TFT on plastic substrate, respectively. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Flexible displays are currently the subject of great interest due to their low weight, superior compactness, robustness, and design flexibility compared with conventional glass-based displays. To realize a mechanically stable display, however, several issues must be resolved. Inorganic materials have very different mechanical properties than plastic substrates. In particular, the thermal expansion coefficients of plastic substrates are much larger than those of inorganic materials and consequently, stresses are introduced during the deposition process. Furthermore, film cracking and delamination may occur during the fabrication process and in operation. If a freestanding substrate is employed, the curvature of the inorganic film structures on plastic substrates changes during circuit fabrication, causing misalignment between the layers. In order to prevent this misalignment, the plastic substrate is typically bonded to a rigid carrier. The adhesive used for bonding must withstand the thin film transistor (TFT) processing temperatures and chemicals; therefore, the use of an adhesive necessitates a reduction of the maximum process temperature from the value that the substrate itself would normally withstand. These issues and the low thermal resistance of most plastic substrates necessitate a low temperature process. ⇑ Corresponding author. Tel.: +82 53 950 5634; fax: +82 53 950 5645. E-mail address: [email protected] (B.O. Park). 0038-1101/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.04.028
In addition, to drive an active matrix organic light emitting display (AMOLED) unit, devices with high mobility are required. For such requirements, an ultralow-temperature poly-Si (ULTPS) TFT appears to be an appropriate choice for device fabrication [1,2]. The crystallization of sputter deposited a-Si films has been achieved by either excimer laser annealing or sequential lateral solidification (SLS) [3]. In this study, we reported a successful SLS on a plastic substrate, which yielded micron-sized large-grain poly-Si films. To prevent damage to the plastic substrates during the laser dopant activation, a quarter wavelength Bragg reflector, made by successive depositions of plasma-CVD silicon dioxide and silicon nitride film, and the oxide–silicon–oxide (SiO2–Si–SiO2) buffer structure was suggested. For gate dielectrics, chemical vapor deposition SiO2, sputter deposition SiO2, and plasma enhanced atomic layer deposition (PEALD) Al2O3 films [4], have been reported. A two-layer gate insulator composed of a plasma oxidized SiO2 and PEALD Al2O3 on a plastic substrate [5] shows high quality characteristics. 2. Experimental procedure Fig. 1 shows the schematic diagram of how low temperature poly-Si TFT on plastic substrate is produced. In this work, we used polyarylate (PAR) plastic substrates. Unless supported by a rigid flat support, flexible plastic substrates are always bent to have some finite curvature. Such curvature imposes great difficulty in achieving correct pattern alignment and uniformity in deposition.
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D.J. Park et al. / Solid-State Electronics 75 (2012) 97–101
activation was obtained. An organic interlayer dielectric material was deposited. Finally the contact hole opening was followed by 300 nm Al formation.
3. Results and discussion
Fig. 1. Schematic diagram of the cross-sectional TFT structure.
For this reason, we bonded the plastic substrate on a rigid glass carrier to ensure processing stability. The carrier has the geometry of a 5-inch glass. The PAR substrate was attached to the glass carrier wafer with an adhesive having a peel strength of 600 gf/ inch. The peel strength was optimized to be neither too weak to allow the delamination of the substrate nor too strong to make the final detachment of the plastic substrate from the glass carrier difficult. In the final step the plastic substrate was detached from the glass carrier by using solvents and heat to decompose the adhesive. On the plastic substrate, a triple-layered buffer layer was deposited by a sputtering method. The buffer layer has a structure of oxide– silicon–oxide (SiO2–Si–SiO2). After laminating the plastic substrate on a 5-inch glass wafer, we sputtered the first buffer oxide layer comprised of 250 nm thick SiO2 film on the plastic substrate at 3.7 W/cm2 and 0.15 Pa, resulting in a deposition rate of 22 nm/ min. Depositing a stiff film on a compliant substrate induces excessive stress on both layers. In order to reduce this stress and prevent delamination from the glass wafer, deposition was conducted at room temperature. Subsequently, we deposited an 80 nm thick a-Si film layer as an absorption layer at 4.0 W/cm2 and 0.48 Pa Ar pressure at a deposition rate of 77 nm/min. Successful crystallization of the a-Si film can be accomplished through the production of a dense a-Si film that has low argon content and can endure highintensity laser irradiation. The sputtering condition used to form the first buffer oxide was utilized again to deposit a 270 nm thick SiO2 buffer oxide on the absorption layer [6]. The thickness and deposition temperature are important to prevent the film cracking during the gate oxide deposition. After forming the buffer layer, an 80 nm thick amorphous Si film was deposited and crystallized by a sequential lateral solidification method [7]. The gate dielectric layer was formed by a PEALD method. Prior to the oxidation, the surface of the Si substrate was cleaned with a 100:1 hydrofluoric (HF) acid solution to remove the native oxide layer. We attempted to oxidize the Si surface with a pulsed O2 plasma at an RF frequency of 13.56 MHz and a power of 0.41 W/cm2 for 30 min in the PEALD chamber. A gate dielectric Al2O3 film containing nitrogen (<1%) was deposited in situ with the O2 gas mixed with N2 gas as the oxidants and trimethylaluminum as the source of Al [8]. The plasma oxidized film and Al2O3 film are 5 and 70 nm thick, respectively. The interface quality between SiO2 and Si film using oxygen plasma treatment could be improved by terminating the trap states in the poly-Si films [9]. Following the gate dielectric formation, Al gate electrode of 200 nm was formed by DC sputtering at room temperature. After the patterning of the gate electrode, the n-channel and p-channel source and drain (S/D) regions were formed by ion shower doping using PH3/4 keV and B2H6/10 keV. The laser activation is necessary for the ultralow temperature process. When the mask had a lineshaped open area with a width of 2 lm and a period of 6 lm, the wavelength of the XeCl excimer laser light was 308 nm, the pulse duration was 25 ns, the shot number is twenty times, and the laser energy of 312 mJ/cm2, a S/D sheet resistance below 300 X/h for n-channel S/D and 500 X/h for p-channel S/D by laser dopant
Although the majority of the plastic substrates are transparent in the visible wavelength range, Fig. 2 illustrates that commonly used plastic substrates absorb a significant fraction of light in the ultraviolet range. As the XeCl excimer laser light (wavelength k = 308 nm) lies in the noted range, damage to plastic substrates such as PAR and/or polyethersulphon (PES) is not easily avoided with XeCl excimer laser processing. In order to overcome this obstacle, a quarter-wavelength Bragg reflector made via successive deposition of plasma CVD silicon dioxide and silicon nitride film was employed to protect against damage during laser dopant activation. Because the Bragg reflector is highly sensitive to the film’s thickness, the process margin is narrowed after etching the active layer or gate dielectric. If the laser dopant activation is processed prior to gate dielectric deposition, a self-aligned process is prohibited and cannot be implemented into the plastic process. We present a novel oxide–silicon–oxide buffer structure suitable for fabricating an ULTPS TFT (<120 °C) on a plastic substrate with an XeCl excimer laser. The buffer structure is designed to have an absorption layer sandwiched between buffer oxide films. Because a-Si film, in terms of its role as an absorption layer, effectively absorbs the laser light during the laser dopant activation process, the plastic substrate is protected. The absorptive a-Si film layer is present across the entire substrate. However, it is converted into poly-Si film during the dopant activation process without roughening the interface of the buffer oxide and buffer silicon, except below the active layer, thus rendering a patterned appearance due to the transmittance difference. The thermal expansion coefficient of the plastic substrate is much larger than those of inorganic materials. Thus, the buffer layer which is in contact with the plastic substrate is expected to experience the most severe tensile stress during any subsequent processes accompanied by heat. Because the poly-Si film deposited on the buffer was already patterned into micron-sized discrete features, the stress transfer through the poly-Si was negligible. During the subsequent processes, the cracks in the buffer layer mainly occurred during the gate oxide step, during which the processing temperature ranged from 150 to 180 °C. To reduce the stress on buffer layer, we varied the sputtering temperature of the buffer layer [10].
Fig. 2. Transmittance characteristics of plastic substrates such as PAR, PES, polyimide (PI), and polycarbonate (PC).
D.J. Park et al. / Solid-State Electronics 75 (2012) 97–101
99
Crack occuring temperature (oC)
300 R.T
250
80-100oC
200 150 100 50
0 Inside of array
Outside of array
Fig. 4. Ar content within the a-Si film and the maximum laser energy density over which the a-Si film is damaged by explosive Ar gas effusion with pressure variation.
Fig. 3. Effect of sputtering temperature on the cracking temperature, above which the buffer layer is cracked. The layer endurance against thermal cracking is improved by increasing the sputtering temperature.
Fig. 3 summarizes the effect of the deposition temperature on the maximum temperature, above which cracking in buffer layer is observed (the maximum temperature is called the cracking temperature). Compared to room temperature deposition, by depositing buffer layers at around 100 °C, it was possible to increase the cracking temperature by approximately 30–50 °C. Fig. 4 shows the Ar content within the a-Si film and the maximum laser energy density over which the a-Si film is damaged by explosive Ar gas effusion. Although the Ar content within the a-Si film is decreased by increasing the working gas pressure, the a-Si film grown at 2.7 mtorr shows the highest resistance upon damage with 792 mJ/cm2. The films prepared at low pressure exhibit little surface morphology and a densely packed structure, which is indicative of a zone-T dense structure [11]. The most resistant a-Si film for Ar gas effusion damage may be determined by competition between the film density and the argon gas concentration. The argon content in the a-Si film analyzed by Rutherford backscattering scattering (RBS) is reduced from 2.0% to 0.98% by first step laser annealing at 336 mJ/cm2 and to 0.84% by second step laser annealing at 482 mJ/cm2. The poly-Si film with 80 nm thickness is obtained by SLS crystallization at 550 mJ/cm2 after first step laser annealing at 336 mJ/cm2. Fig. 5a shows a transmission electron microscopy (TEM) of poly-Si grains, which are about 6 lm long. To obtain the grain boundary (GB) characters of such grains, we obtained Kikuchi patterns using an EBSD facility. Fig. 5b shows the statistical distribution of the coincidence site lattice (CLS) or R, which represents the reciprocal density of the sites shared by two adjoining grains. The CLS distribution reveals that R3 and R9 occupy the first and second appearance probability. Because such coherent GBs have low density of dangling bonds and charge trap sites, our poly-Si is expected to have high mobility. Fig. 6 shows the inverse pole figures of surface normal, rolling, and transverse directions. Whereas the normal and the rolling directions did not bear any strong preferential texture, the transverse tended to have a h1 0 0i preference. The preferential growth in h1 0 0i reflects the fact that the advancing solidification front of the diamond cubic is [1 0 0], which has been interpreted as the facility in atom bonding to complete the relevant plane. Attempts to produce a gate dielectric film of Al2O3 with plasma enhanced atomic layer deposition (PEALD) at low temperature resulted in the formation of a defective silicon oxide (SiO2) interface layer [12]. Usually, to facilitate the transport of reaction gas species, PEALD uses a appropriate plasma oxidation power in order to improve quality SiO2 interface layer formation between the gate
Fig. 5. (a) TEM image of polycrystalline Si, which was obtained by laser crystallization and (b) CSL distribution of Si grains.
dielectric and the poly-Si film. However, the plasma oxidation process condition should be selected from both a high oxidation rate and a suppression of ion bombardment damage [13]. Fig. 7 shows the thickness of SiO2 and Al2O3 layer with a plasma oxidation power variation in the PEALD of 50 nm Al2O3 film. Prior to the Al2O3 film deposition at 200 °C, the surface of the HF cleaned Si substrates was treated with pulsed O2 plasma with 300 W for 30 min to form a high quality SiO2 interfacial layer. There is a clearly grown SiO2 layer as shown in the inset and SiO2 interface
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D.J. Park et al. / Solid-State Electronics 75 (2012) 97–101
Fig. 9. Transfer characteristics of the nMOS/pMOS TFT with W/L = 30 lm/30 lm. Fig. 6. Inverse pole figures of poly-Si. The transverse direction bears texture preference along [0 0 1].
60
Thickness (nm)
50 40
Al2O3
30
Al2O3
20
SiOx Si
SiO2
10 0
50
80
100
150
Power (W)
10
10
8
8
6
6
4
4
2
2
0
Voltage Shift (V)
Dielectric constance
Fig. 7. Thickness variation of SiO2 and Al2O3 layer with the plasma oxidation power obtained from TEM observation. The inset shows TEM images of interface layer, 8 nm SiOx, and 50 nm Al2O3 deposition layer.
0 50
80
100
150
Power (W) Fig. 8. Changes in the dielectric constants and hysteresis values of 70 nm grown gate dielectric with a plasma oxidation power variation using C–V measurement.
layer thickness shows large difference with the plasma oxidation power. As can be seen, the thickness of SiOx layer increases with plasma power up to 100 W. Fig. 8 shows the changes in the dielectric constants and voltage shift in a hysteresis curve of a 50 nm thick gate dielectric with a plasma oxidation power using capacitance–voltage (C–V) measurement. From the results of Fig. 8, it was apparent that, the dielectric
constants show no explicit dependency on plasma oxidation power. However, as plasma power increased, the hysteresis values decreased. The voltage shift had marginally decreased up to 80 W, but decreased more rapidly above 100 W. This result suggests plasma power of more than 100 W is required to cure interface defects. Also, the result indicates that by increasing the plasma oxidation power in PEALD, the production of a high quality interfacial oxide may occur by increasing the oxidation rate without inducing ion bombardment damage. Fig. 9 shows the transfer characteristics of the n-channel metal–oxide-semiconductor (nMOS) and p-channel metal– oxide-semiconductor (pMOS) TFT with W/L = 30 lm/30 lm. High performances with field effect mobilities of 196 and 95 cm2 V1 s1, threshold voltages of 1.6 and 1.5 V and sub-threshold swings of 0.53 and 0.45 V/decade were obtained for n-channel and p-channel TFT on flexible metal foil substrate, respectively. 4. Conclusion This study fabricated a low temperature poly-Si TFT on plastic suited for application in the field of flexible displays. On the plastic substrate, a triple-layered buffer layer (SiO2–Si–SiO2) was deposited by a sputtering method in preventing plastic damage which is induced during the laser activation process. The study has demonstrated a successful crystallization of large grain poly-Si films with SLS method on a plastic substrate. In realizing SLS, it is important to adjust the buffer layer density, and produce a dense a-Si film which endures high intensity laser irradiation. Also, the optimization of the condition of plasma oxidation forming a high quality interface layer between the gate dielectric film and the poly-Si film were presented. The fabricated nMOS/pMOS TFT on plastic substrate showed field effect mobilities of 180/62 cm2 V1 s1, threshold voltages of 1.4/1.6 V and sub-threshold swings of 0.78/0.92 V/decade, respectively. References [1] Gosain DP, Noguchi T, Usui S. High mobility thin film transistors fabricated on a plastic substrate at a processing temperature of 110°C. Jpn J Appl Phys, Part 2 2000;39:L179–81. [2] Kwon JY, Kim DY, Cho HS, Park KB, Jung JS, et al. Low temperature poly-si thin film transistor on plastic substrates. IEICE Trans Electron 2005;E88-C:667–71. [3] Kim YH, Sohn CY, Lim JW, Yun SJ, et al. High-performance ultra-lowtemperature polycrystalline silicon using sequential lateral solidification. IEEE Electron Device Lett 2004;25:550–2. [4] Park DJ, Lim JW, Park BO. Stabilization of Al2O3 gate oxide on plastic substrate for low temperature poly-silicon by in situ plasma treatment. Solid-State Electron 2010;54:323–6.
D.J. Park et al. / Solid-State Electronics 75 (2012) 97–101 [5] Kim YH, Moon J, Chung CH, Yun SJ, Park DJ, et al. Performance improvement of ultralow temperature polycrystalline silicon TFT on plastic substrate by plasma oxidation of polycrystalline Si surface. IEEE Electron Device Lett 2006;27:896–8. [6] Kim YH, Chung CH, Moon J, Kim GH, Park DJ, et al. Oxide–silicon–oxide buffer structure for ultra-low temperature polycrystalline silicon thin film transistor on plastic substrate. IEEE Electron Device Lett 2006;27:579–81. [7] Kim YH, Chung CH, Yun SJ, Moon J, Park DJ, et al. Large grain polycrystalline silicon film by sequential lateral solidification on a plastic substrate. Thin Solid Films 2005;493:192–6. [8] Lim JW, Yun SJ. Electrical properties of alumina films by plasma-enhanced atomic layer deposition. Electrochem Solid-State Lett 2004;7:F45. [9] Higashi S, Abe D, Hiroshima Y, Miyashita K, Kawamura T, et al. High-quality SiO2/Si interface formation and its application to fabrication of low-
[10]
[11] [12]
[13]
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temperature-processed polycrystalline Si thin-film transistor. Jpn J Appl Phys 2002;41:3646–50. Leterrier Y, Medico L, Demarco F, et al. Mechanical integrity of transparent conductive oxide films for flexible polymer-based displays. Thin Solid Films 2004;460:156–66. Unagami T, Lousa A, Messier R. Silicon thin film with columnar structure formed by RF diode sputtering. Jpn J Appl Phys 1997;36:L737–9. Ha SC, Choi E, Kim SH, Roh JS. Influence of oxidant source on the property of atomic layer deposited Al2O3 on hydrogen-terminated Si substrate. Thin Solid Films 2005;476:252–7. Goto M, Azuma K, Okamoto T, Nakata Y. Surface wave plasma oxidation at low temperature under rare gas dilution. Jpn J Appl Phys 2003;42:7033–8.
Contents lists available at SciVerse ScienceDirect
Solid-State Electronics journal homepage: www.elsevier.com/locate/sse
High performance of ultralow temperature polycrystalline silicon thin film transistor on plastic substrate Dong Jin Park a, Yong Hae Kim b, Byung Ok Park a,⇑ a b
Department of Electronic Materials Engineering, Kyungpook National University, 1370 Sankyuk-dong, Buk-gu, Daegu 702-701, Republic of Korea Digital Paper Technology Research Team, Electronics and Telecommunications Research Institute (ETRI), 138 Gajeong-ro, Yuseong-gu, Daejeon 305-700, Republic of Korea
a r t i c l e
i n f o
Article history: Received 8 June 2011 Received in revised form 6 December 2011 Accepted 1 April 2012 Available online 9 May 2012 The review of this paper was arranged by Dr. Y. Kuk Keywords: AMOLED Flexible display Poly-silicon SLS
a b s t r a c t A high performance ultralow temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) was obtained on a plastic substrate using the optimization of a triple layered buffer process for a suppression the damage on plastic substrate during laser dopant activation, the high quality SiO2 interface layer formation between the gate dielectric film and the poly-Si film using plasma oxidation, and a successful crystallization of large grain poly-Si films with a sequential lateral solidification (SLS) method. High performances with field effect mobilities of 180 and 62 cm2 V1 s1, threshold voltages of 1.4 and 1.6 V and sub-threshold swings of 0.78 and 0.92 V/decade were obtained for n-channel metal–oxidesemiconductor (nMOS) and p-channel metal–oxide-semiconductor (pMOS) TFT on plastic substrate, respectively. Ó 2012 Elsevier Ltd. All rights reserved.
1. Introduction Flexible displays are currently the subject of great interest due to their low weight, superior compactness, robustness, and design flexibility compared with conventional glass-based displays. To realize a mechanically stable display, however, several issues must be resolved. Inorganic materials have very different mechanical properties than plastic substrates. In particular, the thermal expansion coefficients of plastic substrates are much larger than those of inorganic materials and consequently, stresses are introduced during the deposition process. Furthermore, film cracking and delamination may occur during the fabrication process and in operation. If a freestanding substrate is employed, the curvature of the inorganic film structures on plastic substrates changes during circuit fabrication, causing misalignment between the layers. In order to prevent this misalignment, the plastic substrate is typically bonded to a rigid carrier. The adhesive used for bonding must withstand the thin film transistor (TFT) processing temperatures and chemicals; therefore, the use of an adhesive necessitates a reduction of the maximum process temperature from the value that the substrate itself would normally withstand. These issues and the low thermal resistance of most plastic substrates necessitate a low temperature process. ⇑ Corresponding author. Tel.: +82 53 950 5634; fax: +82 53 950 5645. E-mail address: [email protected] (B.O. Park). 0038-1101/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.04.028
In addition, to drive an active matrix organic light emitting display (AMOLED) unit, devices with high mobility are required. For such requirements, an ultralow-temperature poly-Si (ULTPS) TFT appears to be an appropriate choice for device fabrication [1,2]. The crystallization of sputter deposited a-Si films has been achieved by either excimer laser annealing or sequential lateral solidification (SLS) [3]. In this study, we reported a successful SLS on a plastic substrate, which yielded micron-sized large-grain poly-Si films. To prevent damage to the plastic substrates during the laser dopant activation, a quarter wavelength Bragg reflector, made by successive depositions of plasma-CVD silicon dioxide and silicon nitride film, and the oxide–silicon–oxide (SiO2–Si–SiO2) buffer structure was suggested. For gate dielectrics, chemical vapor deposition SiO2, sputter deposition SiO2, and plasma enhanced atomic layer deposition (PEALD) Al2O3 films [4], have been reported. A two-layer gate insulator composed of a plasma oxidized SiO2 and PEALD Al2O3 on a plastic substrate [5] shows high quality characteristics. 2. Experimental procedure Fig. 1 shows the schematic diagram of how low temperature poly-Si TFT on plastic substrate is produced. In this work, we used polyarylate (PAR) plastic substrates. Unless supported by a rigid flat support, flexible plastic substrates are always bent to have some finite curvature. Such curvature imposes great difficulty in achieving correct pattern alignment and uniformity in deposition.
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D.J. Park et al. / Solid-State Electronics 75 (2012) 97–101
activation was obtained. An organic interlayer dielectric material was deposited. Finally the contact hole opening was followed by 300 nm Al formation.
3. Results and discussion
Fig. 1. Schematic diagram of the cross-sectional TFT structure.
For this reason, we bonded the plastic substrate on a rigid glass carrier to ensure processing stability. The carrier has the geometry of a 5-inch glass. The PAR substrate was attached to the glass carrier wafer with an adhesive having a peel strength of 600 gf/ inch. The peel strength was optimized to be neither too weak to allow the delamination of the substrate nor too strong to make the final detachment of the plastic substrate from the glass carrier difficult. In the final step the plastic substrate was detached from the glass carrier by using solvents and heat to decompose the adhesive. On the plastic substrate, a triple-layered buffer layer was deposited by a sputtering method. The buffer layer has a structure of oxide– silicon–oxide (SiO2–Si–SiO2). After laminating the plastic substrate on a 5-inch glass wafer, we sputtered the first buffer oxide layer comprised of 250 nm thick SiO2 film on the plastic substrate at 3.7 W/cm2 and 0.15 Pa, resulting in a deposition rate of 22 nm/ min. Depositing a stiff film on a compliant substrate induces excessive stress on both layers. In order to reduce this stress and prevent delamination from the glass wafer, deposition was conducted at room temperature. Subsequently, we deposited an 80 nm thick a-Si film layer as an absorption layer at 4.0 W/cm2 and 0.48 Pa Ar pressure at a deposition rate of 77 nm/min. Successful crystallization of the a-Si film can be accomplished through the production of a dense a-Si film that has low argon content and can endure highintensity laser irradiation. The sputtering condition used to form the first buffer oxide was utilized again to deposit a 270 nm thick SiO2 buffer oxide on the absorption layer [6]. The thickness and deposition temperature are important to prevent the film cracking during the gate oxide deposition. After forming the buffer layer, an 80 nm thick amorphous Si film was deposited and crystallized by a sequential lateral solidification method [7]. The gate dielectric layer was formed by a PEALD method. Prior to the oxidation, the surface of the Si substrate was cleaned with a 100:1 hydrofluoric (HF) acid solution to remove the native oxide layer. We attempted to oxidize the Si surface with a pulsed O2 plasma at an RF frequency of 13.56 MHz and a power of 0.41 W/cm2 for 30 min in the PEALD chamber. A gate dielectric Al2O3 film containing nitrogen (<1%) was deposited in situ with the O2 gas mixed with N2 gas as the oxidants and trimethylaluminum as the source of Al [8]. The plasma oxidized film and Al2O3 film are 5 and 70 nm thick, respectively. The interface quality between SiO2 and Si film using oxygen plasma treatment could be improved by terminating the trap states in the poly-Si films [9]. Following the gate dielectric formation, Al gate electrode of 200 nm was formed by DC sputtering at room temperature. After the patterning of the gate electrode, the n-channel and p-channel source and drain (S/D) regions were formed by ion shower doping using PH3/4 keV and B2H6/10 keV. The laser activation is necessary for the ultralow temperature process. When the mask had a lineshaped open area with a width of 2 lm and a period of 6 lm, the wavelength of the XeCl excimer laser light was 308 nm, the pulse duration was 25 ns, the shot number is twenty times, and the laser energy of 312 mJ/cm2, a S/D sheet resistance below 300 X/h for n-channel S/D and 500 X/h for p-channel S/D by laser dopant
Although the majority of the plastic substrates are transparent in the visible wavelength range, Fig. 2 illustrates that commonly used plastic substrates absorb a significant fraction of light in the ultraviolet range. As the XeCl excimer laser light (wavelength k = 308 nm) lies in the noted range, damage to plastic substrates such as PAR and/or polyethersulphon (PES) is not easily avoided with XeCl excimer laser processing. In order to overcome this obstacle, a quarter-wavelength Bragg reflector made via successive deposition of plasma CVD silicon dioxide and silicon nitride film was employed to protect against damage during laser dopant activation. Because the Bragg reflector is highly sensitive to the film’s thickness, the process margin is narrowed after etching the active layer or gate dielectric. If the laser dopant activation is processed prior to gate dielectric deposition, a self-aligned process is prohibited and cannot be implemented into the plastic process. We present a novel oxide–silicon–oxide buffer structure suitable for fabricating an ULTPS TFT (<120 °C) on a plastic substrate with an XeCl excimer laser. The buffer structure is designed to have an absorption layer sandwiched between buffer oxide films. Because a-Si film, in terms of its role as an absorption layer, effectively absorbs the laser light during the laser dopant activation process, the plastic substrate is protected. The absorptive a-Si film layer is present across the entire substrate. However, it is converted into poly-Si film during the dopant activation process without roughening the interface of the buffer oxide and buffer silicon, except below the active layer, thus rendering a patterned appearance due to the transmittance difference. The thermal expansion coefficient of the plastic substrate is much larger than those of inorganic materials. Thus, the buffer layer which is in contact with the plastic substrate is expected to experience the most severe tensile stress during any subsequent processes accompanied by heat. Because the poly-Si film deposited on the buffer was already patterned into micron-sized discrete features, the stress transfer through the poly-Si was negligible. During the subsequent processes, the cracks in the buffer layer mainly occurred during the gate oxide step, during which the processing temperature ranged from 150 to 180 °C. To reduce the stress on buffer layer, we varied the sputtering temperature of the buffer layer [10].
Fig. 2. Transmittance characteristics of plastic substrates such as PAR, PES, polyimide (PI), and polycarbonate (PC).
D.J. Park et al. / Solid-State Electronics 75 (2012) 97–101
99
Crack occuring temperature (oC)
300 R.T
250
80-100oC
200 150 100 50
0 Inside of array
Outside of array
Fig. 4. Ar content within the a-Si film and the maximum laser energy density over which the a-Si film is damaged by explosive Ar gas effusion with pressure variation.
Fig. 3. Effect of sputtering temperature on the cracking temperature, above which the buffer layer is cracked. The layer endurance against thermal cracking is improved by increasing the sputtering temperature.
Fig. 3 summarizes the effect of the deposition temperature on the maximum temperature, above which cracking in buffer layer is observed (the maximum temperature is called the cracking temperature). Compared to room temperature deposition, by depositing buffer layers at around 100 °C, it was possible to increase the cracking temperature by approximately 30–50 °C. Fig. 4 shows the Ar content within the a-Si film and the maximum laser energy density over which the a-Si film is damaged by explosive Ar gas effusion. Although the Ar content within the a-Si film is decreased by increasing the working gas pressure, the a-Si film grown at 2.7 mtorr shows the highest resistance upon damage with 792 mJ/cm2. The films prepared at low pressure exhibit little surface morphology and a densely packed structure, which is indicative of a zone-T dense structure [11]. The most resistant a-Si film for Ar gas effusion damage may be determined by competition between the film density and the argon gas concentration. The argon content in the a-Si film analyzed by Rutherford backscattering scattering (RBS) is reduced from 2.0% to 0.98% by first step laser annealing at 336 mJ/cm2 and to 0.84% by second step laser annealing at 482 mJ/cm2. The poly-Si film with 80 nm thickness is obtained by SLS crystallization at 550 mJ/cm2 after first step laser annealing at 336 mJ/cm2. Fig. 5a shows a transmission electron microscopy (TEM) of poly-Si grains, which are about 6 lm long. To obtain the grain boundary (GB) characters of such grains, we obtained Kikuchi patterns using an EBSD facility. Fig. 5b shows the statistical distribution of the coincidence site lattice (CLS) or R, which represents the reciprocal density of the sites shared by two adjoining grains. The CLS distribution reveals that R3 and R9 occupy the first and second appearance probability. Because such coherent GBs have low density of dangling bonds and charge trap sites, our poly-Si is expected to have high mobility. Fig. 6 shows the inverse pole figures of surface normal, rolling, and transverse directions. Whereas the normal and the rolling directions did not bear any strong preferential texture, the transverse tended to have a h1 0 0i preference. The preferential growth in h1 0 0i reflects the fact that the advancing solidification front of the diamond cubic is [1 0 0], which has been interpreted as the facility in atom bonding to complete the relevant plane. Attempts to produce a gate dielectric film of Al2O3 with plasma enhanced atomic layer deposition (PEALD) at low temperature resulted in the formation of a defective silicon oxide (SiO2) interface layer [12]. Usually, to facilitate the transport of reaction gas species, PEALD uses a appropriate plasma oxidation power in order to improve quality SiO2 interface layer formation between the gate
Fig. 5. (a) TEM image of polycrystalline Si, which was obtained by laser crystallization and (b) CSL distribution of Si grains.
dielectric and the poly-Si film. However, the plasma oxidation process condition should be selected from both a high oxidation rate and a suppression of ion bombardment damage [13]. Fig. 7 shows the thickness of SiO2 and Al2O3 layer with a plasma oxidation power variation in the PEALD of 50 nm Al2O3 film. Prior to the Al2O3 film deposition at 200 °C, the surface of the HF cleaned Si substrates was treated with pulsed O2 plasma with 300 W for 30 min to form a high quality SiO2 interfacial layer. There is a clearly grown SiO2 layer as shown in the inset and SiO2 interface
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Fig. 9. Transfer characteristics of the nMOS/pMOS TFT with W/L = 30 lm/30 lm. Fig. 6. Inverse pole figures of poly-Si. The transverse direction bears texture preference along [0 0 1].
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Fig. 7. Thickness variation of SiO2 and Al2O3 layer with the plasma oxidation power obtained from TEM observation. The inset shows TEM images of interface layer, 8 nm SiOx, and 50 nm Al2O3 deposition layer.
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layer thickness shows large difference with the plasma oxidation power. As can be seen, the thickness of SiOx layer increases with plasma power up to 100 W. Fig. 8 shows the changes in the dielectric constants and voltage shift in a hysteresis curve of a 50 nm thick gate dielectric with a plasma oxidation power using capacitance–voltage (C–V) measurement. From the results of Fig. 8, it was apparent that, the dielectric
constants show no explicit dependency on plasma oxidation power. However, as plasma power increased, the hysteresis values decreased. The voltage shift had marginally decreased up to 80 W, but decreased more rapidly above 100 W. This result suggests plasma power of more than 100 W is required to cure interface defects. Also, the result indicates that by increasing the plasma oxidation power in PEALD, the production of a high quality interfacial oxide may occur by increasing the oxidation rate without inducing ion bombardment damage. Fig. 9 shows the transfer characteristics of the n-channel metal–oxide-semiconductor (nMOS) and p-channel metal– oxide-semiconductor (pMOS) TFT with W/L = 30 lm/30 lm. High performances with field effect mobilities of 196 and 95 cm2 V1 s1, threshold voltages of 1.6 and 1.5 V and sub-threshold swings of 0.53 and 0.45 V/decade were obtained for n-channel and p-channel TFT on flexible metal foil substrate, respectively. 4. Conclusion This study fabricated a low temperature poly-Si TFT on plastic suited for application in the field of flexible displays. On the plastic substrate, a triple-layered buffer layer (SiO2–Si–SiO2) was deposited by a sputtering method in preventing plastic damage which is induced during the laser activation process. The study has demonstrated a successful crystallization of large grain poly-Si films with SLS method on a plastic substrate. In realizing SLS, it is important to adjust the buffer layer density, and produce a dense a-Si film which endures high intensity laser irradiation. Also, the optimization of the condition of plasma oxidation forming a high quality interface layer between the gate dielectric film and the poly-Si film were presented. The fabricated nMOS/pMOS TFT on plastic substrate showed field effect mobilities of 180/62 cm2 V1 s1, threshold voltages of 1.4/1.6 V and sub-threshold swings of 0.78/0.92 V/decade, respectively. References [1] Gosain DP, Noguchi T, Usui S. High mobility thin film transistors fabricated on a plastic substrate at a processing temperature of 110°C. Jpn J Appl Phys, Part 2 2000;39:L179–81. [2] Kwon JY, Kim DY, Cho HS, Park KB, Jung JS, et al. Low temperature poly-si thin film transistor on plastic substrates. IEICE Trans Electron 2005;E88-C:667–71. [3] Kim YH, Sohn CY, Lim JW, Yun SJ, et al. High-performance ultra-lowtemperature polycrystalline silicon using sequential lateral solidification. IEEE Electron Device Lett 2004;25:550–2. [4] Park DJ, Lim JW, Park BO. Stabilization of Al2O3 gate oxide on plastic substrate for low temperature poly-silicon by in situ plasma treatment. Solid-State Electron 2010;54:323–6.
D.J. Park et al. / Solid-State Electronics 75 (2012) 97–101 [5] Kim YH, Moon J, Chung CH, Yun SJ, Park DJ, et al. Performance improvement of ultralow temperature polycrystalline silicon TFT on plastic substrate by plasma oxidation of polycrystalline Si surface. IEEE Electron Device Lett 2006;27:896–8. [6] Kim YH, Chung CH, Moon J, Kim GH, Park DJ, et al. Oxide–silicon–oxide buffer structure for ultra-low temperature polycrystalline silicon thin film transistor on plastic substrate. IEEE Electron Device Lett 2006;27:579–81. [7] Kim YH, Chung CH, Yun SJ, Moon J, Park DJ, et al. Large grain polycrystalline silicon film by sequential lateral solidification on a plastic substrate. Thin Solid Films 2005;493:192–6. [8] Lim JW, Yun SJ. Electrical properties of alumina films by plasma-enhanced atomic layer deposition. Electrochem Solid-State Lett 2004;7:F45. [9] Higashi S, Abe D, Hiroshima Y, Miyashita K, Kawamura T, et al. High-quality SiO2/Si interface formation and its application to fabrication of low-
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temperature-processed polycrystalline Si thin-film transistor. Jpn J Appl Phys 2002;41:3646–50. Leterrier Y, Medico L, Demarco F, et al. Mechanical integrity of transparent conductive oxide films for flexible polymer-based displays. Thin Solid Films 2004;460:156–66. Unagami T, Lousa A, Messier R. Silicon thin film with columnar structure formed by RF diode sputtering. Jpn J Appl Phys 1997;36:L737–9. Ha SC, Choi E, Kim SH, Roh JS. Influence of oxidant source on the property of atomic layer deposited Al2O3 on hydrogen-terminated Si substrate. Thin Solid Films 2005;476:252–7. Goto M, Azuma K, Okamoto T, Nakata Y. Surface wave plasma oxidation at low temperature under rare gas dilution. Jpn J Appl Phys 2003;42:7033–8.