Historical review of compound semiconductor reliability

Microelectronics Reliability 46 (2006) 1218–1227 www.elsevier.com/locate/microrel

Historical review of compound semiconductor reliability William J. Roesch

*

TriQuint Semiconductor, Inc., 2300 N.E. Brookwood Parkway, Hillsboro, OR 97124-5300, United States Received 31 January 2006 Available online 5 June 2006

Abstract This discussion is meant to look back at reliability progress over the last thirty years and identify trends and shortcomings. The main body of published work came from the ROCS workshop. While the workshop addresses various specific issues individually, it is the accumulation of a variety of data, information, and experience which forms the basis of an assessment of reliability. In the end, reliability is simply an insightful perception of facts and statistics. After 20years of workshop meetings and three decades of accumulation of compound semiconductor reliability information, it is time to review, compare, and discuss the progress and the future of reliability for compound semiconductors.  2006 Elsevier Ltd. All rights reserved.

1. ROCS workshop The workshop began in 1985 as an outgrowth the GaAs Reliability Advisory Council. The council dissolved and reformed as a JEDEC committee, JC-50. This committee eventually moved under a general JEDEC semiconductor committee and became JC-14.7, as it is today. In 1986, the first GaAs reliability workshop was held in Grenelefe Florida, and in 2004, the name was changed. JC-14.7 is the primary sponsor and support group for the reliability of compound semiconductor (ROCS) workshop. Fig. 1 shows the attendance and location for the ROCS workshop over its 20-year history. Each year, the workshop objective is to bring together researchers, manufacturers, and users of compound semiconductor devices. Papers presenting the latest results and new developments in all phases of compound semiconductor reliability are solicited. Original papers discussing work in progress and emerging device technologies are acceptable and encouraged. *

Tel.: +1 503 615 9292; fax: +1 503 615 8903. E-mail address: [email protected]

Generally, the following topics are presented and discussed: failure mechanisms, circuit reliability, reliability modeling, thermal analysis, accelerated testing, materials defects, reliability standards, novel device problems, ESD/EOS/pulse burnout, and environmental effects. The workshop provides a program of between eight and 16 authors, where questions are allowed during presentation and several breaks are included to facilitate an informal atmosphere of discussion, benchmarking, and sharing of reliability data.

2. Introduction Compound semiconductors (CSs) have been around since the beginning of solid state technology. GaAs devices generated their own niche at about the time the commercialization and ‘‘catch up’’ phase started in earnest just about when the workshop began. Although it has a certain allure, new technology unfortunately carries a suspicion of reliability risk. This discussion will address the question. How have compound semiconductors (CSs) done in terms of reliability over the past 20-years?

0026-2714/$ - see front matter  2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2006.02.008

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227 140 120

Workshop Location History

80

2004 Monterey

2005 Palm Springs

2002 Monterey

2003 San Diego

2001 Baltimore

2000 Seattle

1999 Monterey

1998 Atlanta

1997 Anaheim

1996 Orlando

1995 San Diego

1994 Philadelphia

1993 San Jose

1992 Miami

1991 Monterey

1988 Nashville

0

1987 Portland

20

1986 Grenelefe

40

1990 New Orleans

60

1989 San Diego

Attendees

100

Fig. 1. History of the ROCS workshop.

The intent of this discussion is to provide information on: (1) Identification of reliability measures. (2) Comparisons to eras of silicon reliability improvements. (3) Short discussion on failure mechanisms.

3. A brief history of semiconductor reliability In order to discuss reliability of CSs, let us start by looking at reported lifetimes of circuits for the past 20years. Fig. 2 was compiled from summarizing reported lifetimes at the ROCS workshop since 1985 [1]. Note these extrapolations are normally for lifetimes of devices operating between 125 C and 150 C—but some extrapolations include operating temperature estimates that are considered appropriate for the structures under nominal use. To compare with silicon’s reliability progress, we will look further back, broaden the scope

1.E+12

Extrapolated Lifetime (hours)

1.E+11

GaAs - FETs GaAs - HBTs GaAs - Other InP - FETs InP - HBTs MM-HEMTs SiGe - HBTs Passives

10,000,000 YEARS

1.E+10 1.E+09 1.E+08 1.E+07

1,000 YEARS

1.E+06 1.E+05

10 YEARS

1.E+04 1.E+03

1985

1990

1995 2000 Publication Year

2005

2010

Fig. 2. Reported operating lifetimes for various compound semiconductors over the history of the ROCS workshop [1].

1219

beyond the workshop, and break-up the time period into five eras of improvement. Prior to 1985, reliability improvement on silicon devices had already begun—and those efforts had already passed through two eras [2]. In the first era of silicon reliability improvement, from 1975 to 1980, the Introduction of ‘‘New’’ VLSI Materials was at the forefront. Everyone was learning about material properties of Si, Al, and SiO2 and their various interactions. In the second era, from 1980 to 1985, the Major Reliability Problems for silicon technologies were identified: mobile ions, electromigration, stress migration, timedependent-dielectric-breakdown (TDDB), cracked die, broken bond wires, purple plague, and soft errors. The re-emergence of compound semiconductors was just beginning—generally with discrete devices, and then with the start of integration of MMICs. In the third era, from 1985 to 1990, Reliability Physics was the focus for the silicon folks. They had developed degradation models for all the previously identified mechanisms and also derived acceleration factors for the special environmental stresses of temperature cycling and corrosion. These were the showcase years for ESD studies on silicon. This was also the time that compound semiconductor circuits were introduced. From Fig. 2, you can see that all the emphasis was on FET style devices during these years, primarily MESFETs. Compound semiconductor (CS) devices were scarce, so sample sizes were small, and the CS folks immediately took up the reliability physics methodologies established by the silicon folks. In the fourth era, from 1990 to 1995, the silicon folks adopted a new phrase; Building-In Reliability. This was a period of reliability engineering, with a lot of emphasis on wafer-level reliability. The CS folks were sidetracked with the commercialization of their technology, and the carving of a small niche in the semiconductor pie. Most all of the work was still with FET devices, but the HBTs were introduced in the later part of this period. The focus was shifting from implanted devices to epitaxial circuits, so this meant more new materials without the experience from the first and second reliability eras. In the fifth era, from 1995 to 2000, the silicon folks were completing their 20-year cycle by merging the metrics of reliability and quality with focus on a Major Defect-Reduction Effort. This was characterized by lots of SPC, various six sigma programs, and a relentless search for ‘‘outliers’’ of measured distributions. This was the ‘‘happiest’’ period for CS as most companies were riding a huge volume increase. CS reliability emphasis was basically back at the second era of the silicon cycle—looking at the mechanisms which became more apparent with the explosion in volume shipments. You can see from Fig. 2 that there was interest in passive devices, particularly capacitors, as the CS folks learned about TDDB.

1220

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227

icon and compound semiconductors for the past 30years.

From 2000 to 2005, the silicon folks were restarting their cycle by reverting back to the first era, with the Introduction of New ULSI Materials. Work is on new copper metallizations, low-K interlayer dielectrics, and high-K gate dielectrics, new metal gate materials and getting features smaller than 100 nm. CS reliability emphasis is also on new material—new semiconductors. Fig. 2 indicates InP, metamorphic layers, and even GaN results starting to show up. During this full cycle review of silicon reliability efforts and the definition of the five eras [2], there are some interesting parallels in the CS data. While some of the techniques of the silicon cycle have been utilized during the CS development, most of the eras have not been fully duplicated. While some elements of era 1–3 have been investigated, holes still remain in the basic material properties of the compound semiconductors and the noble metallizations used for CS. Moore’s Law has not driven developments for CS interconnects or dielectrics. Instead of shrinking features appreciably, we tend to squeeze performance out of epitaxial enhancements and blending of additional ‘‘new’’ materials in the epitaxy. The eras of ‘‘building-in reliability,’’ and ‘‘major defect reduction effort,’’ have barely been touched by CS manufacturers. Even though the compound materials are constantly changing, a glance at Fig. 2 indicates there is no significant lifetime difference from materials or from FET and bipolar technologies. In fact, there is no significant change in the overall reliability during the past 20-years! (This same complaint is also made by the silicon reliability folks) [2]. Fig. 3 shows the comparisons of various reliability eras for sil-

4. Understanding mechanisms From the third era of reliability, everyone has learned the methodology of determining reliability. The three keys to measuring and predicting reliability are: (1) Knowledge of the root cause failure mechanisms. (2) Measurement of degradation distributions. (3) Characterization of acceleration factors. Obviously, the CS folks used all of the prior knowledge available from the first and second silicon reliability eras, but the failure mechanisms are not necessarily the same. There are a multitude of failure mechanisms for compound semiconductors, and recognizing that there are more than just one is an important point. Here are a few of the significant CS mechanisms in a relative chronological order of presentation at the ROCS workshop. 4.1. Sinking gates This diffusion mechanism is thermally driven. It is one of the oldest reported for FET-style compound semiconductors. This material diffusion mechanism has been substantiated with physical evidence for both MESFETs [3] and pHEMTs [4]. Because the sinking mechanism is so easy to accelerate with temperature,

Significant Reliability Events

GaN ROCS Workshop

Start of Fourth Generation

1975

Reliability Problems: Bkdce, Contacts

Reliability Physics: EM, REDR

First Era

2nd Era

Third Era

Introduction of GaAs FET Materials: GaAs, Au, SixNx

Reliability Problems: Sinking Gates, Ohmic Contacts

Reliability Physics: Thermal Diffusion, JEP118, Hydrogen

Reliability Engineering: WLR, Passives BIR?

Defect Reduction: Capacitors, Interconnects

First Era

Second Era

Third Era

Fourth Era

Fifth Era

First Era Second Era Introduction of New VLSI Materials: Si, Al, SiO2

Introduction of Epi Materials: HBTs, HEMTs

Major Reliability Problems: Mobile-ions, Electromigration Stress Migration, TDDB, Corrosion, Cracked-Die, Broken-Bonds, ESD, Soft-Errors

1980

Third Era

Fourth Era

Fifth Era

Major Reliability Physics Effort: Models Developed for: EM, MobileIons, SM, TDDB Corrosion, Temp-Cycling, Alpha Particles, EOS/ESD

Major Reliability Engineering Effort: Building-In Rel with Emphasis on WLR & DIR

Major DefectReduction Effort: SPC & 6 Sigma Outliers

1985

Year

1990

Introduction of New ULSI Materials: Cu & Low-K, High-K, Metal Gates, etc.

Start of Fifth Generation

1995

2000

2005

Fig. 3. Comparisons of silicon and compound semiconductor reliability eras. Note: Silicon eras [2]. On the bottom, and compound semiconductors are across the middle and epitaxial materials are on top.

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227

sinking gates are often identified as the cause of FET wearout. Even though some refractory gate metals have been aged and reported, titanium is still a common material for FET gates, and Ti diffusion with GaAs has a very high activation energy (the diffusion is exponentially accelerated with increasing temperatures). Even though the activation energy has been empirically measured at 2.56 eV [5], it is not unexpected based upon diffusion of other transition metals in GaAs; Mn = 2.49 eV, Au = 2.64 eV, and Ag = 2.27 eV. So if we were to make an estimate of the activation energy for Ti diffusion in GaAs from the Ballistic model, it would not be a stretch to 2.56 eV since the enthalpy of formation of a gallium site has been estimated by Van Vechten to be 2.31 eV [6]. This mechanism is quite unique to the Schottky contact FETs, and nothing like the mechanism found and addressed in the MOS-type world. The diffusion of Ti into compound semiconductors is so highly accelerated by temperature, it is arguably the mechanism, which has driven the CS fascination with lifetesting at multiple high temperatures to predict wear out. 4.2. Gate lag A common affliction for FETs. This phenomenon is thought to be a result of traps on the GaAs channel surface beside the gate. But is gate lag a failure mechanism, or merely an ugly property of trap-filled compound semiconductor substrates? These trap studies have focused on traps in various locations which result in various effects such as drain lag, side-gating, back-gating, and substrate-gating. Investigations into the aging of traps have indicated no particular degradation over time [7]. 4.3. Hot electrons Borrowed from problems suffered by silicon gate dielectrics, this is a charging effect, sometimes called ‘‘power-slump.’’ This is indeed an interesting mechanism, since it is exacerbated by low temperatures—at least for oxide dielectrics. The degradation is caused by impact ionization at the gate edge, which injects hot carriers into the interface between the semiconductor and the insulator. These carriers effectively expand the surface depletion layer and reduce Idss and gm without much of a change to the threshold voltage [8]. 4.4. Mechanical stress Compound semiconductors are piezoelectric [9]. Local mechanical stresses will cause changes in fields and characteristics of active devices. Yet when hydrogen contamination was found to cause threshold shift degradation in CS FET devices (in 1989), this piezoelectric

1221

property was passed-over for a more sexy theory ‘‘. . .conversion of gaseous hydrogen into atomic hydrogen in the Pt layer of the gate metallization, and the subsequent doping compensation and carrier removal from the active channel as the atomic hydrogen diffuses into the channel’’ [10]. It has taken more than 10-years to bust the original beautiful theory with the simple ugly fact that reduction of the gate metals (particularly titanium) in hydrogen produces a compressive stress that causes a piezoelectric polarization charge and results in the threshold shift [11]. This is another mechanism foreign to the silicon guys. 4.5. Electromigration This is an example of a failure mechanism born from silicon devices. Aluminum metallization is particularly susceptible to electromigration because of its relatively high resistivity. Aluminum also has a grain structure that makes it vulnerable to failure. Most CSs use gold instead of aluminum. The electromigration mechanism can be induced in gold under very high current densities, but electromigration has been largely disregarded for compound semiconductor interconnects at current densities below 500,000 A/cm2. Current density does seem to have an accelerating effect on HBTs [12], but there are two diverse mechanisms being theorized as to the cause. From the GaAs blend folks, the latest account for increasing base current is the ‘‘tunneling-recombination conduction mechanism’’ [13]. From the SiGe folks, ‘‘change in b is attributed to electromigration induced pressure on the emitter contact’’ [14]. There continues to be significant experimentation with thermal acceleration aging and both theories speak in terms of activation energy instead of current density. HBT studies and results usually define current density conditions, and the current density is known to be the primary stress to accelerate degradation in HBT devices, but two different mechanisms are claimed. Could both arguments be correct? This is a curiosity of the present state-of-the-art. 4.6. Corrosion Moisture ingression has only recently been considered as an issue for compound semiconductors [15]. Although gold and nitride are thought to be relatively inert, many of the CS contact materials are susceptible to moisture as are some of the semiconductor materials. In the past couple of years, humidity testing has come to the forefront. Once again, the CS mechanisms were found to be radically different from those characterized and modeled originally with silicon material families [16]. Nevertheless, significant lifetime improvements based upon various surface treatments are still being made for CS FETs [17]. It is interesting that even within

1222

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227

5

Normal Angle [ 0 I 0]

4 Perpendicular [ 0 I I ]

Perpendicular [ 0 I I ]

D Vth (%)

3 2

GaAs [ 1 0 0 ]

1

0II

0 -1 -2 -3

Normal Angle [ 0 I 0]

-4 -5 0

200

TIME (hours)

400

600

Fig. 4. Threshold shift dependence on gate orientation for degradation on GaAs pHEMTs aged unbiased at 85 C and 85% RH [17].

Fig. 5. Representation of distribution data that underlies simple lines showing median life dependence on temperature [17].

5.2. Squeezing the curve this short review of selected failure mechanisms, a 2004 look at moisture takes us back to the mechanical stress mechanism—see Fig. 4.

5. Failure distributions and statistics 5.1. Living with distributions To understand reliability, folks need to know about distributions. Significant degradation is needed during aging and the ability to separate fallout by each mechanism is often the issue. This can be especially difficult in a complex IC where multiple mechanisms are all degrading at various rates (and in opposite directions). Reliability engineers tend to immerse these problems with complicated statistical formulas and probability estimates in order to evaluate all the complexities. While this approach may seem to bring out unbiased and objective interpretations of the results, it often is where the non-reliability person gets lost. Unfortunately, even the reliability engineer often looses sight of what might be most important for customers. Even though reliability engineers and statisticians will enjoy analyses of distributions using normal, lognormal, Weibull, Poisson, maximum likelihood, or some other techniques, they all tend to show nearly identical (albeit astronomical) results after the acceleration factors are considered. In other words, small differences between distributions are not significant when each method projects median lifetimes that are 180 orders of magnitude larger than the known age of the universe [18]! The important point to keep in mind is that the graphical representation (a line predicting reliability) is only a surrogate for the distribution data that generates the line. See Fig. 5 for a different viewpoint of the reliability prediction line.

Once the distribution is known, how do we make use of it? One of the most controversial issues in CS reliability is interpretation of results. For example, reliability engineers speak in terms of ‘‘median’’ lifetimes—when half of the population will fail. The issue is that customers want to know when the first part will degrade. Typically, this question begins another mathematical diversion into confidence levels and probabilities—more gobbledygook for those not familiar with reliability. A not-so-obvious answer could be to reduce the dispersion of the distribution, so that the time to the first failure and time to 50% failure are closer together. Another idea would be to dump references to median time, and report data for the first failure, such as a tppm (time to first part per million fail) instead of t50 (time to 50% failure.) Once the distribution shifts from the ‘‘middle’’ to the ‘‘front edge,’’ any separations between quality and reliability start to come together—as was signaled in the silicon generation; this is an indicator of the fourth era.

6. Using the right acceleration If we are to make predictions about reliability, we must be able to accelerate the failure mechanisms without generating new issues or masking mechanisms that may exist under reduced stress. Thermal acceleration is easy, but that does not make it the right thing to do. Understanding of mechanisms and degradation distributions can help us to look where acceleration might be less understood. To help, we need to talk more with our customers. Their use of the devices can give use clues as to what types of acceleration are more applicable. For example, thermal excursions, voltage, current density, and humidity might be preferable to high temperature acceleration. In other words, almost every part gets attached by a solder reflow (an extreme thermal excur-

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227

sion). Hopefully, they will all turn on (experience voltage fields and current flow). And eventually, they are likely to be exposed to an everyday environment (humidity). We can investigate the applicability of various stresses by talking with customers, or by use of an effectiveness chart. Remember, reliability folks need some kind of degradation to measure and predict metrics, so effectiveness means: how well do aging tests cause failure? Since we have already admitted that changes in reliability are meager, this type of graph is useful to guide our improvement efforts.

7. Overcoming mismatches in mechanisms How does one define importance? What should be the priority for reliability testing? How do reliability engineers know ‘‘what matters?’’ For any situation, a good answer is: ask your customer. For a reliability issue, just look at what causes your customers to return devices. Fig. 8 shows the causes of device returns for a five year time span. Notice that none of the problems that our customers report match with the six mechanisms previously mentioned in the historical recap! This should not be a surprise because most lifetime projections from Fig. 2 do not predict any wear-out for hundreds (even thousands) of years. What can be more important than a customer failure? If the stresses do not simulate what a customer does to the device, and the failures are not the same type that our customers report, then how can ‘‘standard’’ methodologies predict reliability in actual use? Following are some of the actual causes of failures from Fig. 6.

1223

cation problem. ESD is definitely an important subject, and it is being discussed more openly in recent years [19,20]. ESD is an issue that spans both silicon and compound semiconductors as the bulk size (volume) of semiconductors decrease. 7.2. Defects The second leading cause of customer problems is currently defects. However, this is not as clear an issue as ESD. Defects seem to rise up in the Pareto chart as all the other causes get solved and processes mature. Assembly and packaging or testing issues will sometimes outweigh defect issues in the development phases of semiconductor technologies. Remember the fifth era of silicon reliability improvement? It was five years of ‘‘major defect reduction effort’’. So, acknowledgement of defects as an issue is a positive sign that they will be addressed appropriately. The most commonly reported CS defects are found in capacitors. Several compound semiconductor manufacturers have reported studies on capacitors [21–24]. The mechanisms, distributions, and acceleration factors are understood and similar to what has been found on silicon devices—particularly for the focused improvements on ever thinner gate dielectrics. Other defects involving interconnect integrity and metal-to-metal leakages are newer issues for compound semiconductors. The distributions are familiar, but the mechanisms and acceleration factors appear to be specific to the technologies involved. Understanding these differences is likely to be one of the next challenges for compound semiconductors. [25]

7.1. ESD 8. Learning from our history From Fig. 6, electro-static discharge is the leading cause of problems reported by customers. This has been true as long as we have measured the causes. However, the compound semiconductor folks have tried to explain away this weakness as a technology difference or an edu-

EOS/ESD 24%

DESIGN 3% TEST 9%

DEFECT 18%

ASSY/PKG 13% No Fault Found 33%

Fig. 6. Results of root cause failure analysis of field returns since 1999.

With few exceptions, the reliability investigations on GaAs circuits over the past two decades have evolved to rely on thermally accelerated wear-out failure mechanisms (see Fig. 7). Regardless of the measured lifetimes, there have been very few wear-out failures reported during use of the circuits. Typically, the application issues of ESD, assembly issues of interfacing the devices to systems, manufacturing and logistics issues of getting the packaging and shipping systems synchronized will capture most of the attention. Buried under these initial start-up problems, customers do report measurable defect rates and early life failures that often match-up with yield fallout failure mechanisms. For the highest volume (>10 M/year) applications (such as cell phones), the early life mechanisms are significant. These volume applications have brought attention to the fifth era for compound semiconductors. Fig. 7 shows the historical fascination with thermal acceleration by the GaAs and compound semiconductor

160

20

04

02

03 20

01

20

99

00 20

20

98 19

19

97

96 19

19

95

94 19

19

93

92 19

19

91

90 19

19

88

89 19

19

19

19

86

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227 87

1224

0%

140

THERMAL ACCELERATION

10%

120

Degree C

30% 40% 50%

1980

1985

1990

1995

2000

2005

Year

NO RELIABILITY PREDICTION

Fig. 9. Reported temperature of operation (use temperature).

100%

Fig. 7. Type of acceleration reported at the reliability of compound semiconductor workshop (entire workshop history).

testing. Perhaps the reason for the popularity of thermal acceleration testing can be illustrated by the following data from the ROCS workshop and other CS reliability publications. Specific data on the actual accelerated test temperatures utilized is shown in Fig. 8. The data for the following summary graphs was collected over a 30-year history from 1975 to 2005. It represents 563 separate reliability aging tests. The primary source of the data is the ROCS workshop, but most of the CS reliability reports from the International Reliability Physics Symposium, Compound Semiconductor Mantech Conference, and the Compound Semiconductor IC Symposium are also included. These data represent much more than 32 million device hours of testing. Although testing has ranged from 0 to 500 C, most of the evaluations in recent years have been held between 200 C and 300 C. While most accelerated testing will report the test temperature, few of the studies will report the expected operating temperature. Fig. 9 shows the operating temperatures that have been reported. It is obvious that of those reporting use temperatures, the consensus is becoming 125 C. While it is refreshing to see this convergence in the reporting, it

does seem strange that the introduction of power amplifiers for cell phones does not appear to affect this type of graph—except that temperatures above 125 C have vanished during the period of the volume increase of HBT cell phone amplifiers? Fig. 10 shows the reported activation energies over the review period. Note that there is a similar moderation as to the test temperature graph (Fig. 8). Fig. 11 shows how the relationship between reported activation 3 2.5

400 300 200 100

1.5 1

0 1975

1980

1985

1990

1995

2000

Year

Fig. 8. Reported accelerated test temperatures.

2005

1990

1995

2000

2005

Fig. 10. Reported activation energies.

1.E+17 1.E+16 1.E+15 1.E+14 1.E+13 1.E+12 1.E+11 1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 0

1980

1985

Year

Projected Wearout (hours)

500

2

0.5

600

Degree C

60

0 1975

80%

0 1975

80

20

OTHER

70%

90%

100

40

60%

Electron Volts

Percentage of Papers

20%

0.5

1

1.5

2

2.5

3

3.5

Activation Energy (eV)

Fig. 11. Relationship of lifetimes to activation energies for reported compound semiconductor reliability studies.

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227 20000 18000 16000

Hours

14000 12000 10000 8000 6000 4000 2000 0 1975

1980

1985

1990

1995

2000

2005

Year

1225

is a ludicrous number, and perhaps that is the reason that sample sizes and tests durations have remained woefully low. The sample size goes unreported in most recent testing, and the median is only 10 parts per test. The average test duration is 1528 h, which seems insignificant compared to the predicted lifetimes. While examining all the reported results, one would be hard-pressed to find indications of overall improvements in methods or results over the past 20–30 years. There are a couple of de-facto standards that are apparent, such as the test temperature and particularly, the use temperature.

Fig. 12. Reported test durations of reliability aging.

10. What is next? The future for CS reliability 10000

Samples

1000

100

10

1 1975

1980

1985

1990

1995

2000

2005

Year

So now that some of the history has been reviewed, what should be done? For 20-years, we have touted the technology differences as a defense for the compound semiconductor niche; why not use the reliability differences as compelling advantages as well? Because of the unique mechanisms and absence of the silicon problems, compound semiconductors have an opportunity to use diversity to build a better ‘‘burn-in’’ and optimize the Bathtub curve. We propose a new goal for compound semiconductors: beat silicon!

Fig. 13. Reported sample size for reliability testing.

11. Strategy to beat silicon energies and predicted lifetimes. This is a most interesting graph to ponder. Should there be any relationship expected? If any is expected, should it look like this one? Following are graphs depicting trends observed over the recent history of Compound Semiconductor reliability testing. Fig. 12 shows reported lifetest durations and Fig. 13 shows the sample size of parts aged.

9. Discussion From the reported history, there is an obvious preference for thermally accelerated lifetesting. The median test temperature of compiled results is 230 C, and the range is decreasing with time. The average of the expected use temperature is 122 C and the data indicates that there is now a ‘‘standard’’ of 125 C. The history of all results indicate a need for projected lifetimes to exceed one million hours (114 years). This ‘‘requirement’’ has become an expectation through competition and example. Even though the desire to reach one million hour lifetimes is not driven by the historical data, the data does favor activation energies above 1.5 eV to ensure that goal. The average reported lifetime is 2.1 · 1014 h, or more than one hundred million times one million hours. This

In spite of our silicon rival’s size, it is not so wild a notion that the CS technologies could actually prevail in terms of a reliability comparison. Even with a full set of six eras under their belt, the silicon folks have a number of new issues of their own yet to solve. The relentless pursuit of Moore’s law has contributed to a continuous cycle of reliability challenges for the silicon technologies. Materials for mainstream silicon are new once more, and the engineers began the second generation of reliability improvement at the turn of the century, with most of the first era completed (again). 2005 is the cross-over year to begin characterization of new mechanisms for the silicon folks as they enter their second era.

12. Being innovative Armed with history and a goal, there are a few obvious tactics available to compound semiconductor companies. Some tactics can be turned-around upon the silicon folks, and some are unique. As the overall reliability improves, measuring degradation becomes elusive. If the CS folks intend to build experience that is familiar to the customers, we should proceed with tactics

1226

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227

Test Structure Quality (%per cm)

100

1.2G 1.1G

95

1G

90 85

0.9G

80 75

0.8G

70

0.6G

0.7G

65 0

10

20

30

40

50

60

70

80

90

100

wafer, test structures to speed reliability advancements and new material implementations. It will be important to apply knowledge of telltale failure signatures and customer returns with the use of in-line screening. Biasing methods of over-voltage, over-current, over-power are expected while quiescent and leakage current monitoring show promise. Perhaps hot or cold chuck probing will be needed as well. The defect reduction efforts of era 5 offer new territory to apply innovative tactics such as defect amplification, use of new environments, and/or pioneering accelerations to put CSs ahead of silicon.

Age (Volts)

Fig. 14. Quality vs. voltage for various normalized gap spacing of interconnects.

14. Conclusion

of building-in reliability and efforts to reduce defects. An illustration might be a more visible use of yield-to-reliability correlations as an example to predict failure rates. If yield fallout also disappears, we can use new tricks such as physical amplification of defects in order to extend our predictive capability [25]. An example of measuring quality as a function of voltage and amplified (reduced) spacing on test structures is shown in Fig. 14. Other recent CS breakthroughs with innovative tests such as ‘‘bubble tests’’, [26] and power cycling [27] are the kind of creative tactics that can put CSs ahead of our larger solid state relatives.

Customers are familiar with the silicon generation of reliability progress accomplished by the past 20-years of continuous improvement. Customers also have experience with problems of new technology, and a perception that compound semiconductor reliability may be lagging the main stream. The success of our efforts is cataloged and recorded in the workshop notes of the GaAs reliability workshop (now named the reliability of compound semiconductors workshop). These records provide a basis for customers to learn that compound semiconductors actually have a desired level of experience, maturity, and stability in terms of reliability.

13. Example of tasks ahead

Acknowledgements

If CS reliability is to be measured by the silicon yardstick, then there are two areas of focus with several important tasks ahead:

The author acknowledges all the authors, presenters, and participants in the past 20 GaAs reliability workshops. This annual gathering and discussion has contributed to the accumulation and dissemination of reliability knowledge for compound semiconductors.

1. Formalize the CS knowledge from the initial three reliability eras. Identify, define, and characterize the failure mechanisms for all CS materials in use. It is also important to match up the mechanisms with appropriate distributions and acceleration factors. That means high temperature stress should not be utilized when current density matters! The rigors of reliability physics are necessary for all mechanisms, not just when high temperature acceleration is employed. 2. Embrace the tactics of era 4 and 5 quickly and openly. Era 4 means more effort on building-in reliability. CS folks need to showcase progress on process control and the relentless search for mavericks, rouge lots, and outliers. There must be continued development of fast, on

References [1] Menozzi R. Dipartimento di Ingegneria dell’Informazione, Universita’ di Parma, Private e-mail November 24, 2004, complied from history of the GaAs reliability workshop— called the ROCS workshop after 2003. [2] Stork H. Reliability challenges for sub-100 nm system on chip technologies, Keynote address. In: International reliability physics symposium (IRPS), 2004. [3] Roesch W, Rubalcava T, Hanson C. Lifetesting GaAs MMICs under RF stimulus. IEEE Trans Microw Theory Tech 1992;40(12):2452–60. [4] Chou YC. et al. On the investigation of gate metal interdiffusion in GaAs HEMTs. In: GaAs IC symposium, 2003. p. 63–6. [5] Roesch W, Stunkard D. Proving GaAs reliability with IC element testing. In: US conference on GaAs manufacturing technology, 1988. p. 91–5.

W.J. Roesch / Microelectronics Reliability 46 (2006) 1218–1227 [6] Casey HC, Pearson GL. Diffusion in semiconductors, Point defects in solids, vol. Z, Plenum, 1975. [7] Cholan H, Stunkard D, Rubalcava T. Long-term effects of sidegating on GaAs MESFETs. IRPS 1992:49–53. [8] Wantanabe A et al. Rapid degradation of WSi selfalighned gate GaAs MESFET by hot carrier effect. IRPS 1992:127–30. [9] Asbeck P, Lee C, Chang M. Piezoelectric effects on GaAs FETs and their role in orientation-dependent device characteristics. IEEE Trans Electron Dev 1984;ED31(October):1377–80. [10] Camp W et al. Hydrogen effects on reliability of GaAs MMICs. In: IEEE GaAs IC symposium, 1989. p. 203–06. [11] Mertens S, del Alamo J. A model for hydrogen-induced piezoelectric effect in InP HEMTs and GaAs PHEMTs. IEEE Trans Eletron Dev 2002;49(11):1849–55. [12] Surridge B. et al. Accelerated reliability testing of InGaP/ GaAs HBTs. In: GaAs Mantech conference, 2002. p. 37–1. [13] Henderson T. A physics-based model for excess leakage current in GaAs/AlGaAs HBTs after bias stress. In: GaAs REL workshop, 1996. p. 2–10. [14] Dunn J et al. Trends in silicon germanium BiCMOS integration and reliability. IRPS 2000:237–42. [15] Roesch W, Winters R, Rubalcava T, Ingle B. Humidity resistance of GaAs ICs. IEEE GaAs IC Symp 1994:251–4. [16] Ersland P, Jen H, Yang X. Lifetime acceleration model for hast tests on a pHEMT process. In: GaAs REL workshop, 2003. p. 3–6. [17] Hisaka T et al. Degradation mechanisms of GaAs pHEMTs in high humidity conditions. In: Reliability of compound semiconductors (ROCS) workshop, 2004. p. 81–8. [particularly slide #10].

1227

[18] Whitman C, Meeder M. Determining constant voltage lifetimes for silicon nitride capacitors in a GaAs IC process by a step stress method. In: ROCS workshop, 2004. p. 91– 119. [particularly slide #10]. [19] Poe A, Brockett S, Rubalcava T. Failure analysis of CDM ESD damage in a GaAs RFIC. In: International symposium for testing and failure analysis, Bellevue, WA, November 2000. [20] Whitman CS, Gilbert T, Rahn A, Antonell JA, C. Determining factors affecting ESD failure voltage using DOE. In: ROCS workshop, 2005. [21] Scarpulla J, Ahlers E, Eng D, Leung D, Olsen S, Wu C. Dielectric breakdown, defects, and reliability in SiN MIMCAPs. In: GaAs REL workshop, 1998. p. 92–105. [22] Cramer H, Oliver J, Dix G. MMIC capacitor dielectric reliability. In: GaAs REL workshop, 1998. p. 46–51. [23] Yeats B. Assessing the reliability of silicon nitride capacitors in a GaAs IC process. IEEE Trans Electron Dev 1998;45(4):939–46. [24] Brophy M, Torrejon A, Peterson S, Avala K, Liu L. MIM’s the word—capacitors for fun and profit. GaAs Mantech 2003:57–9. [25] Roesch W, Hamada D. Studying yield and reliability relationships for metal defects. In: ROCS workshop, 2004. p. 121–33. [26] Roesch W, Peterson S, Poe A, Brockett S, Mahon S, Bruckner J. Assessing circuit hermeticity by electrolysis. GaAs Mantech conference 2000:121–4. [27] Roesch W. Thermal excursion accelerating factors. GaAs REL workshop, 1999. p. 119–26.