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Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests
MR-11693; No of Pages 4 Microelectronics Reliability xxx (2015) xxx–xxx
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests M.A. Belaïd ⁎ SAGE-ENISo, National Engineering School of Sousse, 4023 University of Sousse, Tunisia
a r t i c l e
i n f o
Article history: Received 22 May 2015 Received in revised form 30 June 2015 Accepted 1 July 2015 Available online xxxx Keywords: Rise time Fall time Switching MOS Aging tests Hot carrier effects Reliability
a b s t r a c t This paper investigates the effects of hot carrier injection on the switching performance of power RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices. In addition, their influences on the dynamic parameters are studied after various accelerated aging tests (thermal and electrical). The response of these parameters and the switching waveform are described. The findings of experimental results are presented and discussed. Measurements show that important variations are obtained on the devices' rise time. After aging tests, the charge trapping in the gate oxide causes the modifications in the Miller capacity level and width resulting in an increase of the rise time and a decrease in the fall time, consequently increasing of the switching losses. © 2015 Elsevier Ltd. All rights reserved.
1. Introduction Power MOSFETs have widely used in applications space systems, particularly in DC/DC power conversion. The major interest for industry, mainly space industry is the use of the devices that can withstand high temperature and/or high voltage operations, where we need to avoid the use of large cooling systems. MOSFET devices are very fast switchers and they are widely used in the industry because they provide at the same time a combination of fast switching and low on-resistance [1]. The switching time variations of power MOSFETs are still on the agenda from the reliability point of view because the gate oxide degradation effects the switching characteristics. The electrical and/or thermal stress changes the interface and oxide charges into the gate oxide and these charges cause degradation in power MOSFETs parameters such as threshold voltage, mobility and terminal capacitances which alter the switching parameters [2]. Due to the increased demand on reliability and safe operation, it is necessary to investigate the MOSFET devices behavior under various running conditions. The work methodology consists in characterizing the device parameters before and after aging, for comparing their performances under various test conditions. The switching speed evolution of MOSFETs is seldom studied from the reliability viewpoint, knowing that the oxide charge effect does not exclude the altering of switching parameters [3]. The electrical parameters evolution and their relation with the oxide layer charge ⁎ Corresponding author. E-mail address: [email protected] (M.A. Belaïd).
after various accelerated aging tests were largely studied in [4,5]. Particularly, the dynamic parameter drifts of power RF LDMOS devices. We investigated in this work, the switching times and dynamic parameters of MOSFET devices after accelerated tests. The content of this paper is presented as follows: Section 2 describes the experimental characterization set-up and the general LDMOS transistor performances. The discussion and results are shown in Section 3. The conclusion and prospects is given in Section 4. 2. Characterization and experiment setup – general power RF LDMOS transistor performances The buck converter structure is represented in Fig. 1. To characterize the switching waveform and the voltage switching period (VSP) we use a particular circuit which is representative of the static converter circuits: a series chopper (buck). This circuit is a DC/DC converter but it is also found in the arms of an inverter, so it is also representative of the DC/AC energy conversion. It has the following specifications: power supply = 25 V; output voltage = 12.5 V; power = 10 W; commutation frequency f = 50 kHz; and duty cycle = 50%. The switching cell is constituted by an RF-LDMOS transistor and a Schottky diode across the DC motor. For the device characteristics, no disappearances are observed. The RF-LDMOS device under test is a commercial telecom dedicated transistor (encapsulated in a 2-lead flange package with a ceramic cap) S-band operating and 65 V DC biasing. Indeed, these performances are given in conditions of width pulse 500 μs with a duty cycle of 50%. The
http://dx.doi.org/10.1016/j.microrel.2015.07.002 0026-2714/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002
2
M.A. Belaïd / Microelectronics Reliability xxx (2015) xxx–xxx Table 1 Summary of the various tests conditions. Test
Temperatures
ΔT
Ids at Tamb
TCT HVD
−75 °C/+75 °C Tamb
150 °C ‐‐
Without DC 3 mA
The implemented structure is typically similar to our tested device. Consequently the qualitative understanding of physical phenomenon will be studied. The suggested structure has a Gaussian doping profile along LDD and channel surface. The doping profile was optimized using a technological process simulation carried out by SSUPREM3 [7,13], see Fig. 3. 3. Results and discussion
A modified structure of RF power N channel LDMOS, previously developed by Raman et al. [6], was implemented and simulated using the physical simulator Atlas of Silvaco [7]. Fig. 3 shows the device's structure with approximate doping wells. The main geometrical and technological parameters are given in Table 2.
Fig. 4 presents the comparison between the Vds(t) switching waveform at the cell bound before and after aging test. The switching losses are changed (see Table 3) but the devices are still in their specified range after test. Under these conditions, the electrical test induces faster degradation than the thermal test. Fig. 5 shows the aging influence and the rise time (time taken by a signal to change from a low value to a specified high value) parameter degradation at the cell bound of Vds waveform switching. Table 3 presents the rise time evolution and fall time after each aging test. We note that rise time increases depending of aging. The electrical aging test induces major degradation of rise time than in the thermal aging. Fig. 6 presents the fall time (is the time taken for the amplitude decrease from a value to another specified value) degradation of Vds waveform with various accelerated aging tests. The power RF LDMOS switching begins by charging the gate-channel capacity in order to invert the semiconductor surface when the gate voltage is above the threshold voltage. Table 4 presents, the peak amplitude evolution at resonant frequency (9 MHz) before and after aging and also the values of the largest increases in the spectra. This is given at the transistor's Turn-ON and Turn-OFF. Study [5] shows that these aging tests of power RF LDMOS devices causes a degradation in electrical parameters such as: threshold voltage, Cgd, Cgs and Crss (see Table 5) [5,8]. These parameter shift due to change of physical properties caused by hot-carrier effect [5,10,11], thereafter affecting in both on the switching time. The study presented in [1] shows the aging component which can have another effect: the stressed device reduces the rise time; thereafter, it will decrease the Cgd capacitance of 31% after electrical aging [5] (see Table 5). In the chopper application, the most important capacitance for dynamic behavior is Cgd [12,13]. Precisely, they showed
Fig. 2. Typical temperature profile.
Fig. 3. Cross-section view 2D of RF-LDMOS with net doping profile along silicon surface implemented in Silvaco-Atlas software.
Fig. 1. Characterization circuit of switching time.
gate length is equal to 0.8 μm. The junction temperature does not exceed 150 ° C for a flange temperature equal to 65 ° C. The thermal resistance is 0.2 C/W. For this study, the devices are stressed with an applied drain-source voltage (Vds) of 40 V and a gate-source voltage (Vgs) necessary to obtain a permanent drain-source current (Ids) less than 20 mA (without selfheating effect), which corresponds to the quiescent current at ambient temperature. The transistors have been characterized before and after aging tests following [5,8]: ⁎ Transistors after thermal aging (Thermal Cycling Tests: TCT), on which 10 thermal cycles without interruption of 10 min for each cycle (from − 75 °C to 75 °C with ΔT = 150 °C) without DC bias (Fig. 2) [5,14]. ⁎ Transistors after DC electrical aging (High Voltage Drain: HVD), where a Vds voltage equal to 40 V and a Vgs voltage equal to 3.5 V during 15 h are applied. The conditions are investigated in order to establish an unequivocal conclusion on the comparison of the different tests (Table 1).
Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002
M.A. Belaïd / Microelectronics Reliability xxx (2015) xxx–xxx
3
Vds
Table 2 Device dimensions. Parameter
Value (μm)
Source length Source-gate spacing Gate length Gate-drain spacing Drain length Gate oxide thickness
1.1 1 0.8 3 1.1 0.065
25
Voltage (V)
20
15
Aging effect 10
Vds
Before aging After thermal aging After electrical aging
5
25 -10.5
15
-9.5
-9
-8.5
-8 -6
x 10
Fig. 5. Rise time evolution after thermal and electrical aging.
10
Before aging 5
After thermal aging After electrical aging
0 -12
-10
Time(s)
-10
-8
-6
-4
-2
0
2 -6
Time(s)
x 10
Fig. 4. Vds switching waveform after aging tests.
that an increase in the value of the Cgd caused a decrease in both the amplitudes and the resonance frequencies of the spectra. It dominates the output switching waveforms through the ‘Miller’ effects. The switching performance shifts in the power LDMOSFET can bring changes in the primary voltage and current [9]. The transient performance of the power device changed after stress. The power efficiency is related to this regime of the switching devices [9]. Therefore, according to the previous works [12,13], this important decrease of the Cgd value explains the switching time shift observed. The decrease in the capacitances (Cgd and Crss) after thermal aging is lower than after electric aging [10]. This explains why the increase of the switching time shifts is more important after electric aging than after thermal aging. The electric parameters of MOS transistor are more and more sensitive to defects bound to the presence of charges in the gate oxide and at the Si/SiO2 interface [5,10]. According to the literature [1,5,11], the cause and the origin of the observed shift related to the presence of very high electric field that increases carrier injection into the grown silicon dioxide layer (SiO2) and into interface state Si/SiO2 [5,15]. The detail of the lateral electric field distribution of the active silicon layer in channel and drift regions is shown in Fig. 7, using a physical simulation software
(Silvaco-Atlas, 2D). This strong electric field causes the generation of charge states at the silicon–oxide interface [9,16]. The hot carrier degradation effect is closely related with current density and with the total number of free electrons at the silicon–oxide interface, where most of the electrons are concentrated deep inside the drift region [15–17]. Hence, the electron concentration contours across the active silicon layer can be observed from Fig. 8. It could be noticed that the concentration is very high at the gate level, on the right (drain side) in such a way that it provides a significant increase of the surface current density at the gate edge. Consequently, many electrons are accelerated to high velocities by this high electric field peak. They become highly energized and should be accelerated away from their normal directional flow. In other words, the drain–source voltage increases the electric field in the drift region and near the oxide layer, therefore enhancing the trapping process. So, the degradation [14,18] is attributed to hot electron-induced interface state generation and/or impact ionization.
Vds 25
Before aging After thermal aging After electrical aging
20
Voltage (V)
Voltage (V)
20
15
Aging effect 10
5 Table 3 Evolution of rise time and fall time after each aging test (%: percentage change).
0
After aging Before aging
Rise time (10−6 s) Fall time (10−7 s)
1.012 5.217
Thermal
Electrical
-4
Value
%
Value
%
1.006 5.191
6 1
0.816 5.019
19 5
0
2
4
6
Time(s)
8
10 -7
x 10
Fig. 6. Fall time profile before and after aging test.
Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002
4
M.A. Belaïd / Microelectronics Reliability xxx (2015) xxx–xxx
Table 4 Peak amplitude evolution (dB mV) before and after aging at resonance frequency (9 MHz). After aging Before aging
Turn-OFF Turn-ON All period
11.31 15.36 18.37
Thermal
Electrical
Value
ΔV
Value
ΔV
20.47 17.2 24.81
+9.16 +1.87 +6.44
22.47 17.47 36.99
+11.16 +2.27 +18.62
Table 5 Dynamic parameter values variations obtained after aging tests (%: percentage change). Parameters
Before aging
After aging Thermal
Crss (pF) Vds = 0 V Vds = 28 V Cgd (pF) Vgd = −1.5 V Cgs (pF) Vgs = 0 V
2.73 0.57 1.90 12.5
Electrical
Value
%
Value
%
2.72 0.57 1.90 12.5
0.36 0 0 0
2.60 0.50 1.31 12.5
4.76 12.3 31 0
Fig. 8. Electron concentration distribution of N-LDMOS, with Vds = 40 V and Vgs = 3.5 V bias.
4. Conclusion and prospects Acknowledgements The results obtained for power RF LDMOS devices highlighted that switching time shifts are important in electrical aging tests. Stressing that, during one switching period, the rise time degradation is faster and more important than fall time. The gate oxide of the devices is subjected to a high field in order to induce defects in the oxide layer and/or at the Si/SiO2 interface. This phenomenon degrades the physical behavior of device, thereafter the critical dynamic parameters (Cgd and Crss); that are sensitive to the electrons injected in gate/SiO2 interface traps. These charges affect the switching parameters by increasing the rise time and by decreasing the fall time. The switching performance study of power RF LDMOS devices shows that it is sensitive to oxide degradation. These problems are of major concern for power MOSFETs performance and can be solved via the driving stage. Extensive tests for switching are needed to improve the overall converter reliability. The experimental results will be followed and confirmed by a detailed simulation analysis. Moreover, it would be interesting to make the connection with the normal life of a component, through an aging model or MTTF (mean time to failure) if we have all data. The comparison of this study with other technologies such as IGBT and VDMOS is underway.
Fig. 7. Lateral electric field distribution in N-LDMOS structure, with Vds = 40 V and Vgs = 3.5 V bias.
The author wish to thank Ms. Ben Amara Najoua Essoukri, Prof. at Engineering National School of Sousse (ENISo) and Director of SAGE Laboratory (Sousse University), for her great help and her encouragement. References [1] R. Habchi, et al., Switching times variation of MOSFET devices with temperature and high-field stress, Microelectron. J. (2008) 828–831. [2] A. Michez, et al., Modeling dose effects in electronics devices: dose and temperature dependence of power MOSFET, Microelectron. Reliab. (2013) 1306–1310. [3] R. Habchi, et al., Switching times variation of power MOSFET devices after electrical stress, Microelectron. Reliab. (2007) 1296–1299. [4] M. TLIG, et al., Power RF N-LDMOS Ageing Effect on Conducted Electromagnetic Interferences, IEEE on Signal, System & Devices (SSD), Tunisia, 2013. 1–5. [5] M.A. Belaid, et al., Evaluation of hot-electron effects on critical parameter drifts in power RF LDMOS transistors, Microelectron. Reliab. (2010) 1763–1767. [6] M.A. Belaïd, et al., Analysis and Simulation of Self-Heating Effects on RF LDMOS Devices, IEEE Simulation of Semiconductor Processes and Devices (SISPAD)2005. 231–234. [7] A. Raman, et al., Simulation of nonequilibrium thermal effects in power LDMOS transistors, Solid State Electron. 47 (2003) 1265–1273. [8] M.A. Belaïd, K. Ketata, K. Mourgues, M. Masmoudi, Reliability study of power RF LDMOS device under thermal stress, Microelectron. J. 70 (2007) (pp. 38:164). [9] Jiann S. Yuan, PhD: Hot Carrier Effect on ldmos Transistors, in the School of Electrical Engineering and Computer Science, in the College of Engineering and Computer Science at the University of Central Florida, 2007. [10] I. Starkov, et al., Local oxide capacitance as a crucial parameter for characterization of hot-carrier degradation in long-channel n-MOSFETs, J. Vac. Sci. Technol. B (2013) 1180–1187. [11] J. Yuan, et al., Evaluation of hot-electron effect on LDMOS device and circuit performances, IEEE Trans. Electron Devices (2008) 1519–1523. [12] J. Ben Hadj Slama, M. Tlig, Effect of the MOSFET Choice on Conducted EMI in Power Converter Circuits, 16th IEEE Mediterranean Electrotechnical Conference MELECON2012. (Tunisia). [13] M. Tlig, J. Ben Hadj Slama, M.A. Belaid, Conducted and radiated EMI evolution of power RF N-LDMOS after accelerated ageing tests, Microelectron. Reliab. (2013) 1793–1797. [14] M.A. Belaïd, K. Ketata, M. Masmoudi, M. Gares, H. Maanane, J. Marcon, Electrical parameters degradation of power RF LDMOS device after accelerated ageing tests, Microelectron. Reliab. (2006) 1800–1805. [15] I. Corte' s, J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo, Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile, Microelectron. Reliab. 45 (2005) 493–498. [16] D. Brisbin, A. Strachan, P. Chaparala, Optimizing the hot carrier reliability of N-LDMOS transistor arrays, Microelectron. Reliab. 45 (2005) 1021–1032. [17] T. Nigam, A. Shibib, S. Xu, H. Safar, L. Steinberg, Nature and location of interface traps in RF LDMOS due to the hot carriers, Microelectron. Eng. 72 (2004) 71–72. [18] B.S. Doyle, K.R. Mistry, D.B. Jackson, Examination of gradual junction p-MOS structures for hot carrier control using a new lifetime extraction method, IEEE Trans. Electron Devices 39 (1992) 10.
Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/mr
Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests M.A. Belaïd ⁎ SAGE-ENISo, National Engineering School of Sousse, 4023 University of Sousse, Tunisia
a r t i c l e
i n f o
Article history: Received 22 May 2015 Received in revised form 30 June 2015 Accepted 1 July 2015 Available online xxxx Keywords: Rise time Fall time Switching MOS Aging tests Hot carrier effects Reliability
a b s t r a c t This paper investigates the effects of hot carrier injection on the switching performance of power RF LDMOS (Radio Frequency Lateral Diffused Metal–Oxide–Semiconductor) devices. In addition, their influences on the dynamic parameters are studied after various accelerated aging tests (thermal and electrical). The response of these parameters and the switching waveform are described. The findings of experimental results are presented and discussed. Measurements show that important variations are obtained on the devices' rise time. After aging tests, the charge trapping in the gate oxide causes the modifications in the Miller capacity level and width resulting in an increase of the rise time and a decrease in the fall time, consequently increasing of the switching losses. © 2015 Elsevier Ltd. All rights reserved.
1. Introduction Power MOSFETs have widely used in applications space systems, particularly in DC/DC power conversion. The major interest for industry, mainly space industry is the use of the devices that can withstand high temperature and/or high voltage operations, where we need to avoid the use of large cooling systems. MOSFET devices are very fast switchers and they are widely used in the industry because they provide at the same time a combination of fast switching and low on-resistance [1]. The switching time variations of power MOSFETs are still on the agenda from the reliability point of view because the gate oxide degradation effects the switching characteristics. The electrical and/or thermal stress changes the interface and oxide charges into the gate oxide and these charges cause degradation in power MOSFETs parameters such as threshold voltage, mobility and terminal capacitances which alter the switching parameters [2]. Due to the increased demand on reliability and safe operation, it is necessary to investigate the MOSFET devices behavior under various running conditions. The work methodology consists in characterizing the device parameters before and after aging, for comparing their performances under various test conditions. The switching speed evolution of MOSFETs is seldom studied from the reliability viewpoint, knowing that the oxide charge effect does not exclude the altering of switching parameters [3]. The electrical parameters evolution and their relation with the oxide layer charge ⁎ Corresponding author. E-mail address: [email protected] (M.A. Belaïd).
after various accelerated aging tests were largely studied in [4,5]. Particularly, the dynamic parameter drifts of power RF LDMOS devices. We investigated in this work, the switching times and dynamic parameters of MOSFET devices after accelerated tests. The content of this paper is presented as follows: Section 2 describes the experimental characterization set-up and the general LDMOS transistor performances. The discussion and results are shown in Section 3. The conclusion and prospects is given in Section 4. 2. Characterization and experiment setup – general power RF LDMOS transistor performances The buck converter structure is represented in Fig. 1. To characterize the switching waveform and the voltage switching period (VSP) we use a particular circuit which is representative of the static converter circuits: a series chopper (buck). This circuit is a DC/DC converter but it is also found in the arms of an inverter, so it is also representative of the DC/AC energy conversion. It has the following specifications: power supply = 25 V; output voltage = 12.5 V; power = 10 W; commutation frequency f = 50 kHz; and duty cycle = 50%. The switching cell is constituted by an RF-LDMOS transistor and a Schottky diode across the DC motor. For the device characteristics, no disappearances are observed. The RF-LDMOS device under test is a commercial telecom dedicated transistor (encapsulated in a 2-lead flange package with a ceramic cap) S-band operating and 65 V DC biasing. Indeed, these performances are given in conditions of width pulse 500 μs with a duty cycle of 50%. The
http://dx.doi.org/10.1016/j.microrel.2015.07.002 0026-2714/© 2015 Elsevier Ltd. All rights reserved.
Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002
2
M.A. Belaïd / Microelectronics Reliability xxx (2015) xxx–xxx Table 1 Summary of the various tests conditions. Test
Temperatures
ΔT
Ids at Tamb
TCT HVD
−75 °C/+75 °C Tamb
150 °C ‐‐
Without DC 3 mA
The implemented structure is typically similar to our tested device. Consequently the qualitative understanding of physical phenomenon will be studied. The suggested structure has a Gaussian doping profile along LDD and channel surface. The doping profile was optimized using a technological process simulation carried out by SSUPREM3 [7,13], see Fig. 3. 3. Results and discussion
A modified structure of RF power N channel LDMOS, previously developed by Raman et al. [6], was implemented and simulated using the physical simulator Atlas of Silvaco [7]. Fig. 3 shows the device's structure with approximate doping wells. The main geometrical and technological parameters are given in Table 2.
Fig. 4 presents the comparison between the Vds(t) switching waveform at the cell bound before and after aging test. The switching losses are changed (see Table 3) but the devices are still in their specified range after test. Under these conditions, the electrical test induces faster degradation than the thermal test. Fig. 5 shows the aging influence and the rise time (time taken by a signal to change from a low value to a specified high value) parameter degradation at the cell bound of Vds waveform switching. Table 3 presents the rise time evolution and fall time after each aging test. We note that rise time increases depending of aging. The electrical aging test induces major degradation of rise time than in the thermal aging. Fig. 6 presents the fall time (is the time taken for the amplitude decrease from a value to another specified value) degradation of Vds waveform with various accelerated aging tests. The power RF LDMOS switching begins by charging the gate-channel capacity in order to invert the semiconductor surface when the gate voltage is above the threshold voltage. Table 4 presents, the peak amplitude evolution at resonant frequency (9 MHz) before and after aging and also the values of the largest increases in the spectra. This is given at the transistor's Turn-ON and Turn-OFF. Study [5] shows that these aging tests of power RF LDMOS devices causes a degradation in electrical parameters such as: threshold voltage, Cgd, Cgs and Crss (see Table 5) [5,8]. These parameter shift due to change of physical properties caused by hot-carrier effect [5,10,11], thereafter affecting in both on the switching time. The study presented in [1] shows the aging component which can have another effect: the stressed device reduces the rise time; thereafter, it will decrease the Cgd capacitance of 31% after electrical aging [5] (see Table 5). In the chopper application, the most important capacitance for dynamic behavior is Cgd [12,13]. Precisely, they showed
Fig. 2. Typical temperature profile.
Fig. 3. Cross-section view 2D of RF-LDMOS with net doping profile along silicon surface implemented in Silvaco-Atlas software.
Fig. 1. Characterization circuit of switching time.
gate length is equal to 0.8 μm. The junction temperature does not exceed 150 ° C for a flange temperature equal to 65 ° C. The thermal resistance is 0.2 C/W. For this study, the devices are stressed with an applied drain-source voltage (Vds) of 40 V and a gate-source voltage (Vgs) necessary to obtain a permanent drain-source current (Ids) less than 20 mA (without selfheating effect), which corresponds to the quiescent current at ambient temperature. The transistors have been characterized before and after aging tests following [5,8]: ⁎ Transistors after thermal aging (Thermal Cycling Tests: TCT), on which 10 thermal cycles without interruption of 10 min for each cycle (from − 75 °C to 75 °C with ΔT = 150 °C) without DC bias (Fig. 2) [5,14]. ⁎ Transistors after DC electrical aging (High Voltage Drain: HVD), where a Vds voltage equal to 40 V and a Vgs voltage equal to 3.5 V during 15 h are applied. The conditions are investigated in order to establish an unequivocal conclusion on the comparison of the different tests (Table 1).
Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002
M.A. Belaïd / Microelectronics Reliability xxx (2015) xxx–xxx
3
Vds
Table 2 Device dimensions. Parameter
Value (μm)
Source length Source-gate spacing Gate length Gate-drain spacing Drain length Gate oxide thickness
1.1 1 0.8 3 1.1 0.065
25
Voltage (V)
20
15
Aging effect 10
Vds
Before aging After thermal aging After electrical aging
5
25 -10.5
15
-9.5
-9
-8.5
-8 -6
x 10
Fig. 5. Rise time evolution after thermal and electrical aging.
10
Before aging 5
After thermal aging After electrical aging
0 -12
-10
Time(s)
-10
-8
-6
-4
-2
0
2 -6
Time(s)
x 10
Fig. 4. Vds switching waveform after aging tests.
that an increase in the value of the Cgd caused a decrease in both the amplitudes and the resonance frequencies of the spectra. It dominates the output switching waveforms through the ‘Miller’ effects. The switching performance shifts in the power LDMOSFET can bring changes in the primary voltage and current [9]. The transient performance of the power device changed after stress. The power efficiency is related to this regime of the switching devices [9]. Therefore, according to the previous works [12,13], this important decrease of the Cgd value explains the switching time shift observed. The decrease in the capacitances (Cgd and Crss) after thermal aging is lower than after electric aging [10]. This explains why the increase of the switching time shifts is more important after electric aging than after thermal aging. The electric parameters of MOS transistor are more and more sensitive to defects bound to the presence of charges in the gate oxide and at the Si/SiO2 interface [5,10]. According to the literature [1,5,11], the cause and the origin of the observed shift related to the presence of very high electric field that increases carrier injection into the grown silicon dioxide layer (SiO2) and into interface state Si/SiO2 [5,15]. The detail of the lateral electric field distribution of the active silicon layer in channel and drift regions is shown in Fig. 7, using a physical simulation software
(Silvaco-Atlas, 2D). This strong electric field causes the generation of charge states at the silicon–oxide interface [9,16]. The hot carrier degradation effect is closely related with current density and with the total number of free electrons at the silicon–oxide interface, where most of the electrons are concentrated deep inside the drift region [15–17]. Hence, the electron concentration contours across the active silicon layer can be observed from Fig. 8. It could be noticed that the concentration is very high at the gate level, on the right (drain side) in such a way that it provides a significant increase of the surface current density at the gate edge. Consequently, many electrons are accelerated to high velocities by this high electric field peak. They become highly energized and should be accelerated away from their normal directional flow. In other words, the drain–source voltage increases the electric field in the drift region and near the oxide layer, therefore enhancing the trapping process. So, the degradation [14,18] is attributed to hot electron-induced interface state generation and/or impact ionization.
Vds 25
Before aging After thermal aging After electrical aging
20
Voltage (V)
Voltage (V)
20
15
Aging effect 10
5 Table 3 Evolution of rise time and fall time after each aging test (%: percentage change).
0
After aging Before aging
Rise time (10−6 s) Fall time (10−7 s)
1.012 5.217
Thermal
Electrical
-4
Value
%
Value
%
1.006 5.191
6 1
0.816 5.019
19 5
0
2
4
6
Time(s)
8
10 -7
x 10
Fig. 6. Fall time profile before and after aging test.
Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002
4
M.A. Belaïd / Microelectronics Reliability xxx (2015) xxx–xxx
Table 4 Peak amplitude evolution (dB mV) before and after aging at resonance frequency (9 MHz). After aging Before aging
Turn-OFF Turn-ON All period
11.31 15.36 18.37
Thermal
Electrical
Value
ΔV
Value
ΔV
20.47 17.2 24.81
+9.16 +1.87 +6.44
22.47 17.47 36.99
+11.16 +2.27 +18.62
Table 5 Dynamic parameter values variations obtained after aging tests (%: percentage change). Parameters
Before aging
After aging Thermal
Crss (pF) Vds = 0 V Vds = 28 V Cgd (pF) Vgd = −1.5 V Cgs (pF) Vgs = 0 V
2.73 0.57 1.90 12.5
Electrical
Value
%
Value
%
2.72 0.57 1.90 12.5
0.36 0 0 0
2.60 0.50 1.31 12.5
4.76 12.3 31 0
Fig. 8. Electron concentration distribution of N-LDMOS, with Vds = 40 V and Vgs = 3.5 V bias.
4. Conclusion and prospects Acknowledgements The results obtained for power RF LDMOS devices highlighted that switching time shifts are important in electrical aging tests. Stressing that, during one switching period, the rise time degradation is faster and more important than fall time. The gate oxide of the devices is subjected to a high field in order to induce defects in the oxide layer and/or at the Si/SiO2 interface. This phenomenon degrades the physical behavior of device, thereafter the critical dynamic parameters (Cgd and Crss); that are sensitive to the electrons injected in gate/SiO2 interface traps. These charges affect the switching parameters by increasing the rise time and by decreasing the fall time. The switching performance study of power RF LDMOS devices shows that it is sensitive to oxide degradation. These problems are of major concern for power MOSFETs performance and can be solved via the driving stage. Extensive tests for switching are needed to improve the overall converter reliability. The experimental results will be followed and confirmed by a detailed simulation analysis. Moreover, it would be interesting to make the connection with the normal life of a component, through an aging model or MTTF (mean time to failure) if we have all data. The comparison of this study with other technologies such as IGBT and VDMOS is underway.
Fig. 7. Lateral electric field distribution in N-LDMOS structure, with Vds = 40 V and Vgs = 3.5 V bias.
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Please cite this article as: M.A. Belaïd, Impact of hot carrier injection on switching time evolution for power RF LDMOS after accelerated tests, Microelectronics Reliability (2015), http://dx.doi.org/10.1016/j.microrel.2015.07.002