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Implementation of Logarithmic Number Systems in control application using FPGA
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ScienceDirect IFAC PapersOnLine 52-27 (2019) 502–507
Implementation Implementation of of Logarithmic Logarithmic Number Number Systems Systems in in control control application application using using Implementation of Logarithmic Number Systems in control application FPGA FPGASystems in control application using Implementation of Logarithmic Number using FPGA FPGA
Ivan Klimo, Michal Kocúr, Peter Drahoš Ivan Klimo, Michal Kocúr, Peter Drahoš Ivan Klimo, Michal Kocúr, Peter Drahoš Ivan Klimo, Michal Kocúr, Peter Drahoš Institute Mechatronics, Institute of of Automotive Automotive Mechatronics, Faculty of Electrical Engineering and Information Institute Engineering of Automotive Mechatronics, Faculty of Electrical and Information Technology, Technology, Institute of Automotive Mechatronics, Slovak University of Technology in Bratislava, Slovakia Slovak UniversityEngineering of Technology Bratislava, Technology, Slovakia Faculty of Electrical andinInformation Faculty of Electrical Engineering and Information Technology, (e-mail: [email protected]) (e-mail: [email protected]) Slovak University of Technology in Bratislava, Slovakia (e-mail: [email protected]) Slovak University of Technology in Bratislava, Slovakia (e-mail: [email protected]) (e-mail: [email protected]) Abstract: Abstract: This This paper paper deals deals with with aa different different approach approach to to hardware hardware implementation implementation of of PI PI controller. controller. Logarithmic Number (LNS) are number instead of of classic, classic, floating point Abstract: This paper Systems deals with a different approach hardware implementation of PI controller. Logarithmic Number Systems (LNS) are used used for for numbertorepresentation representation instead floating point Abstract: This paper deals with a different approach to hardware implementation of PI controller. (FLP) or fixed point (FP) representation. The comparison and pros and cons of these representation are Logarithmic Number Systems (LNS) are used number representation instead classic, floating point (FLP) or fixed point (FP) representation. The for comparison and pros and cons of of these representation are Logarithmic Number Systems (LNS) are used for number representation instead of classic, floating point presented.The results shows, that using LNS can be another way to implement controllers. The presented.The shows, that usingThe LNS can be another to implement controllers. The (FLP) or fixed results point (FP) representation. comparison and prosway and cons of these representation are (FLP) or fixed point representation. The comparison and pros and cons of these representation are implementation were (FP) realized onthat Field Programmable Gate arrays (FPGA). presented.The results shows,on using LNS can Gate be another way to implement controllers. The implementation were realized Field Programmable arrays (FPGA). presented.The results shows, that using LNS can be another way to implement controllers. The implementation wereFPGA, realized on Field Programmable Gate arrays (FPGA). © 2019, IFAC (International Federation of Automatic Hosting by Elsevier Ltd. All rights reserved. Keywords: Control, LNS, floating points. Control) implementation wereFPGA, realized on Field Programmable Gate arrays (FPGA). Keywords: Control, LNS, floating points. Keywords: Control, FPGA, LNS, floating points. Keywords: Control, FPGA, LNS, floating points. 1. INTRODUCTION 1. INTRODUCTION overall advantage of LNS is fast and simple multiplication 1. INTRODUCTION The first first proposal proposal of of1.Logarithmic Logarithmic Number System System (LNS) (LNS) are are The The overall advantage of LNS is fast and simple multiplication INTRODUCTION The Number and division. The multiplication andand division shown in (1) The overall advantage of LNS is fast simpleis multiplication datedfirst up to to 1971, where where they were were Number introduced to digital digital signal division. The multiplication andand division shown in (1) The proposal of Logarithmic System (LNS) are and dated up 1971, they introduced to signal The overall advantage of LNS is fast simpleis multiplication and (2) (Naziri and Ismail) The first proposal of Logarithmic Number System (LNS) are and division. The multiplication and division is shown in (1) (2) (Naziri and Ismail) processing Rayner). Another approach dated up to (Kingsbury 1971, whereand they were introduced to digital signal and processing (Kingsbury and Rayner). Another similar similar approach and division. The multiplication and division is shown in (1) dated up to 1971, where they were introduced to digital signal and (2) (Naziri and Ismail) was shown in 1975, where using complement format for LNS processing and using Rayner). Another similar was shown (Kingsbury in 1975, where complement formatapproach for LNS and (2) (Naziri log(𝑎𝑎 = (1) and∗∗ 𝑏𝑏) Ismail) log(𝑎𝑎 𝑏𝑏) = log(𝑎𝑎) log(𝑎𝑎) + + log log((𝑏𝑏) 𝑏𝑏) (1) processing and Rayner). Another(Swartlander similar approach were used to avoid negative and wereshown used (Kingsbury to 1975, avoidwhere negative logarithms (Swartlander and was in usinglogarithms complement format for LNS log(𝑎𝑎 ∗ 𝑏𝑏) = log(𝑎𝑎) + log ( 𝑏𝑏) (1) was shown in 1975, where using complement format for LNS Alexopoulus). log(𝑎𝑎/𝑏𝑏) ==log(𝑎𝑎) log(𝑎𝑎) −+log log 𝑏𝑏) (2) log(𝑎𝑎 ∗ 𝑏𝑏)= log(𝑎𝑎)− log (𝑏𝑏) (1) Alexopoulus). log(𝑎𝑎/𝑏𝑏) ((𝑏𝑏) (2) were used to avoid negative logarithms (Swartlander and were used to avoid negative logarithms (Swartlander and Alexopoulus). log(𝑎𝑎/𝑏𝑏) = log(𝑎𝑎) − log ( 𝑏𝑏) Since that, some authors have started calling them signed LNS addition addition and subtraction subtraction (Ismail et𝑏𝑏)al)requires al)requires much much (2) more Alexopoulus). log(𝑎𝑎/𝑏𝑏) = log(𝑎𝑎) − log(et (2) and (Ismail more Since that, some authors have started calling them signed LNS logarithmic number system (SLNS). The philosophy behind it complex DSP operations, as it requires approximation of nonDSP and operations, as it(Ismail requires of more nonSince that, number some authors started thembehind signed logarithmic system have (SLNS). The calling philosophy it complex LNS addition subtraction et approximation al)requires much Since that, somesign authors have started calling themnegative signed LNS addition and subtraction (Ismail et al)requires much more is use of another bit. One sign bit represent actual linear function (Kostopoulos, Marino, Taylor), or as it is is function (Kostopoulos, Marino,approximation Taylor), or as it logarithmic number philosophy it linear is use of another signsystem bit. One(SLNS). sign bitThe represent actual behind negative DSP operations, as it requires of nonlogarithmic number system (SLNS). The philosophy behind it complex complex DSP operations, as it requires approximation of nonor positive value of number and other represent sign of commonly used, requires a fair amount of Look-Up Tables used,(Kostopoulos, requires a fairMarino, amount Taylor), of Look-Up is use of another signofbit. One sign bit other represent actual negative or positive value number and represent sign of commonly linear function or asTables it is is use of another signofbit. One sign bit other represent actual negative linear function (Kostopoulos,increase Marino, their Taylor), as itare is exponent. (LUT), which exponentially increase their size. orThere There are or positive value number and represent sign of (LUT), exponent. which exponentially size. commonly used, requires a fair amount of Look-Up Tables or positive value of number and other represent sign of commonly used, requires a fair amount of Look-Up Tables different ways to toexponentially reduce LUT LUT size. size. exponent. different ways reduce (LUT), which increase their size. There are In exponent. which exponentially increase their size. There are In 1990 1990 Arnold Arnold have have proposed proposed architecture architecture for for LNS LNS based based (LUT), different ways to reduce LUT size. processor, but the design was not complete and was limiting All three number systems (FLP, LNS FP) FP) were were implemented implemented different to reduce size. processor, but thehave design was notarchitecture complete and three ways number systemsLUT (FLP, LNS In 1990 Arnold proposed forwas LNSlimiting based All In 1990 Arnold have proposed architecture for LNS based (Arnold). In 1999 The Gravity Pipe Supercomputer (GRAPE), on experimental embedded device consisting of DC motor and and (Arnold). Inbut 1999 Gravity Supercomputer (GRAPE), Allexperimental three numberembedded systems (FLP, FP) were implemented deviceLNS consisting of DC motor processor, theThe design was Pipe not complete and was limiting on processor, but the design was not (Chugh complete and was limiting All three number systems (FLP, LNS FP) were implemented which won the Gordon Bell Prize and Parhani). RPM controller implemented on FPGA Nexys 4 board. controller implemented on FPGA Nexys board. (Arnold). 1999 The Gravity Pipe(Chugh Supercomputer (GRAPE), RPM which wonIn Gordon Bell Prize and Parhani). experimental embedded device consisting of4DC motor and (Arnold). Inthe 1999 The Gravity Pipe Supercomputer (GRAPE), on on experimental embedded device consisting of DC motor and which won the Gordon Bell Prize (Chugh and Parhani). RPM controller implemented on FPGA Nexys 4 board. Today LNStheare usedBell in speech recognising and DNA The most common approach is isonshown shown inNexys (3) 4 board. which Gordon (Chugh and Parhani). RPMmost controller implemented FPGAin common approach (3) Today won LNS are used in Prize speech recognising and DNA The sequencing. LNS are not standardized up to this day. Today LNS are are used in speech recognising and DNA The log(𝑎𝑎 sequencing. not standardized up to this day. most common is shown in (3) ± 𝑏𝑏) 𝑏𝑏) = =approach 𝑙𝑙𝑙𝑙 + + log(1 log(1 ± 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 − 𝑙𝑙𝑙𝑙))(3) 𝑙𝑙𝑙𝑙))(3) Today LNSLNS are used in speech recognising and DNA The log(𝑎𝑎 most common approach is shown in (3) ± 𝑙𝑙𝑙𝑙 ± − sequencing. LNS are not standardized up to this day. One can thenLNS represent LNS as it is shown inthis the day. fig. 1. Integer sequencing. are not standardized up to One can then represent LNS as it is shown in the fig. 1. Integer log(𝑎𝑎 ± 𝑏𝑏) = 𝑙𝑙𝑙𝑙 + log(1 ± 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 − 𝑙𝑙𝑙𝑙))(3) part is signed number, if sign required. log(𝑎𝑎 ± 𝑏𝑏) = 𝑙𝑙𝑙𝑙 + log(1 ± 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 − 𝑙𝑙𝑙𝑙))(3) One can represent as itanother is shown inbit theis 1. Integer where part E E is then signed number,LNS if not, not, another sign bit isfig. required. la and and lb lb are are numbers numbers already already represented represented by by LNS. LNS. One can then represent LNS as itanother is shown inbit theisfig. 1. Integer where la part E is signed number, if not, sign required. Fixed-point Logarithmic where la and lb are numbers already represented by LNS. part E is signed number, if value not, another sign bit is required. Fixed-point Logarithmic value where la and lb are numbers already represented by LNS. 2. NUMBER NUMBER SYSTEMS SYSTEMS Fixed-point Logarithmic value 2. Sign bit Integer /Exponent: e-bits Fractional: t-bits Fixed-point Logarithmic value e-bits Sign bit Integer /Exponent: Fractional: t-bits 2. NUMBER SYSTEMS This section section is is focused focused about LNS LNS presentation and and compare compare it it Sign bit Integer /Exponent: e-bits Fractional: t-bits 2. NUMBER SYSTEMS This about presentation S E f Sign bit Integer /Exponent: e-bits t-bits S E fFractional: with section floatingispoint point (FLP) andLNS fixedpresentation point (FP). (FP). and compare it This focused about with floating (FLP) and fixed point This focused about S E f with section floatingispoint (FLP) andLNS fixedpresentation point (FP). and compare it S E f with floating point (FLP) and fixed point (FP). 2.1 Logarithmic Logarithmic Number Number System System properties properties 2.1 Floating- point point value value Floating2.1 Logarithmic Number System properties The Logarithmic LNS representation representation was shown in the the fig. fig. 1. 1. LNS LNS can can be be 2.1 Numberwas System properties Floating- point value The LNS shown in Sign bit bit point Integer /Exponent: e-bits e-bits Mantisa: t-bits t-bits Floatingvalue/Exponent: Sign Integer Mantisa: also represented as (4) also represented as (4) was shown in the fig. 1. LNS can be The LNS representation Sign bit Integer /Exponent: e-bits Mantisa: t-bits The representation also LNS represented as (4) was shown in the fig. 1. LNS can be S E m Sign bit Integer /Exponent: e-bits Mantisa: t-bits S E m also𝐿𝐿𝐿𝐿𝐿𝐿 represented as (4) = −1𝑆𝑆𝑆𝑆𝑆𝑆 ∗ 2𝐸𝐸+𝑓𝑓 𝐸𝐸+𝑓𝑓 (4) 𝐿𝐿𝐿𝐿𝐿𝐿 = −1 ∗ 2𝐸𝐸+𝑓𝑓 (4) S 1. LNS and E FLP representation in hardware m Fig. S 1. LNS and E FLP representation in hardware m 𝐿𝐿𝐿𝐿𝐿𝐿 = −1𝑆𝑆𝑆𝑆 ∗ 2𝐸𝐸+𝑓𝑓 Fig. 𝐸𝐸+𝑓𝑓 (4) 𝐿𝐿𝐿𝐿𝐿𝐿 = −1 ∗ 2 (4) Fig. 1. LNS and FLP representation in hardware 2405-8963 © 2019, (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. Fig. 1. LNS and IFAC FLP representation in hardware Peer review under responsibility of International Federation of Automatic Control. 10.1016/j.ifacol.2019.12.713
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which is similar to FLP (5). The (4) can be represented as (6) In practice, NaN and infinity must be defined, similarly to FLP.
coefficient, which has no less than P digits in base B - 0 to 𝐵𝐵𝑃𝑃−1 and Q of exponent from range 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 ≤ 𝑄𝑄 + 𝑃𝑃 ≤ 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 . Therefore:
𝐿𝐿𝐿𝐿𝐿𝐿 = (−1)𝑆𝑆 ∗ 2𝐸𝐸 ∗ 2𝑓𝑓 (5)
(−1)𝑆𝑆 𝑥𝑥𝐶𝐶𝑥𝑥𝐵𝐵𝑄𝑄 (13)
𝐹𝐹𝐹𝐹𝐹𝐹 = (−1)𝑆𝑆 ∗ 2𝐸𝐸 ∗ (1 + 𝑚𝑚)(6)
LNS have relative error, that can be proved by:
𝑏𝑏 −𝑡𝑡−1 𝑚𝑚´ − 𝑚𝑚 ≤ (7) 𝑚𝑚 𝑚𝑚
Where t-bit mantise m is relative error FLP, 𝑚𝑚´ is approximation of m and b is arbitary base. Range of relative error is then: 𝑏𝑏 −𝑡𝑡−1 𝑏𝑏 −𝑡𝑡−1 𝑏𝑏 −𝑡𝑡−1 ≤ ≤ (8) 2 𝑚𝑚 1 Maximum relative error for base 2 of FLP system is then: 2−𝑡𝑡−1 (9) Absolute error for LNS with fraction of wide t-bits is: 𝐴𝐴𝑒𝑒 = 𝑘𝑘´ − 𝑘𝑘 = 2−𝑡𝑡−1 (10)
2.
± infinity
3.
two types of NaNs, qNaN and sNaN
FLP norm includes additional information as how to round, type of rounding, addition subtraction, multiplication and division. FLP has absolute error and dynamic range. 2.3 Fixed point Unlike FLP, fixed point (FP) have no worldwide standard. Although some software languages have libraries, that includes fixed point logic, these libraries use different methods and may not be used in cross-platforms. FP main features are (Finnerty and Ratinger): 1.
Static range
2.
Static precision
3.
Lesser delays
4.
Competitive performance
5.
Adjustability
6.
When used on FPGA :
Equivalent of absolute linear error is: 𝐴𝐴𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 = 2𝑘𝑘´ − 2𝑘𝑘 (11) And relative error of LNS is: 𝑘𝑘´
𝑅𝑅𝑒𝑒 =
𝑘𝑘
2 −2 −𝑡𝑡−1 = 22 − 1 = 2−𝑡𝑡−1,529 (12) 𝑘𝑘 2
Therefore the range of LNS depends on integer part of exponent and precision is defined by the fraction (Barry and Lee).
a.
Less material used
b.
Lesser power consumption
c.
Better bills of materials 3. EXPERIMENT DESIGN
The principle scheme of our experiment workstation is in the fig. 2. FPGA will be used for signal processing and motor control. DAC
Scope/ Matlab
FPGA DAC driver
H-Bridge
PWM
Motor
2.2 Floating Point The FLP is standardized by the norm IEEE 754.
Refrerence
Controller
Format of floating point is defined: Decoder
Rotary encoder
1.
base B, which is called radix, it can be represented by 2 or 10
2.
precision P
Fig. 2. Experiment control structure
3.
range of exponent 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 a 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 , where 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 = 1 - 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚
The first part of experiment is to design and co-simulate our proposed architecture. In our proposed model, more than 32 bits are used and we the device capable of measuring and displaying such precision was not available to us. The reference, real (takes value from decoder and compute it to
The format include: 1.
finite numbers, described by three integers, S – sign bit, it can take value 0 or 1. C – significant or
Motor system
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RPM), decoder, PWM and DAC blocks are part of VHDL design. The controller block will be important to Vivado to confirm our design behaving as intended. All used components are Nexys41 , motor 2 , HB53 and DAC 4 . The PMOD, HB5 is H-bridge, which converts 3.3 V PWM output signal from the board up to 12 V (12 V DC motor is used). The motor has gearbox with 1:19 ratio and 2 channel IRC encoder with 3 impulses per revolution. To compare the difference in principles of LNS and FLP/FP number systems see fig. 3 and fig. 4. uses LNS_DSP method, it consist of 2 subblocks. The first that is transforming binary input into LNS and the next one is subtraction, which is combined with transformation out of LNS. The design already consider: 1.
transform number signal to LNS representation
2.
multiplication (addition in LNS representation)
3.
division (subtraction in LNS representation)
4.
addition
5.
subtraction
6.
additional sign bit
7.
transforming LNS to FLP/FP number representation
4. CONTROLLER DESIGN AND IMPLEMENTATION This section will describe briefly controller design for DC motor and the development software used for implementation. 4.1 Motor identification The considered controlled system is a DC motor. The motor does not exhibit linear behaviour on its entire voltage input range, but it can be approximated as linear system for smaller input voltage ranges around the suitably chosen working point. The best way is to use experimental identification based on measured step response in the chosen setpoint – 400 RPM.
GR (z) = k p (1 +
Tv z TI z−1
+
TD z−1 TV z
)
(14)
Transfer function of the motor for chosen setpoints is: GS (z) =
154.4 (15) 1 + 0.638
We consider that the continuous transfer function (15) was transformed to discrete region by the sampling period Ts = 0.001s. And calculated 2 parameters: q0 is 0.0132 and q1 is 0.0130. 4.2 System Generator and Vivado
Fig. 3. LNS controller design
Fig. 4. Standard controller design All blocks between yellow “In” and “Out” blocks will be compiled and flashed into FPGA, the independent FPGA board. Standard Matlab blocks, scope, display, transfer function and many others are independent and will not hinder FPGA performance. 1
Nexys 4TM FPGA Board reference manual https://reference.digilentinc.com/_media/nexys:nexys4:nexys4_rm.pdf?_ga=2.73632081.272923646.1 551431486-661679554.1551107050 2 Datasheet of DC Motor/Gearbox https://reference.digilentinc.com/_media/motor_gearbox/290006_ig220019x00015r_ds.pdf?_ga=2.235971010.272923646.1551431486-661679554.1551107050 3 Pmod HB5 Reference manual https://reference.digilentinc.com/reference/pmod/pmodhb5/referencemanual?_ga=2.240232768.272923646.1551431486-661679554.1551107050 4 Pmod DA2 Reference manual https://reference.digilentinc.com/reference/pmod/pmodda2/referencemanual?_ga=2.135851250.272923646.1551431486-661679554.1551107050
System Generator is a MatLab Simulink add-on, which helps the design tool, tests and implements high performance DSP algorithms on the Xilinx devices. By dragging predefined blocks and wiring them altogether, one can create, check, simulate, or even co-simulate design (the difference between simulation and co-simulation is that the co-simulation is running on the Xilinx devices and not in MatLab). After verification of the design results, the user can create IP (Intellectual property) core, which can be included in Vivado. Vivado is developer software created by Xilinx, for synthesising and analysing HDL design. The design can be simulated, tested. Timing analysis can be done up to delays of gates or wired routes. The Vivado provides not only test benches and timing analysis, but also resource analysis. Resource analysis provides an overview of your design hardware area usage. 4.3 Simulations and Co-simulations For demonstration, an 1 ms sample period was chosen. The result of simulations are shown in the fig. 5. Simulations shows, that LNS produce very similar, nearly identical results. Co-simulations is feature of System Generator – Matlab addon which provides a set of blocks, which can be flashed through JTAG into FPGA making the design run by the FPGA and not Matlab. Matlab role is to coordinate input and outputs of FPGA and if needed displaying them through scope or other similar tools.
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For implementation of designed controller 3 types of number system implementations were used (FLP, LNS and FP base controller). The first is realized using the fixed point and is focused on area resource effectivity, the second is realized as floating point, which focus on precision, the last is LNS number system representation, that offers kind of compromise between precision and area resources.
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While LNS_BRAM results are similar to results of FIX_P, from the fig. 5. we can assume, that precision was slightly better on LNS_BRAM. The FLP and LNS_DSP, the results in precisions are less significant. By analysing the fig. 7. further, they both have very similar precisions. The zoomed and filtered part of fig. 7, is shown in the fig. 9.
The first and initial design is focused on precision . It does use “brute DSP” power to calculate the logarithm in real time, meaning calculating logarithm as infinite series up until 32 bit precision is not hindered (Tropea). While this offer very good precision, it requires a decent amount of processing power, however nothing the FPGA or any DSP could handle (Marked as LNS_DSP). The other uses a BRAM (block RAM), where predefined values are saved to lower necessary DSP intervention. The results of these two are in the fig. 6 (Marked as LNS_BRAM).
Fig. 7. Difference between: Matlab_model - other_models
Fig. 5. LNS controller and Matlab model controller BRAM is dedicated memory containing certain amount of RAM. Unlike distributed RAM, which is made out of LUTs, therefore using a larger amount of data to be stored is better to use BRAM than LUTs. BRAM provides 8, 16, 32 data width, and can be used as ROM or dual RAM. BRAM is also being used when storing program for microblaze or part of FIFO (first in first out) between two clock domains. Because our design takes a lot of LUTs relocating some data into BRAM is good choice, as the resource used by our board will be more distributed. Type LNS_DSP LNS_BRAM
BRAMs(135) DSPs(24) LUTs(63400) Registers(126800) 0 28 12248 64 2 0 651 986
Fig. 6. Two LNS implementations BRAM and DSP. In the second implementation, where no DSP is being used, however, the precision suffers, as the inputs of BRAM is integer value, therefore the rounding is being done. The precision is then improved by simple interpolation. Interpolation consists only of adding and shifting, which are basic DSP operations. The comparison of precision is in the fig. 7 and the overall, all 4 controllers are shown in the fig.8. If not zoomed, the difference is not visible as they are overlapping each other making it seem as there are only two controllers.
Fig. 8. Results of all controllers simulations and cosimulations. The area resource can be reduced by knowing, that same type of binary representation will be used for different numbers. E.g. log2(33) and log2(66) will have same fraction part, meaning one number can be represented as 5.044 and the other 6.044. The only difference in such representation is the integer part, which represents exponent value. The fraction value does not change. This can result in using only half of the initial value, when using ROM, RAM or LUTs. One can even further reduce amount of ROM used by using interpolation. Suppose we have number 60, which is not saved in the RAM. The two nearest numbers are 59 and 61. In LNS, Integer part will be same and only fraction F will differ. By taking the two nearest fraction and then shifting its value once we can get the required fraction, (F59 + F61)/2 = F60. This results in another halving of needed ROM. Resources used for FP (24 bits) were 2 DSPs, 1751 LUTs and 32 Registers. For FLP (single precision) were 4 DSPs, 4820 LUTs and 64 Registers.
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automation is our intention to achieve. For state zero, LNS value would not be finite, therefore, this has to be considered in the design. In our solution we implemented additional bit, which signal us, that on the input to our conversion block is currently being zero value. In case of zero value BRAM, or logarithm block is then not being used and this zero value is signalized in addition blocks (which actually are multiplying) and in the subtraction block. This will signalise to finish the last cycle as there was no subtraction (because q1 is delayed and for stability issues, this needs to be done). After one cycle, if there is still zero value at the input, the controller will keep its last value, until the change on the input will occur. 4. MOTOR CONTROL Fig. 9. Zoomed precision error of LNS_DSP and FLP Another way how to implement LNS is to combine these two (BRAM and DSP) methods. It is combination of DSP and BRAM method. BRAM provides less precise results because before conversion a rounding is needed. While the DSP method require heavy computation compared to the BRAM. The input of the controller will be wired directly into the BRAM, which output will be immediately LNS without using a DSP function or loosing precision. On the output there won’t be another BRAM where a rounding would occur, but rather precise DSP operation will take place making the system precise.
The speed decoder block estimates the actual motor speed. The DC motor considered in this project has a gear ratio 1:19 and has rotary encoder with 3 pulses per revolution. Quadrature decoder was used in our implementation. For evaluation of actual motor speed and control output we are using digital to analog converter. Analog output of converter is connected to the scope and then evaluated in MATLAB environment. Communication with DA converter ensures DAC design block. PWM transforms a 12-bit (duty) signal into a 1-bit signal, period is set to 800, but binary. LNS were used only in controller design not in signal processing of speed. The whole running workspace is in the fig. 13.
Fig. 10. Controller design for hybrid implementation
The results of live system are not shown, because only 12 bit DAC is present. With 12 bit accuracy all controllers behave identically and better precision would be required to see the difference between them. In the fig. 10. an LNS_DSP controller is being used to run the motor.
Fig. 11. Comparison of hybrid LNS and FLP Type BRAMs(135) DSPs(24) LUTs(63400) Registers(126800) LNS_Hybrid 1 14 8820 464 FLP 0 4 4820 64 FP 0 2 1751 32
Fig. 12. Resource analysis of hybrid LNS, FLP and FP. In the LNS a zero value is problematic course of action. As when zero value is at the input of our system, which in
Fig. 13. Workstation with implemented LNS controller
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5. CONCLUSIONS
REFERENCES
In this paper we have implemented a 5 PI controllers, where fixed point and floating point based were to act as reference to our LNS design. LNS are not used in many real-time applications, have no standard, and most of the authors implement them for specific situations or with too strict restrictions.
N. G. Kingsbury and P. J. W. Rayner, "Digital filtering using logarithmic arithmetic," in Electronics Letters, vol. 7, no. 2, pp. 56-58, 28 January 1971. doi: 10.1049/el:19710039. E. E. Swartzlander and A. G. Alexopoulos, "The Sign/Logarithm Number System," in IEEE Transactions on Computers, vol. C-24, no. 12, pp. 1238-1242, Dec. 1975. doi: 10.1109/T-C.1975.224172 M. G. Arnold, "A VLIW architecture for logarithmic arithmetic," Euromicro Symposium on Digital System Design, 2003. Proceedings., Belek-Antalya, Turkey, 2003, pp. 294-302. doi: 10.1109/DSD.2003.1231957 M. Chugh and B. Parhami, "Logarithmic arithmetic as an alternative to floating-point: A review," 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2013, pp. 1139-1143. doi: 10.1109/ACSSC.2013.6810472 D. K. Kostopoulos, "An algorithm for the computation of binary logarithms," in IEEE Transactions on Computers, vol. 40, no. 11, pp. 1267-1270, Nov. 1991. doi: 10.1109/12.102831 D. Marino, "New Algorithms for the Approximate Evaluation in Hardware of Binary Logarithms and Elementary Functions," in IEEE Transactions on Computers, vol. C21, no. 12, pp. 1416-1421, Dec. 1972. doi: 10.1109/TC.1972.223516 F. Taylor, "An extended precision logarithmic number system," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 31, no. 1, pp. 232-234, February 1983. doi: 10.1109/TASSP.1983.1164042 M. Chugh and B. Parhami, "Logarithmic arithmetic as an alternative to floating-point: A review," 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2013, pp. 1139-1143. doi: 10.1109/ACSSC.2013.6810472 Barry, R., Lee., A comparison of logarithmic and floating point number systems implemented on Xilinx Virtex-II field programmable arrays. ProQuest, Cardiff, University of Wales, 2004. UMI: U584674. Finnerty, A., and Ratigner, H., Reduce Power and Cost by Converting from Floating Point to Fixed Point, [online], [cited 10.1.2019], available at: https://www.xilinx.com/support/documentation/white_pa pers/wp491-floating-to-fixed-point.pdf S. Z. M. Naziri, R. C. Ismail and A. Y. M. Shakaff, "The design revolution of logarithmic number system architecture," 2014 2nd International Conference on Electrical, Electronics and System Engineering (ICEESE), Kuala Lumpur, 2014, pp. 5-10. doi: 10.1109/ICEESE.2014.7154603 R.C. Ismail, S.A.Z. Murad, R. Hussin, J.N. Coleman, Improved Subtraction Function for Logarithmic Number System, Procedia Engineering, Volume 53, 2013, Pages 387-392, ISSN 1877-7058, S. E. Tropea, "FPGA Implementation of Base-N Logarithm," 2007 3rd Southern Conference on Programmable Logic, Mar del Plata, 2007, pp. 27-32. doi: 10.1109/SPL.2007.371719
We chose to implement them for the first time in automation control, to show their possible value. The implementation was done on simple PI controller and the first order motor. The simplicity of solution provided a challenge to implement a real-time addition and subtraction of LNS, overcome the 0 problematic, define our own standard, which can be used in the future – make our solution repeatable and adaptable to other type of controllers, for example more advanced LQPI state space controller. Transformation to and back from LNS took some precision and area resources, depending on the type of implementation. These transformations could be avoided if the whole system (e.g. sensor, PWM etc.) were LNS. This possibility can be purpose of another study, as implementing whole system, not just controller could bring interesting solutions. Precision can be considered as the same of the floating point, while the adjustability of floating point is much lesser compared to LNS, the area resource used by the floating points were lesser. One of the reason is too few multiplications in simple PI controller. When using BRAM, the area resources were lowered by significant amount, while the performance was similar to the 24 bit fixed point solution. Not all solution requires a high precision implementation. While when a higher precision is needed, LNS can provided that as well, but the resources used are higher. The precision is then competitive to floating points and in certain situations it is even higher than floating point. Area of resources were shown for all solutions. The best overall outcome was given by the hybrid solution, where used resources were reduced even by 50% while not loosing precision. Overall 50% reduction on DSP, around 30% reduction on LUTS, but the registers were raised by 725%. However the FPGA usage in more distributed, which can be considered good, because if the solution heavily weight only one type of resource, when a more complex design tries to by implemented, one can meet a technology hardware limitations. The experiment shown a way how to handle exception, that LNS bring with themselves and show an effective ways to adjust LNS designs to our desired solution and even on quick changing and dynamic system as the controller itself is. ACKNOWLEDGEMENT The paper was partially supported by the Slovak Research and Development Agency, grant No. APVV-17-0190 and the Slovak Cultural Educational Grant Agency, grant No. 038STU-4/2018.
ScienceDirect IFAC PapersOnLine 52-27 (2019) 502–507
Implementation Implementation of of Logarithmic Logarithmic Number Number Systems Systems in in control control application application using using Implementation of Logarithmic Number Systems in control application FPGA FPGASystems in control application using Implementation of Logarithmic Number using FPGA FPGA
Ivan Klimo, Michal Kocúr, Peter Drahoš Ivan Klimo, Michal Kocúr, Peter Drahoš Ivan Klimo, Michal Kocúr, Peter Drahoš Ivan Klimo, Michal Kocúr, Peter Drahoš Institute Mechatronics, Institute of of Automotive Automotive Mechatronics, Faculty of Electrical Engineering and Information Institute Engineering of Automotive Mechatronics, Faculty of Electrical and Information Technology, Technology, Institute of Automotive Mechatronics, Slovak University of Technology in Bratislava, Slovakia Slovak UniversityEngineering of Technology Bratislava, Technology, Slovakia Faculty of Electrical andinInformation Faculty of Electrical Engineering and Information Technology, (e-mail: [email protected]) (e-mail: [email protected]) Slovak University of Technology in Bratislava, Slovakia (e-mail: [email protected]) Slovak University of Technology in Bratislava, Slovakia (e-mail: [email protected]) (e-mail: [email protected]) Abstract: Abstract: This This paper paper deals deals with with aa different different approach approach to to hardware hardware implementation implementation of of PI PI controller. controller. Logarithmic Number (LNS) are number instead of of classic, classic, floating point Abstract: This paper Systems deals with a different approach hardware implementation of PI controller. Logarithmic Number Systems (LNS) are used used for for numbertorepresentation representation instead floating point Abstract: This paper deals with a different approach to hardware implementation of PI controller. (FLP) or fixed point (FP) representation. The comparison and pros and cons of these representation are Logarithmic Number Systems (LNS) are used number representation instead classic, floating point (FLP) or fixed point (FP) representation. The for comparison and pros and cons of of these representation are Logarithmic Number Systems (LNS) are used for number representation instead of classic, floating point presented.The results shows, that using LNS can be another way to implement controllers. The presented.The shows, that usingThe LNS can be another to implement controllers. The (FLP) or fixed results point (FP) representation. comparison and prosway and cons of these representation are (FLP) or fixed point representation. The comparison and pros and cons of these representation are implementation were (FP) realized onthat Field Programmable Gate arrays (FPGA). presented.The results shows,on using LNS can Gate be another way to implement controllers. The implementation were realized Field Programmable arrays (FPGA). presented.The results shows, that using LNS can be another way to implement controllers. The implementation wereFPGA, realized on Field Programmable Gate arrays (FPGA). © 2019, IFAC (International Federation of Automatic Hosting by Elsevier Ltd. All rights reserved. Keywords: Control, LNS, floating points. Control) implementation wereFPGA, realized on Field Programmable Gate arrays (FPGA). Keywords: Control, LNS, floating points. Keywords: Control, FPGA, LNS, floating points. Keywords: Control, FPGA, LNS, floating points. 1. INTRODUCTION 1. INTRODUCTION overall advantage of LNS is fast and simple multiplication 1. INTRODUCTION The first first proposal proposal of of1.Logarithmic Logarithmic Number System System (LNS) (LNS) are are The The overall advantage of LNS is fast and simple multiplication INTRODUCTION The Number and division. The multiplication andand division shown in (1) The overall advantage of LNS is fast simpleis multiplication datedfirst up to to 1971, where where they were were Number introduced to digital digital signal division. The multiplication andand division shown in (1) The proposal of Logarithmic System (LNS) are and dated up 1971, they introduced to signal The overall advantage of LNS is fast simpleis multiplication and (2) (Naziri and Ismail) The first proposal of Logarithmic Number System (LNS) are and division. The multiplication and division is shown in (1) (2) (Naziri and Ismail) processing Rayner). Another approach dated up to (Kingsbury 1971, whereand they were introduced to digital signal and processing (Kingsbury and Rayner). Another similar similar approach and division. The multiplication and division is shown in (1) dated up to 1971, where they were introduced to digital signal and (2) (Naziri and Ismail) was shown in 1975, where using complement format for LNS processing and using Rayner). Another similar was shown (Kingsbury in 1975, where complement formatapproach for LNS and (2) (Naziri log(𝑎𝑎 = (1) and∗∗ 𝑏𝑏) Ismail) log(𝑎𝑎 𝑏𝑏) = log(𝑎𝑎) log(𝑎𝑎) + + log log((𝑏𝑏) 𝑏𝑏) (1) processing and Rayner). Another(Swartlander similar approach were used to avoid negative and wereshown used (Kingsbury to 1975, avoidwhere negative logarithms (Swartlander and was in usinglogarithms complement format for LNS log(𝑎𝑎 ∗ 𝑏𝑏) = log(𝑎𝑎) + log ( 𝑏𝑏) (1) was shown in 1975, where using complement format for LNS Alexopoulus). log(𝑎𝑎/𝑏𝑏) ==log(𝑎𝑎) log(𝑎𝑎) −+log log 𝑏𝑏) (2) log(𝑎𝑎 ∗ 𝑏𝑏)= log(𝑎𝑎)− log (𝑏𝑏) (1) Alexopoulus). log(𝑎𝑎/𝑏𝑏) ((𝑏𝑏) (2) were used to avoid negative logarithms (Swartlander and were used to avoid negative logarithms (Swartlander and Alexopoulus). log(𝑎𝑎/𝑏𝑏) = log(𝑎𝑎) − log ( 𝑏𝑏) Since that, some authors have started calling them signed LNS addition addition and subtraction subtraction (Ismail et𝑏𝑏)al)requires al)requires much much (2) more Alexopoulus). log(𝑎𝑎/𝑏𝑏) = log(𝑎𝑎) − log(et (2) and (Ismail more Since that, some authors have started calling them signed LNS logarithmic number system (SLNS). The philosophy behind it complex DSP operations, as it requires approximation of nonDSP and operations, as it(Ismail requires of more nonSince that, number some authors started thembehind signed logarithmic system have (SLNS). The calling philosophy it complex LNS addition subtraction et approximation al)requires much Since that, somesign authors have started calling themnegative signed LNS addition and subtraction (Ismail et al)requires much more is use of another bit. One sign bit represent actual linear function (Kostopoulos, Marino, Taylor), or as it is is function (Kostopoulos, Marino,approximation Taylor), or as it logarithmic number philosophy it linear is use of another signsystem bit. One(SLNS). sign bitThe represent actual behind negative DSP operations, as it requires of nonlogarithmic number system (SLNS). The philosophy behind it complex complex DSP operations, as it requires approximation of nonor positive value of number and other represent sign of commonly used, requires a fair amount of Look-Up Tables used,(Kostopoulos, requires a fairMarino, amount Taylor), of Look-Up is use of another signofbit. One sign bit other represent actual negative or positive value number and represent sign of commonly linear function or asTables it is is use of another signofbit. One sign bit other represent actual negative linear function (Kostopoulos,increase Marino, their Taylor), as itare is exponent. (LUT), which exponentially increase their size. orThere There are or positive value number and represent sign of (LUT), exponent. which exponentially size. commonly used, requires a fair amount of Look-Up Tables or positive value of number and other represent sign of commonly used, requires a fair amount of Look-Up Tables different ways to toexponentially reduce LUT LUT size. size. exponent. different ways reduce (LUT), which increase their size. There are In exponent. which exponentially increase their size. There are In 1990 1990 Arnold Arnold have have proposed proposed architecture architecture for for LNS LNS based based (LUT), different ways to reduce LUT size. processor, but the design was not complete and was limiting All three number systems (FLP, LNS FP) FP) were were implemented implemented different to reduce size. processor, but thehave design was notarchitecture complete and three ways number systemsLUT (FLP, LNS In 1990 Arnold proposed forwas LNSlimiting based All In 1990 Arnold have proposed architecture for LNS based (Arnold). In 1999 The Gravity Pipe Supercomputer (GRAPE), on experimental embedded device consisting of DC motor and and (Arnold). Inbut 1999 Gravity Supercomputer (GRAPE), Allexperimental three numberembedded systems (FLP, FP) were implemented deviceLNS consisting of DC motor processor, theThe design was Pipe not complete and was limiting on processor, but the design was not (Chugh complete and was limiting All three number systems (FLP, LNS FP) were implemented which won the Gordon Bell Prize and Parhani). RPM controller implemented on FPGA Nexys 4 board. controller implemented on FPGA Nexys board. (Arnold). 1999 The Gravity Pipe(Chugh Supercomputer (GRAPE), RPM which wonIn Gordon Bell Prize and Parhani). experimental embedded device consisting of4DC motor and (Arnold). Inthe 1999 The Gravity Pipe Supercomputer (GRAPE), on on experimental embedded device consisting of DC motor and which won the Gordon Bell Prize (Chugh and Parhani). RPM controller implemented on FPGA Nexys 4 board. Today LNStheare usedBell in speech recognising and DNA The most common approach is isonshown shown inNexys (3) 4 board. which Gordon (Chugh and Parhani). RPMmost controller implemented FPGAin common approach (3) Today won LNS are used in Prize speech recognising and DNA The sequencing. LNS are not standardized up to this day. Today LNS are are used in speech recognising and DNA The log(𝑎𝑎 sequencing. not standardized up to this day. most common is shown in (3) ± 𝑏𝑏) 𝑏𝑏) = =approach 𝑙𝑙𝑙𝑙 + + log(1 log(1 ± 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 − 𝑙𝑙𝑙𝑙))(3) 𝑙𝑙𝑙𝑙))(3) Today LNSLNS are used in speech recognising and DNA The log(𝑎𝑎 most common approach is shown in (3) ± 𝑙𝑙𝑙𝑙 ± − sequencing. LNS are not standardized up to this day. One can thenLNS represent LNS as it is shown inthis the day. fig. 1. Integer sequencing. are not standardized up to One can then represent LNS as it is shown in the fig. 1. Integer log(𝑎𝑎 ± 𝑏𝑏) = 𝑙𝑙𝑙𝑙 + log(1 ± 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 − 𝑙𝑙𝑙𝑙))(3) part is signed number, if sign required. log(𝑎𝑎 ± 𝑏𝑏) = 𝑙𝑙𝑙𝑙 + log(1 ± 𝑒𝑒𝑒𝑒𝑒𝑒(𝑙𝑙𝑙𝑙 − 𝑙𝑙𝑙𝑙))(3) One can represent as itanother is shown inbit theis 1. Integer where part E E is then signed number,LNS if not, not, another sign bit isfig. required. la and and lb lb are are numbers numbers already already represented represented by by LNS. LNS. One can then represent LNS as itanother is shown inbit theisfig. 1. Integer where la part E is signed number, if not, sign required. Fixed-point Logarithmic where la and lb are numbers already represented by LNS. part E is signed number, if value not, another sign bit is required. Fixed-point Logarithmic value where la and lb are numbers already represented by LNS. 2. NUMBER NUMBER SYSTEMS SYSTEMS Fixed-point Logarithmic value 2. Sign bit Integer /Exponent: e-bits Fractional: t-bits Fixed-point Logarithmic value e-bits Sign bit Integer /Exponent: Fractional: t-bits 2. NUMBER SYSTEMS This section section is is focused focused about LNS LNS presentation and and compare compare it it Sign bit Integer /Exponent: e-bits Fractional: t-bits 2. NUMBER SYSTEMS This about presentation S E f Sign bit Integer /Exponent: e-bits t-bits S E fFractional: with section floatingispoint point (FLP) andLNS fixedpresentation point (FP). (FP). and compare it This focused about with floating (FLP) and fixed point This focused about S E f with section floatingispoint (FLP) andLNS fixedpresentation point (FP). and compare it S E f with floating point (FLP) and fixed point (FP). 2.1 Logarithmic Logarithmic Number Number System System properties properties 2.1 Floating- point point value value Floating2.1 Logarithmic Number System properties The Logarithmic LNS representation representation was shown in the the fig. fig. 1. 1. LNS LNS can can be be 2.1 Numberwas System properties Floating- point value The LNS shown in Sign bit bit point Integer /Exponent: e-bits e-bits Mantisa: t-bits t-bits Floatingvalue/Exponent: Sign Integer Mantisa: also represented as (4) also represented as (4) was shown in the fig. 1. LNS can be The LNS representation Sign bit Integer /Exponent: e-bits Mantisa: t-bits The representation also LNS represented as (4) was shown in the fig. 1. LNS can be S E m Sign bit Integer /Exponent: e-bits Mantisa: t-bits S E m also𝐿𝐿𝐿𝐿𝐿𝐿 represented as (4) = −1𝑆𝑆𝑆𝑆𝑆𝑆 ∗ 2𝐸𝐸+𝑓𝑓 𝐸𝐸+𝑓𝑓 (4) 𝐿𝐿𝐿𝐿𝐿𝐿 = −1 ∗ 2𝐸𝐸+𝑓𝑓 (4) S 1. LNS and E FLP representation in hardware m Fig. S 1. LNS and E FLP representation in hardware m 𝐿𝐿𝐿𝐿𝐿𝐿 = −1𝑆𝑆𝑆𝑆 ∗ 2𝐸𝐸+𝑓𝑓 Fig. 𝐸𝐸+𝑓𝑓 (4) 𝐿𝐿𝐿𝐿𝐿𝐿 = −1 ∗ 2 (4) Fig. 1. LNS and FLP representation in hardware 2405-8963 © 2019, (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved. Fig. 1. LNS and IFAC FLP representation in hardware Peer review under responsibility of International Federation of Automatic Control. 10.1016/j.ifacol.2019.12.713
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which is similar to FLP (5). The (4) can be represented as (6) In practice, NaN and infinity must be defined, similarly to FLP.
coefficient, which has no less than P digits in base B - 0 to 𝐵𝐵𝑃𝑃−1 and Q of exponent from range 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 ≤ 𝑄𝑄 + 𝑃𝑃 ≤ 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 . Therefore:
𝐿𝐿𝐿𝐿𝐿𝐿 = (−1)𝑆𝑆 ∗ 2𝐸𝐸 ∗ 2𝑓𝑓 (5)
(−1)𝑆𝑆 𝑥𝑥𝐶𝐶𝑥𝑥𝐵𝐵𝑄𝑄 (13)
𝐹𝐹𝐹𝐹𝐹𝐹 = (−1)𝑆𝑆 ∗ 2𝐸𝐸 ∗ (1 + 𝑚𝑚)(6)
LNS have relative error, that can be proved by:
𝑏𝑏 −𝑡𝑡−1 𝑚𝑚´ − 𝑚𝑚 ≤ (7) 𝑚𝑚 𝑚𝑚
Where t-bit mantise m is relative error FLP, 𝑚𝑚´ is approximation of m and b is arbitary base. Range of relative error is then: 𝑏𝑏 −𝑡𝑡−1 𝑏𝑏 −𝑡𝑡−1 𝑏𝑏 −𝑡𝑡−1 ≤ ≤ (8) 2 𝑚𝑚 1 Maximum relative error for base 2 of FLP system is then: 2−𝑡𝑡−1 (9) Absolute error for LNS with fraction of wide t-bits is: 𝐴𝐴𝑒𝑒 = 𝑘𝑘´ − 𝑘𝑘 = 2−𝑡𝑡−1 (10)
2.
± infinity
3.
two types of NaNs, qNaN and sNaN
FLP norm includes additional information as how to round, type of rounding, addition subtraction, multiplication and division. FLP has absolute error and dynamic range. 2.3 Fixed point Unlike FLP, fixed point (FP) have no worldwide standard. Although some software languages have libraries, that includes fixed point logic, these libraries use different methods and may not be used in cross-platforms. FP main features are (Finnerty and Ratinger): 1.
Static range
2.
Static precision
3.
Lesser delays
4.
Competitive performance
5.
Adjustability
6.
When used on FPGA :
Equivalent of absolute linear error is: 𝐴𝐴𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 = 2𝑘𝑘´ − 2𝑘𝑘 (11) And relative error of LNS is: 𝑘𝑘´
𝑅𝑅𝑒𝑒 =
𝑘𝑘
2 −2 −𝑡𝑡−1 = 22 − 1 = 2−𝑡𝑡−1,529 (12) 𝑘𝑘 2
Therefore the range of LNS depends on integer part of exponent and precision is defined by the fraction (Barry and Lee).
a.
Less material used
b.
Lesser power consumption
c.
Better bills of materials 3. EXPERIMENT DESIGN
The principle scheme of our experiment workstation is in the fig. 2. FPGA will be used for signal processing and motor control. DAC
Scope/ Matlab
FPGA DAC driver
H-Bridge
PWM
Motor
2.2 Floating Point The FLP is standardized by the norm IEEE 754.
Refrerence
Controller
Format of floating point is defined: Decoder
Rotary encoder
1.
base B, which is called radix, it can be represented by 2 or 10
2.
precision P
Fig. 2. Experiment control structure
3.
range of exponent 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 a 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 , where 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚 = 1 - 𝑒𝑒𝑚𝑚𝑚𝑚𝑚𝑚
The first part of experiment is to design and co-simulate our proposed architecture. In our proposed model, more than 32 bits are used and we the device capable of measuring and displaying such precision was not available to us. The reference, real (takes value from decoder and compute it to
The format include: 1.
finite numbers, described by three integers, S – sign bit, it can take value 0 or 1. C – significant or
Motor system
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RPM), decoder, PWM and DAC blocks are part of VHDL design. The controller block will be important to Vivado to confirm our design behaving as intended. All used components are Nexys41 , motor 2 , HB53 and DAC 4 . The PMOD, HB5 is H-bridge, which converts 3.3 V PWM output signal from the board up to 12 V (12 V DC motor is used). The motor has gearbox with 1:19 ratio and 2 channel IRC encoder with 3 impulses per revolution. To compare the difference in principles of LNS and FLP/FP number systems see fig. 3 and fig. 4. uses LNS_DSP method, it consist of 2 subblocks. The first that is transforming binary input into LNS and the next one is subtraction, which is combined with transformation out of LNS. The design already consider: 1.
transform number signal to LNS representation
2.
multiplication (addition in LNS representation)
3.
division (subtraction in LNS representation)
4.
addition
5.
subtraction
6.
additional sign bit
7.
transforming LNS to FLP/FP number representation
4. CONTROLLER DESIGN AND IMPLEMENTATION This section will describe briefly controller design for DC motor and the development software used for implementation. 4.1 Motor identification The considered controlled system is a DC motor. The motor does not exhibit linear behaviour on its entire voltage input range, but it can be approximated as linear system for smaller input voltage ranges around the suitably chosen working point. The best way is to use experimental identification based on measured step response in the chosen setpoint – 400 RPM.
GR (z) = k p (1 +
Tv z TI z−1
+
TD z−1 TV z
)
(14)
Transfer function of the motor for chosen setpoints is: GS (z) =
154.4 (15) 1 + 0.638
We consider that the continuous transfer function (15) was transformed to discrete region by the sampling period Ts = 0.001s. And calculated 2 parameters: q0 is 0.0132 and q1 is 0.0130. 4.2 System Generator and Vivado
Fig. 3. LNS controller design
Fig. 4. Standard controller design All blocks between yellow “In” and “Out” blocks will be compiled and flashed into FPGA, the independent FPGA board. Standard Matlab blocks, scope, display, transfer function and many others are independent and will not hinder FPGA performance. 1
Nexys 4TM FPGA Board reference manual https://reference.digilentinc.com/_media/nexys:nexys4:nexys4_rm.pdf?_ga=2.73632081.272923646.1 551431486-661679554.1551107050 2 Datasheet of DC Motor/Gearbox https://reference.digilentinc.com/_media/motor_gearbox/290006_ig220019x00015r_ds.pdf?_ga=2.235971010.272923646.1551431486-661679554.1551107050 3 Pmod HB5 Reference manual https://reference.digilentinc.com/reference/pmod/pmodhb5/referencemanual?_ga=2.240232768.272923646.1551431486-661679554.1551107050 4 Pmod DA2 Reference manual https://reference.digilentinc.com/reference/pmod/pmodda2/referencemanual?_ga=2.135851250.272923646.1551431486-661679554.1551107050
System Generator is a MatLab Simulink add-on, which helps the design tool, tests and implements high performance DSP algorithms on the Xilinx devices. By dragging predefined blocks and wiring them altogether, one can create, check, simulate, or even co-simulate design (the difference between simulation and co-simulation is that the co-simulation is running on the Xilinx devices and not in MatLab). After verification of the design results, the user can create IP (Intellectual property) core, which can be included in Vivado. Vivado is developer software created by Xilinx, for synthesising and analysing HDL design. The design can be simulated, tested. Timing analysis can be done up to delays of gates or wired routes. The Vivado provides not only test benches and timing analysis, but also resource analysis. Resource analysis provides an overview of your design hardware area usage. 4.3 Simulations and Co-simulations For demonstration, an 1 ms sample period was chosen. The result of simulations are shown in the fig. 5. Simulations shows, that LNS produce very similar, nearly identical results. Co-simulations is feature of System Generator – Matlab addon which provides a set of blocks, which can be flashed through JTAG into FPGA making the design run by the FPGA and not Matlab. Matlab role is to coordinate input and outputs of FPGA and if needed displaying them through scope or other similar tools.
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For implementation of designed controller 3 types of number system implementations were used (FLP, LNS and FP base controller). The first is realized using the fixed point and is focused on area resource effectivity, the second is realized as floating point, which focus on precision, the last is LNS number system representation, that offers kind of compromise between precision and area resources.
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While LNS_BRAM results are similar to results of FIX_P, from the fig. 5. we can assume, that precision was slightly better on LNS_BRAM. The FLP and LNS_DSP, the results in precisions are less significant. By analysing the fig. 7. further, they both have very similar precisions. The zoomed and filtered part of fig. 7, is shown in the fig. 9.
The first and initial design is focused on precision . It does use “brute DSP” power to calculate the logarithm in real time, meaning calculating logarithm as infinite series up until 32 bit precision is not hindered (Tropea). While this offer very good precision, it requires a decent amount of processing power, however nothing the FPGA or any DSP could handle (Marked as LNS_DSP). The other uses a BRAM (block RAM), where predefined values are saved to lower necessary DSP intervention. The results of these two are in the fig. 6 (Marked as LNS_BRAM).
Fig. 7. Difference between: Matlab_model - other_models
Fig. 5. LNS controller and Matlab model controller BRAM is dedicated memory containing certain amount of RAM. Unlike distributed RAM, which is made out of LUTs, therefore using a larger amount of data to be stored is better to use BRAM than LUTs. BRAM provides 8, 16, 32 data width, and can be used as ROM or dual RAM. BRAM is also being used when storing program for microblaze or part of FIFO (first in first out) between two clock domains. Because our design takes a lot of LUTs relocating some data into BRAM is good choice, as the resource used by our board will be more distributed. Type LNS_DSP LNS_BRAM
BRAMs(135) DSPs(24) LUTs(63400) Registers(126800) 0 28 12248 64 2 0 651 986
Fig. 6. Two LNS implementations BRAM and DSP. In the second implementation, where no DSP is being used, however, the precision suffers, as the inputs of BRAM is integer value, therefore the rounding is being done. The precision is then improved by simple interpolation. Interpolation consists only of adding and shifting, which are basic DSP operations. The comparison of precision is in the fig. 7 and the overall, all 4 controllers are shown in the fig.8. If not zoomed, the difference is not visible as they are overlapping each other making it seem as there are only two controllers.
Fig. 8. Results of all controllers simulations and cosimulations. The area resource can be reduced by knowing, that same type of binary representation will be used for different numbers. E.g. log2(33) and log2(66) will have same fraction part, meaning one number can be represented as 5.044 and the other 6.044. The only difference in such representation is the integer part, which represents exponent value. The fraction value does not change. This can result in using only half of the initial value, when using ROM, RAM or LUTs. One can even further reduce amount of ROM used by using interpolation. Suppose we have number 60, which is not saved in the RAM. The two nearest numbers are 59 and 61. In LNS, Integer part will be same and only fraction F will differ. By taking the two nearest fraction and then shifting its value once we can get the required fraction, (F59 + F61)/2 = F60. This results in another halving of needed ROM. Resources used for FP (24 bits) were 2 DSPs, 1751 LUTs and 32 Registers. For FLP (single precision) were 4 DSPs, 4820 LUTs and 64 Registers.
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automation is our intention to achieve. For state zero, LNS value would not be finite, therefore, this has to be considered in the design. In our solution we implemented additional bit, which signal us, that on the input to our conversion block is currently being zero value. In case of zero value BRAM, or logarithm block is then not being used and this zero value is signalized in addition blocks (which actually are multiplying) and in the subtraction block. This will signalise to finish the last cycle as there was no subtraction (because q1 is delayed and for stability issues, this needs to be done). After one cycle, if there is still zero value at the input, the controller will keep its last value, until the change on the input will occur. 4. MOTOR CONTROL Fig. 9. Zoomed precision error of LNS_DSP and FLP Another way how to implement LNS is to combine these two (BRAM and DSP) methods. It is combination of DSP and BRAM method. BRAM provides less precise results because before conversion a rounding is needed. While the DSP method require heavy computation compared to the BRAM. The input of the controller will be wired directly into the BRAM, which output will be immediately LNS without using a DSP function or loosing precision. On the output there won’t be another BRAM where a rounding would occur, but rather precise DSP operation will take place making the system precise.
The speed decoder block estimates the actual motor speed. The DC motor considered in this project has a gear ratio 1:19 and has rotary encoder with 3 pulses per revolution. Quadrature decoder was used in our implementation. For evaluation of actual motor speed and control output we are using digital to analog converter. Analog output of converter is connected to the scope and then evaluated in MATLAB environment. Communication with DA converter ensures DAC design block. PWM transforms a 12-bit (duty) signal into a 1-bit signal, period is set to 800, but binary. LNS were used only in controller design not in signal processing of speed. The whole running workspace is in the fig. 13.
Fig. 10. Controller design for hybrid implementation
The results of live system are not shown, because only 12 bit DAC is present. With 12 bit accuracy all controllers behave identically and better precision would be required to see the difference between them. In the fig. 10. an LNS_DSP controller is being used to run the motor.
Fig. 11. Comparison of hybrid LNS and FLP Type BRAMs(135) DSPs(24) LUTs(63400) Registers(126800) LNS_Hybrid 1 14 8820 464 FLP 0 4 4820 64 FP 0 2 1751 32
Fig. 12. Resource analysis of hybrid LNS, FLP and FP. In the LNS a zero value is problematic course of action. As when zero value is at the input of our system, which in
Fig. 13. Workstation with implemented LNS controller
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5. CONCLUSIONS
REFERENCES
In this paper we have implemented a 5 PI controllers, where fixed point and floating point based were to act as reference to our LNS design. LNS are not used in many real-time applications, have no standard, and most of the authors implement them for specific situations or with too strict restrictions.
N. G. Kingsbury and P. J. W. Rayner, "Digital filtering using logarithmic arithmetic," in Electronics Letters, vol. 7, no. 2, pp. 56-58, 28 January 1971. doi: 10.1049/el:19710039. E. E. Swartzlander and A. G. Alexopoulos, "The Sign/Logarithm Number System," in IEEE Transactions on Computers, vol. C-24, no. 12, pp. 1238-1242, Dec. 1975. doi: 10.1109/T-C.1975.224172 M. G. Arnold, "A VLIW architecture for logarithmic arithmetic," Euromicro Symposium on Digital System Design, 2003. Proceedings., Belek-Antalya, Turkey, 2003, pp. 294-302. doi: 10.1109/DSD.2003.1231957 M. Chugh and B. Parhami, "Logarithmic arithmetic as an alternative to floating-point: A review," 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2013, pp. 1139-1143. doi: 10.1109/ACSSC.2013.6810472 D. K. Kostopoulos, "An algorithm for the computation of binary logarithms," in IEEE Transactions on Computers, vol. 40, no. 11, pp. 1267-1270, Nov. 1991. doi: 10.1109/12.102831 D. Marino, "New Algorithms for the Approximate Evaluation in Hardware of Binary Logarithms and Elementary Functions," in IEEE Transactions on Computers, vol. C21, no. 12, pp. 1416-1421, Dec. 1972. doi: 10.1109/TC.1972.223516 F. Taylor, "An extended precision logarithmic number system," in IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. 31, no. 1, pp. 232-234, February 1983. doi: 10.1109/TASSP.1983.1164042 M. Chugh and B. Parhami, "Logarithmic arithmetic as an alternative to floating-point: A review," 2013 Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2013, pp. 1139-1143. doi: 10.1109/ACSSC.2013.6810472 Barry, R., Lee., A comparison of logarithmic and floating point number systems implemented on Xilinx Virtex-II field programmable arrays. ProQuest, Cardiff, University of Wales, 2004. UMI: U584674. Finnerty, A., and Ratigner, H., Reduce Power and Cost by Converting from Floating Point to Fixed Point, [online], [cited 10.1.2019], available at: https://www.xilinx.com/support/documentation/white_pa pers/wp491-floating-to-fixed-point.pdf S. Z. M. Naziri, R. C. Ismail and A. Y. M. Shakaff, "The design revolution of logarithmic number system architecture," 2014 2nd International Conference on Electrical, Electronics and System Engineering (ICEESE), Kuala Lumpur, 2014, pp. 5-10. doi: 10.1109/ICEESE.2014.7154603 R.C. Ismail, S.A.Z. Murad, R. Hussin, J.N. Coleman, Improved Subtraction Function for Logarithmic Number System, Procedia Engineering, Volume 53, 2013, Pages 387-392, ISSN 1877-7058, S. E. Tropea, "FPGA Implementation of Base-N Logarithm," 2007 3rd Southern Conference on Programmable Logic, Mar del Plata, 2007, pp. 27-32. doi: 10.1109/SPL.2007.371719
We chose to implement them for the first time in automation control, to show their possible value. The implementation was done on simple PI controller and the first order motor. The simplicity of solution provided a challenge to implement a real-time addition and subtraction of LNS, overcome the 0 problematic, define our own standard, which can be used in the future – make our solution repeatable and adaptable to other type of controllers, for example more advanced LQPI state space controller. Transformation to and back from LNS took some precision and area resources, depending on the type of implementation. These transformations could be avoided if the whole system (e.g. sensor, PWM etc.) were LNS. This possibility can be purpose of another study, as implementing whole system, not just controller could bring interesting solutions. Precision can be considered as the same of the floating point, while the adjustability of floating point is much lesser compared to LNS, the area resource used by the floating points were lesser. One of the reason is too few multiplications in simple PI controller. When using BRAM, the area resources were lowered by significant amount, while the performance was similar to the 24 bit fixed point solution. Not all solution requires a high precision implementation. While when a higher precision is needed, LNS can provided that as well, but the resources used are higher. The precision is then competitive to floating points and in certain situations it is even higher than floating point. Area of resources were shown for all solutions. The best overall outcome was given by the hybrid solution, where used resources were reduced even by 50% while not loosing precision. Overall 50% reduction on DSP, around 30% reduction on LUTS, but the registers were raised by 725%. However the FPGA usage in more distributed, which can be considered good, because if the solution heavily weight only one type of resource, when a more complex design tries to by implemented, one can meet a technology hardware limitations. The experiment shown a way how to handle exception, that LNS bring with themselves and show an effective ways to adjust LNS designs to our desired solution and even on quick changing and dynamic system as the controller itself is. ACKNOWLEDGEMENT The paper was partially supported by the Slovak Research and Development Agency, grant No. APVV-17-0190 and the Slovak Cultural Educational Grant Agency, grant No. 038STU-4/2018.