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InP DHBTs with patterned sub-collector fabricated by elevated temperature N+ implant
Solid-State Electronics 49 (2005) 981–985 www.elsevier.com/locate/sse
High performance InP/InGaAs/InP DHBTs with patterned sub-collector fabricated by elevated temperature N+ implant Mary Chen *, Marko Sokolich, David Chow, Bin Shi, Rajesh Rajavel, Steven Bui, Yakov Royter, Steve Thomas III, Charles Fields HRL Laboratories, LLC 3011 Malibu Canyon Road, Malibu, CA 90265-4799, USA Received 29 October 2004; received in revised form 18 February 2005; accepted 16 March 2005 Available online 20 April 2005
The review of this paper was arranged by Prof. A. Zaslavsky
Abstract We have demonstrated InP/InGaAs/InP MBE-grown DHBTs fabricated with patterned sub-collector by elevated temperature 200 C N+ implant and subsequent device material over growth. Ft/Fmax > 250 GHz/300 GHz were obtained on DHBTs with 0.35 lm · 6 lm emitters from this process. Ring oscillators fabricated with this process showed good uniformity with 82% of yield on wafers and an average gate delay of 8 ps. Difference of surface morphology on re-grown DHBT layers over elevated temperature implanted and room temperature 22 C implanted sub-collector was observed. 2005 Elsevier Ltd. All rights reserved. Keywords: HBT; InP; Ion implantation; Over growth
1. Introduction Ion implantation is well known as a technique for selective area doping through masked implant. We have demonstrated the use of ion implantation prior to epitaxial growth to form a patterned N+ sub-collector as a new tool for scaling InP HBTs [1]. The process flow and details of the ion implantation have been reported elsewhere [2]. It was found in our experiments that implant temperature is a determining factor for obtaining device quality material in the sub-collector implant region and subsequent device layer over growth. In this presentation we report results from elevated-temperature 200 C and room temperature 22 C sub-collector implant experiments and subsequent device layers over growth. Fur-
*
Corresponding author. Tel.: +1 310 317 5736; fax: +1 310 317 5152. E-mail address: [email protected] (M. Chen).
0038-1101/$ - see front matter 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2005.03.013
nace annealing conditions are the same for wafers implanted under 200 and 22 C: 6 min at 680 C under phosphine over-pressure.
2. Experiments and analysis for material characterization ˚ MBE-grown unSi+ was implanted into a 3000 A doped InP on a S.I. InP substrate under room temperature 22 C followed by a furnace annealing. Then a 0.5 lm N+ InAlAs layer was deposited by MBE. X-ray diffraction (XRD) pattern is shown in Fig. 1(a). The X-ray diffraction peak is coincident with the InP substrate peak, indicating good lattice match. It was found XRD peak widths from layers grown on room temperature 22 C implanted sub-collector are similar to widths from layers grown on elevated temperature 200 C implanted sub-collector [2], indicating similar bulk crystalline quality. However, under microscope inspection, the surface morphology shows increased
M. Chen et al. / Solid-State Electronics 49 (2005) 981–985
Fe concentration (cm-3)
982
Room temperature Si implant into 0.3µm InP(und.) / InP(Fe) substrate
1019 1018 1017 1016
0.0
0.2
Fe concentration (cm-3)
(a)
0.4
0.6
0.8
Depth (microns)
Elevated temperature Si implant into InP(Fe) substrate
19
10
1018 1017 16
10
0.0
Fig. 1. (a) X-ray diffraction from an InAlAs layer deposited on room temperature implanted and annealed MBE InP/InP S.I. substrate. (b) TENCOR surface profile on top of re-grown InAlAs layer over room temperature implanted and annealed MBE InP/InP S.I. substrate.
roughness compared with the surface prior to re-growth. Fig. 1(b) shows surface profile on top of re-grown N+ InAlAs by TENCOR and indicates surface roughness ˚ approximately. This roughness may be of 50–100 A caused by residual implant damage not fully removed by annealing. Fig. 2(a) shows SIMS profile of Fe in a room-temper˚ MBE-grown undoped ature 22 C Si+ implanted 3000 A InP layer on a S.I. InP substrate after furnace anneal. Fig. 2(b) is a SIMS profile of Fe in an elevated-temperature 200 C Si+ implanted S.I. InP substrate after a similar furnace anneal. The implant energy and dosages ˚ depth from the surface for are equal, targeted at 4000 A those two wafers. In both cases the level of Fe concentration was orders of magnitude lower than the N+ implant concentration [1] and it does not appear the profile of the Fe concentration affected Si+ implant profile. No direct comparison was attempted on these two SIMS profiles since before implant the material structures of the two wafers were not the same. However a few facts can still be easily observed. First, there is a clear indica˚ Fe movement in the room-temperation that 1000 A ture 22 C implanted wafer occurred from the S.I. InP substrate into the MBE-grown undoped InP region because there was no Fe in the MBE-grown undoped InP. This could indicate the damage caused by the room-temperature 22 C implant generated a path for
(b)
0.2
0.4
0.6
0.8
Depth (microns)
˚ Fig. 2. (a) SIMS profile of Fe of room temperature implanted 3000 A MBE-grown undoped InP on an S.I. InP substrate after anneal. (b) SIMS profile of Fe of elevated temperature implanted and annealed InP S.I. substrate after anneal.
Fe ions to move within implant and longitudinal straggling range during implant and/or anneal. Second, from range of 0.6–0.8 lm, or the tail part of the implant range, the profile from the room-temperature implant 22 C shows a clearer boundary between the amorphized layer and the virgin crystal than does the profile from elevated-temperature 200 C implant. Actually the SIMS profile shown in 2(a) has similarity with reported in [3], which shows Fe redistribution in room temperature Si+ implanted InP substrate after annealing. The SIMS profile of Fe in Fig. 2(b) shows very small amount of Fe concentration variance vs. depth from surface (except near surface [3]). This may indicate Fe in elevatedtemperature 200 C implanted S.I. InP substrate has very little movement after annealing. Considering annealing condition after implant is 6 min at 680 C which is much higher than HBT layer MBE growth temperature diffusion of Fe is not likely to occur in case of layers with MBE grown structure. It was found in our experiments that room temperature 22 C implanted InP can be etched by a solution containing HF before annealing. The etch rate was significantly reduced by annealing and no measurable etch rate was obtained after annealing. However, no measurable etch rate was found in elevated-temperature 200 C implanted InP by HF solution before annealing. These
M. Chen et al. / Solid-State Electronics 49 (2005) 981–985
results were all from patterned implanted wafers. On room temperature 22 C implanted wafers, no significant etch rate was found from masked area during implant. This is a strong indication that the roomtemperature 22 C implant causes more damage than the elevated-temperature 200 C implant. Although there are indications that annealing removed some of the damage created by the room temperature 22 C implant, no device-quality layers were obtained from re-growth. There will be more discussions of the effect of implant temperature to re-growth layer quality in the following section.
3. Device and circuit results The layer structure of the InP/InGaAs/InP DHBT reported here is listed in Table 1 and is similar to the structure reported in [1] except that an InP emitter and emitter cap replaced the InAlAs emitter and emitter cap. The doping of the InP emitter is 8.0E17/cm3. There is no chirped superlattice, nor graded region at the emitter/base junction. Our overgrowth of HBT layers from collector up on elevated-temperature 200 C implanted sub-collectors show excellent device quality. Fig. 3(a) shows a SEM
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image of a DHBT with elevated-temperature 200 C patterned sub-collector implant after base contact metallization. The emitter size of the HBTs is 10 lm · 10 lm. The surface morphology of overgrowth layers is excellent. As a comparison, Fig. 3(b) shows a SEM image of a DHBT of same size and layer structure as in Fig. 3(a) , but with room-temperature 22 C patterned sub-collector implant. The area showing surface roughness in Fig. 3(b) indicates implanted sub-collector area underneath. Surface morphology of the other area in Fig. 3(b) grown on top of the masked area during room-temperature 22 C implant is smooth. In other words only areas of overgrowth on top of room-temperature 22 C implanted areas show surface roughness. This indicates room-temperature 22 C implant might have caused the surface roughness of the overgrowth device material. Fig. 4(a) is from a TENCOR instrument measurement on top of re-grown DHBT layer over patterned room-temperature 22 C implanted sub-collector. ˚ can be Surface roughness of approximately 50–100 A seen in areas re-grown over room temperature implanted area while the surface morphology in area regrown over not-implanted area is much smoother. The range of surface roughness is similar to Fig. 1(b). Fig. 4(a) also indicates areas re-grown over room temperature implanted area have higher growth rate than area
Table 1 Layer structure of InP/InGaAs/InP DHBT Layer description MBE MBE MBE MBE MBE
InGaAs contact InP emitter contact InP emitter InGaAs base layer Quaternary grade InP collector
˚) Thickness (A
Doping level (cm 3)
1100 400 1050 325 980
n: n: n: p: n:
2.1E19 1.0E19 8.0E17 2.9E19 1.0E17
Fig. 3. SEM image of a DHBT with 10 · 10 lm2 InP emitter after base contact. (a) Re-grown HBT layers on top of elevated-temperature patterned implanted sub-collector shows good surface morphology. (b) Area with surface roughness indicates room temperature implanted patterned subcollector implant underneath.
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M. Chen et al. / Solid-State Electronics 49 (2005) 981–985 Ft,Fmax 0.35x6µm HBT 350 Ft
Cutoff Frequency (GHz)
300
Fmax
250 200 150 100 50 0 0.01
0.10
1.00
10.00
100.00
Collector Current (mA)
Fig. 5. Ft/Fmax of a DHBT with 0.35 lm · 6 lm emitter from elevatedtemperature patterned sub-collector implant and re-grown process. Lower curve represents Ft. Upper curve represents Fmax.
re-grown over not implanted area. This might be related to remaining damage from room-temperature 22 C implant after anneal. Fig. 4(b) shows surface profile of a re-grown DHBT over elevated temperature implanted sub-collector with InAs emitter cap layer. The surface ˚ and is significantly roughness is approximately 10–20 A smoother compared with Fig. 4(a). This shows even with InAs cap layer which usually is with more surface roughness than InGaAs cap layer, surface morphology of re-grown DHBTs over elevated temperature implanted sub-collector is still significantly smoother than re-grown DHBTs with InGaAs cap layer over room temperature implanted sub-collector. A process has been developed at HRL to deposit MBE-grown HBT layers on an elevated-temperature 200 C implanted InP sub-collector layer with good material quality and no interfacial charge. Specific contact resistance of collector contacts on elevated temperature implanted InP sub-collector in range of 10 7 X cm2 was obtained from TLM measurements. Results that demonstrate efficiency of the ion implantation process in providing a reduction of the base–collector capacitance were obtained from our experiments [2]. Fig. 5 shows Ft/Fmax 271 GHz/301 GHz obtained with Vce 1.5 V from a typical InP/InGaAs/InP DHBT with a 0.35 lm · 6 lm emitter and elevated-temperature
Ring Oscillator Gate Delay Uniformity
14 12 10 Count
Fig. 4. (a) TENCOR surface profile on top of re-grown DHBT layers over room temperature 22 C patterned implanted sub-collector. (b) TENCOR surface profile on top of re-grown DHBT layers over elevated temperature patterned implanted sub-collector.
200 C patterned sub-collector implant process. The width of implanted area is similar to emitter width [2]. Both Ft and Fmax were extrapolated from s-parameter measurements at frequencies up to 110 GHz. This is the highest Ft/Fmax ever obtained in InP DHBTs with a patterned sub-collector implant and re-growth. We conclude that excellent MBE re-grown device layer quality can be obtained on a patterned sub-collector implanted at elevated temperature. For further evaluation of material uniformity and HBT yield, a number of ring oscillators were tested using DHBTs with various size emitters. Among them, 15-stage ring oscillator circuits employing 1 · 3 lm2 DHBT and CML inverters provided 82% of yield on wafers with average gate delay of 8 ps. Fig. 6 shows a typical distribution of CML gate delay on one wafer. These results demonstrated a high potential of elevated-temperature patterned sub-collector
8 6 4 2 0
0
2
4
6
8
10
Gate Delay, ps
Fig. 6. Distribution of CML gate delay of 15-stage ring oscillators on one wafer.
M. Chen et al. / Solid-State Electronics 49 (2005) 981–985
implant, with subsequent device layer re-growth technique for DHBT IC applications.
Acknowledgements We thank John Zolper at DARPA and Mark Pacer at AFRL for supporting this work. We thank Young Boegeman, Mary Montes, Arlene Arthur, Jana Duvall, Rosanna Martinez, and AnnaMaria Shoemaker for wafer processing. We also thank Bill Stanchina for helpful discussions and encouragement.
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References [1] Sokolich M, Chen MY, Chow DH, Royter Y, Thomas III S, Fields CH, et al. InP HBT integrated circuit technology with selectively implanted subcollector and regrown layers. In: GaAs IC Symp 2003. p. 219–22. [2] Chen M, Sokolich M, Chow D, Bui S, Royter Y, Thomas III S, et al.. Patterned n+ implant into InP substrate for HBT sub-collector. IEEE Trans Electron Devices 2004;51(10):1736– 39. [3] Gauneau M, Chaplain R, Rupert A, Rao EVK, Duhamel N. Further evidence of chromium, manganese, iron, and zinc redistribution in indium phosphide after annealing. J Appl Phys 1985;57(4):1029–35.
High performance InP/InGaAs/InP DHBTs with patterned sub-collector fabricated by elevated temperature N+ implant Mary Chen *, Marko Sokolich, David Chow, Bin Shi, Rajesh Rajavel, Steven Bui, Yakov Royter, Steve Thomas III, Charles Fields HRL Laboratories, LLC 3011 Malibu Canyon Road, Malibu, CA 90265-4799, USA Received 29 October 2004; received in revised form 18 February 2005; accepted 16 March 2005 Available online 20 April 2005
The review of this paper was arranged by Prof. A. Zaslavsky
Abstract We have demonstrated InP/InGaAs/InP MBE-grown DHBTs fabricated with patterned sub-collector by elevated temperature 200 C N+ implant and subsequent device material over growth. Ft/Fmax > 250 GHz/300 GHz were obtained on DHBTs with 0.35 lm · 6 lm emitters from this process. Ring oscillators fabricated with this process showed good uniformity with 82% of yield on wafers and an average gate delay of 8 ps. Difference of surface morphology on re-grown DHBT layers over elevated temperature implanted and room temperature 22 C implanted sub-collector was observed. 2005 Elsevier Ltd. All rights reserved. Keywords: HBT; InP; Ion implantation; Over growth
1. Introduction Ion implantation is well known as a technique for selective area doping through masked implant. We have demonstrated the use of ion implantation prior to epitaxial growth to form a patterned N+ sub-collector as a new tool for scaling InP HBTs [1]. The process flow and details of the ion implantation have been reported elsewhere [2]. It was found in our experiments that implant temperature is a determining factor for obtaining device quality material in the sub-collector implant region and subsequent device layer over growth. In this presentation we report results from elevated-temperature 200 C and room temperature 22 C sub-collector implant experiments and subsequent device layers over growth. Fur-
*
Corresponding author. Tel.: +1 310 317 5736; fax: +1 310 317 5152. E-mail address: [email protected] (M. Chen).
0038-1101/$ - see front matter 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.sse.2005.03.013
nace annealing conditions are the same for wafers implanted under 200 and 22 C: 6 min at 680 C under phosphine over-pressure.
2. Experiments and analysis for material characterization ˚ MBE-grown unSi+ was implanted into a 3000 A doped InP on a S.I. InP substrate under room temperature 22 C followed by a furnace annealing. Then a 0.5 lm N+ InAlAs layer was deposited by MBE. X-ray diffraction (XRD) pattern is shown in Fig. 1(a). The X-ray diffraction peak is coincident with the InP substrate peak, indicating good lattice match. It was found XRD peak widths from layers grown on room temperature 22 C implanted sub-collector are similar to widths from layers grown on elevated temperature 200 C implanted sub-collector [2], indicating similar bulk crystalline quality. However, under microscope inspection, the surface morphology shows increased
M. Chen et al. / Solid-State Electronics 49 (2005) 981–985
Fe concentration (cm-3)
982
Room temperature Si implant into 0.3µm InP(und.) / InP(Fe) substrate
1019 1018 1017 1016
0.0
0.2
Fe concentration (cm-3)
(a)
0.4
0.6
0.8
Depth (microns)
Elevated temperature Si implant into InP(Fe) substrate
19
10
1018 1017 16
10
0.0
Fig. 1. (a) X-ray diffraction from an InAlAs layer deposited on room temperature implanted and annealed MBE InP/InP S.I. substrate. (b) TENCOR surface profile on top of re-grown InAlAs layer over room temperature implanted and annealed MBE InP/InP S.I. substrate.
roughness compared with the surface prior to re-growth. Fig. 1(b) shows surface profile on top of re-grown N+ InAlAs by TENCOR and indicates surface roughness ˚ approximately. This roughness may be of 50–100 A caused by residual implant damage not fully removed by annealing. Fig. 2(a) shows SIMS profile of Fe in a room-temper˚ MBE-grown undoped ature 22 C Si+ implanted 3000 A InP layer on a S.I. InP substrate after furnace anneal. Fig. 2(b) is a SIMS profile of Fe in an elevated-temperature 200 C Si+ implanted S.I. InP substrate after a similar furnace anneal. The implant energy and dosages ˚ depth from the surface for are equal, targeted at 4000 A those two wafers. In both cases the level of Fe concentration was orders of magnitude lower than the N+ implant concentration [1] and it does not appear the profile of the Fe concentration affected Si+ implant profile. No direct comparison was attempted on these two SIMS profiles since before implant the material structures of the two wafers were not the same. However a few facts can still be easily observed. First, there is a clear indica˚ Fe movement in the room-temperation that 1000 A ture 22 C implanted wafer occurred from the S.I. InP substrate into the MBE-grown undoped InP region because there was no Fe in the MBE-grown undoped InP. This could indicate the damage caused by the room-temperature 22 C implant generated a path for
(b)
0.2
0.4
0.6
0.8
Depth (microns)
˚ Fig. 2. (a) SIMS profile of Fe of room temperature implanted 3000 A MBE-grown undoped InP on an S.I. InP substrate after anneal. (b) SIMS profile of Fe of elevated temperature implanted and annealed InP S.I. substrate after anneal.
Fe ions to move within implant and longitudinal straggling range during implant and/or anneal. Second, from range of 0.6–0.8 lm, or the tail part of the implant range, the profile from the room-temperature implant 22 C shows a clearer boundary between the amorphized layer and the virgin crystal than does the profile from elevated-temperature 200 C implant. Actually the SIMS profile shown in 2(a) has similarity with reported in [3], which shows Fe redistribution in room temperature Si+ implanted InP substrate after annealing. The SIMS profile of Fe in Fig. 2(b) shows very small amount of Fe concentration variance vs. depth from surface (except near surface [3]). This may indicate Fe in elevatedtemperature 200 C implanted S.I. InP substrate has very little movement after annealing. Considering annealing condition after implant is 6 min at 680 C which is much higher than HBT layer MBE growth temperature diffusion of Fe is not likely to occur in case of layers with MBE grown structure. It was found in our experiments that room temperature 22 C implanted InP can be etched by a solution containing HF before annealing. The etch rate was significantly reduced by annealing and no measurable etch rate was obtained after annealing. However, no measurable etch rate was found in elevated-temperature 200 C implanted InP by HF solution before annealing. These
M. Chen et al. / Solid-State Electronics 49 (2005) 981–985
results were all from patterned implanted wafers. On room temperature 22 C implanted wafers, no significant etch rate was found from masked area during implant. This is a strong indication that the roomtemperature 22 C implant causes more damage than the elevated-temperature 200 C implant. Although there are indications that annealing removed some of the damage created by the room temperature 22 C implant, no device-quality layers were obtained from re-growth. There will be more discussions of the effect of implant temperature to re-growth layer quality in the following section.
3. Device and circuit results The layer structure of the InP/InGaAs/InP DHBT reported here is listed in Table 1 and is similar to the structure reported in [1] except that an InP emitter and emitter cap replaced the InAlAs emitter and emitter cap. The doping of the InP emitter is 8.0E17/cm3. There is no chirped superlattice, nor graded region at the emitter/base junction. Our overgrowth of HBT layers from collector up on elevated-temperature 200 C implanted sub-collectors show excellent device quality. Fig. 3(a) shows a SEM
983
image of a DHBT with elevated-temperature 200 C patterned sub-collector implant after base contact metallization. The emitter size of the HBTs is 10 lm · 10 lm. The surface morphology of overgrowth layers is excellent. As a comparison, Fig. 3(b) shows a SEM image of a DHBT of same size and layer structure as in Fig. 3(a) , but with room-temperature 22 C patterned sub-collector implant. The area showing surface roughness in Fig. 3(b) indicates implanted sub-collector area underneath. Surface morphology of the other area in Fig. 3(b) grown on top of the masked area during room-temperature 22 C implant is smooth. In other words only areas of overgrowth on top of room-temperature 22 C implanted areas show surface roughness. This indicates room-temperature 22 C implant might have caused the surface roughness of the overgrowth device material. Fig. 4(a) is from a TENCOR instrument measurement on top of re-grown DHBT layer over patterned room-temperature 22 C implanted sub-collector. ˚ can be Surface roughness of approximately 50–100 A seen in areas re-grown over room temperature implanted area while the surface morphology in area regrown over not-implanted area is much smoother. The range of surface roughness is similar to Fig. 1(b). Fig. 4(a) also indicates areas re-grown over room temperature implanted area have higher growth rate than area
Table 1 Layer structure of InP/InGaAs/InP DHBT Layer description MBE MBE MBE MBE MBE
InGaAs contact InP emitter contact InP emitter InGaAs base layer Quaternary grade InP collector
˚) Thickness (A
Doping level (cm 3)
1100 400 1050 325 980
n: n: n: p: n:
2.1E19 1.0E19 8.0E17 2.9E19 1.0E17
Fig. 3. SEM image of a DHBT with 10 · 10 lm2 InP emitter after base contact. (a) Re-grown HBT layers on top of elevated-temperature patterned implanted sub-collector shows good surface morphology. (b) Area with surface roughness indicates room temperature implanted patterned subcollector implant underneath.
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M. Chen et al. / Solid-State Electronics 49 (2005) 981–985 Ft,Fmax 0.35x6µm HBT 350 Ft
Cutoff Frequency (GHz)
300
Fmax
250 200 150 100 50 0 0.01
0.10
1.00
10.00
100.00
Collector Current (mA)
Fig. 5. Ft/Fmax of a DHBT with 0.35 lm · 6 lm emitter from elevatedtemperature patterned sub-collector implant and re-grown process. Lower curve represents Ft. Upper curve represents Fmax.
re-grown over not implanted area. This might be related to remaining damage from room-temperature 22 C implant after anneal. Fig. 4(b) shows surface profile of a re-grown DHBT over elevated temperature implanted sub-collector with InAs emitter cap layer. The surface ˚ and is significantly roughness is approximately 10–20 A smoother compared with Fig. 4(a). This shows even with InAs cap layer which usually is with more surface roughness than InGaAs cap layer, surface morphology of re-grown DHBTs over elevated temperature implanted sub-collector is still significantly smoother than re-grown DHBTs with InGaAs cap layer over room temperature implanted sub-collector. A process has been developed at HRL to deposit MBE-grown HBT layers on an elevated-temperature 200 C implanted InP sub-collector layer with good material quality and no interfacial charge. Specific contact resistance of collector contacts on elevated temperature implanted InP sub-collector in range of 10 7 X cm2 was obtained from TLM measurements. Results that demonstrate efficiency of the ion implantation process in providing a reduction of the base–collector capacitance were obtained from our experiments [2]. Fig. 5 shows Ft/Fmax 271 GHz/301 GHz obtained with Vce 1.5 V from a typical InP/InGaAs/InP DHBT with a 0.35 lm · 6 lm emitter and elevated-temperature
Ring Oscillator Gate Delay Uniformity
14 12 10 Count
Fig. 4. (a) TENCOR surface profile on top of re-grown DHBT layers over room temperature 22 C patterned implanted sub-collector. (b) TENCOR surface profile on top of re-grown DHBT layers over elevated temperature patterned implanted sub-collector.
200 C patterned sub-collector implant process. The width of implanted area is similar to emitter width [2]. Both Ft and Fmax were extrapolated from s-parameter measurements at frequencies up to 110 GHz. This is the highest Ft/Fmax ever obtained in InP DHBTs with a patterned sub-collector implant and re-growth. We conclude that excellent MBE re-grown device layer quality can be obtained on a patterned sub-collector implanted at elevated temperature. For further evaluation of material uniformity and HBT yield, a number of ring oscillators were tested using DHBTs with various size emitters. Among them, 15-stage ring oscillator circuits employing 1 · 3 lm2 DHBT and CML inverters provided 82% of yield on wafers with average gate delay of 8 ps. Fig. 6 shows a typical distribution of CML gate delay on one wafer. These results demonstrated a high potential of elevated-temperature patterned sub-collector
8 6 4 2 0
0
2
4
6
8
10
Gate Delay, ps
Fig. 6. Distribution of CML gate delay of 15-stage ring oscillators on one wafer.
M. Chen et al. / Solid-State Electronics 49 (2005) 981–985
implant, with subsequent device layer re-growth technique for DHBT IC applications.
Acknowledgements We thank John Zolper at DARPA and Mark Pacer at AFRL for supporting this work. We thank Young Boegeman, Mary Montes, Arlene Arthur, Jana Duvall, Rosanna Martinez, and AnnaMaria Shoemaker for wafer processing. We also thank Bill Stanchina for helpful discussions and encouragement.
985
References [1] Sokolich M, Chen MY, Chow DH, Royter Y, Thomas III S, Fields CH, et al. InP HBT integrated circuit technology with selectively implanted subcollector and regrown layers. In: GaAs IC Symp 2003. p. 219–22. [2] Chen M, Sokolich M, Chow D, Bui S, Royter Y, Thomas III S, et al.. Patterned n+ implant into InP substrate for HBT sub-collector. IEEE Trans Electron Devices 2004;51(10):1736– 39. [3] Gauneau M, Chaplain R, Rupert A, Rao EVK, Duhamel N. Further evidence of chromium, manganese, iron, and zinc redistribution in indium phosphide after annealing. J Appl Phys 1985;57(4):1029–35.