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Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits
Microelectronics Journal 42 (2011) 942–949
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits Mohammad Javad Sharifi a,n, Davoud Bahrepour b a b
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Velenjak, Tehran, Iran Science and Research Branch, Islamic Azad University, Tehran, Iran
a r t i c l e i n f o
a b s t r a c t
Article history: Received 15 October 2010 Received in revised form 27 January 2011 Accepted 27 April 2011
Single electron devices (SEDs) are utilized in designing many logic gates; however, in most cases the examination of the circuits is limited to a DC analysis that only indicates the correct performance of the circuits’ logic function. This paper focuses mainly on the issue of optimization. In this regard, comparison of different designs is needed, but it is not possible to compare two different designs unless they both belong to a single technology or can be scaled to a same technology. So, we first introduce a technology index for SEDs, which allows meaningful comparisons between various designs of different technologies. Then, we describe a method for scaling these designs into a single identical technology, and clarifying the relations between the involved concepts. Using two examples, we explain an optimum design method for digital logic gates based on SEDs. Finally, the results of these two examples are presented and compared with the original designs. The comparison showed that all the three major performance features, including lower bit error rate, higher operation frequency, and higher temperature operation are improved in the proposed optimized design. & 2011 Elsevier Ltd. All rights reserved.
Keywords: Optimum design procedure Technology index Single electron device Digital gate
1. Introduction
2. Technology index and scaling
Due to their ultra small dimensions and lower power consumption, single-electron devices (SEDs) are good candidates for future ULSI applications. Although they are utilized in many digital logic gates [1–7], gate operation is usually examined merely by a simple verification using SIMON [8], and optimum design procedures are either less studied or the procedures presented are incomplete [9–11] or very complex [12]. This paper aims to present a method for achieving optimum performance of SED-based digital gates by introducing a simple quality index. In Section 2, the technology concepts are discussed and a technology index for SEDs is introduced. In Section 3, we consider a NOT gate as our first example and propose a design procedure for optimum gate performance. This design procedure is based on a single index, the quality index, that characterizes the performance. The design procedure and optimum design will be repeated for a NAND gate, as the second example, in Section 4. Finally, conclusions are provided in Section 5.
For any comparison between the performances of two different designs to be valid, the first important parameter is that the two designs must be implemented in a same technology. In other words, comparison of two designs, which are implemented in two different technologies, is not valid unless the two designs are scaled into a single technology. Therefore, we need an index for SED technology.
n
Corresponding author. Tel.: þ98 9123045891; fax: þ 98 21 29902284. E-mail addresses: m_j_sharifi@sbu.ac.ir (M. Javad Sharifi), [email protected] (D. Bahrepour). 0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2011.04.014
2.1. Introducing the technology index On one hand, a good technology index should be based on real technological limitations, and on the other hand, it should also have a clear relation with the performance of the circuits that are based on that technology. A well-known technology index is the minimum feature size for MOSFET technology. This indexes MOSFET technology in an excellent fashion because it not only reveals the most important limitations of the technology but it also has a clear relation with MOSFET circuit performances. Here, regarding SEDs and the two technology index criteria mentioned above, we introduce the total capacitor of the island, CT, and the tunneling resistor, RT, as the technology index. These two parameters are related to the SEDs’ technological limitations; because CT reveals the possibility of miniaturization and RT is associated with the technology’s manufacturing tolerance, which is of growing importance. As we see later,
M. Javad Sharifi, D. Bahrepour / Microelectronics Journal 42 (2011) 942–949
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these two parameters will also determine the SED circuit performances. 2.2. Scaling method Using the above-mentioned technology index, one can transfer a design from one technology to another, and a comparison of designs in different technologies would then be possible. For this purpose, the scaling factors are defined as follows: CT,new CT,old
ð1Þ
RT,new RSF9 RT,old
ð2Þ
CSF9
Fig. 1. A simple NOT gate based on a SEB [13] (Cin ¼Ct ¼ Cb ¼40 aF).
where CSF is the capacitance scaling factor, CT,new is the total capacitor in the new technology, CT,old is the total capacitor in the old technology, RSF is the tunneling resistance scaling factor, RT,new is the tunneling resistance in the new technology, and RT,old is the tunneling resistance in the old technology. For a logic circuit design consists of more than one island or tunnel junction, the total capacitance for each island and the tunneling resistance for each tunnel junction should be considered, and then the smallest total capacitance and the smallest tunneling resistance should be selected as the technology of that design. The scaling process is as follows: The capacitors and the tunneling resistors are multiplied by CSF and RSF, respectively, and the voltages are divided by CSF. By doing so, the logic function remains unchanged.
technology. There are also the following equations: VOH ¼
Vb Cb VIL Cin CT CT
ð3Þ
VOL ¼
Vb Cb VIH Cin q þ CT CT CT
ð4Þ
where q is the unit charge. Assuming the symmetry of the logic levels around zero, the equality of the input and output voltages (VOL ¼VIL,VOH ¼VIH, VIL ¼ VIH), and VOH ¼V, we have V¼
Vb Cb VCin CT CT
V ¼
Vb Cb VCin q þ CT CT CT
In this section, the concept of design procedure and optimum design along with the method of using the proposed technology index in a design procedure is discussed. Here, as an applicable example, we choose a simple NOT gate [13] since it enables us to present the details of the design computations in an easy way. This section consists of three subsections. Section 3.1 describes the design procedure and shows when the desired requirements are applied to the describing equations, a single degree of freedom remains that can be spent for optimization. Section 3.2 discusses the concept of optimum design, introduces a quality index, and presents the optimized design. In Section 3.3, the simulation results are presented. We considered both the original and the selected technologies (here after called the new technology) as well as the original and the new optimized design. On the whole, we have introduced and compared four designs including the original design in the old technology, the optimized design in the old technology, the original design in the new technology, and the optimized design in the new technology. 3.1. Design procedure A NOT gate based on a single-electron box (SEB) is introduced by Klunder [13]. In this paper, this gate is used as an applicable example because of its simple structure. Fig. 1 shows the SEB-based NOT gate. Regarding the design procedure, there are nine unknown variables to be determined in this circuit: tunnel junction capacitance and resistance (CT, RT), logic 0 and logic 1 levels in the input and output (VIL, VIH, VOL, VOH), bias voltage and bias capacitance (Vb, Cb), and input capacitance (Cin). It should be noted that in this design procedure, CT and RT are left to be determined by the selected
ð6Þ
Substituting Eq. (5) to Eq. (6) yields Vb Cb ¼
3. Calculation method for a NOT gate
ð5Þ
q 2
ð7Þ
From Eq. (7), it can be seen that Cb scales the Vb value. Therefore, depending on the limitations of having a large enough Vb, Cb can be chosen as the smallest possible. Here, Cb must be small because our main limitation, based on the selected technology, is the total capacitance, CT, which must therefore be carefully spent. Up to now, seven out of nine variables have been determined, and following equation is for the last two unknown variables (V and Cin): V¼
q VC in 2CT CT
ð8Þ
with the requirement that all capacitance values should be positive. Applying this restriction to V leads the following two inequalities (the upper bound drives from the Cin ¼0, and the lower bound from the CT ¼ 0) q q oV o 2ð2CT Cb Þ 2CT
ð9Þ
In summary, four assumptions are made: predefined CT and RT, identical input and output logic levels, the symmetry of logic levels around zero, and a selected value for Vb. These assumptions are applied to satisfy this paper’s design procedure, and one degree of freedom still remains that can be used for design optimization. 3.2. Optimum performance design An optimum logic design usually has three main characteristics: (i) small physical dimensions (i.e., occupying the smallest possible area on the chip), (ii) low power consumption, and (iii) high-speed switching. By carefully considering these measures, it is obvious that the first one is fixed by the selection of the SED technology because a smaller CT means a smaller size, and vice versa. Regarding the second measure, it should be noted that
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it is also fixed by the selection of the SED technology because the energy dissipation of SEDs in a logic transition is only a function of CT (equal to e2/CT). Moreover, the power consumption in SEDs is extremely low and, in fact, does not require any optimization. For instance, in a SED circuit with CT ¼1 aF, energy consumption is 2.56 10 20 J (power consumption¼256 pW for 10 GHz clock frequency) and can be ignored. Therefore, there is no need to further consider these two measures and it can be concluded that optimization in SED-based circuits is related only to switching speed. Thus our goal is to determine the circuit elements and logic levels for the inputs and outputs to achieve the highest possible speed. However, the concept of speed in SEDs is slightly different from that in classical devices, which is discussed in the following. In the orthodox theory, which is the basic theory for SEDs, an electron’s transit time through a tunneling barrier is assumed to be zero [14]. Hence what remains from the time behavior is the tunneling time latency, which is a random time an electron waits behind a tunneling barrier before crossing. The probability density function of this waiting time has an exponential form. Consequently, if one waits any length of time, there is still a nonzero probability that the electron tunneling does not tunnel, and hence, no logic output is established. In this way, a bit error in the logic gate output is caused by the random time of transfer through a tunneling barrier. This error is a function of clock frequency, and increasing the clock frequency increases the bit error rate (BER). Besides the clock frequency, temperature can also cause errors, in that an electron without having received a command from the input can tunnel from a tunneling barrier by only obtaining energy from the environment. If TFE is the total error rate, we have TFE ¼ TE þFE
TEpeðqðVT VÞÞ=KB T
ð11Þ
FEpeGtp ¼ eG=F ¼ eððVT VÞÞ=qRt F
ð12Þ
where KB is the Boltzmann constant, T is absolute temperature, G is the tunneling rate at 0 K, tp is the clock period, F is the clock frequency, and V is the tunnel junction voltage described in Eq. (8). As seen from Eqs. (11) and (12), both the error terms are related to the V term, and this issue leads us to define a design quality index, DQ, as ð13Þ
The variable DQ is a unique quality index because it affects both error terms mentioned in Eqs. (11) and (12). In addition, note that DQ is dimensionless; hence, it is independent of SED technology, and therefore the results of an optimization process based on this index will be independent of the technology as well. This means that any circuit optimized with this method remains optimized in all technologies. By using Eq. (8), DQ is equal to DQ ¼
Cin CT þ Cin
CT Cb 2CT Cb
DQ 2Rt CT lnðTFEÞjT ¼ 0
ð16Þ
Tmax ¼
DQq2 2KB CT lnðTFEÞjF ¼ 0
ð17Þ
From Eqs. (16) and (17), we can find the scaling rules for Fmax and Tmax Fmaxnew ¼
Fmaxold CSF RSF
ð18Þ
Tmaxnew ¼
Tmaxold CSF
ð19Þ
These two formulas complete the set of scaling rules for the SED technology. We may conclude that: 1. Fmax and Tmax are linear functions of DQ; hence, they are optimized identically by DQ 2. Fmaxnew is a function of two technology parameters, i.e., reduction in dimensions and reduction in tolerance; decreasing CT and RT (up to its quantum limitation value, 25.8 KO) lead to a better Fmax. 3. Tmaxnew is only a function of CSF and therefore it improves only by shrinking the dimensions
3.3. Results and discussion This section compares four different versions of the NOT gate: (a) The original design in the old technology (mentioned in [13]). In this case, CT was equal to 120 aF and the RT value was not stated, which we consider it equal to 1 MO. (b) The optimized design in the old technology, where the technology is the same as (a) (i.e., CT ¼120 aF, RT ¼1 MO) but the circuit is redesigned according to the method introduced in this paper (with DQ ¼0.44); (c) The original design in the new technology, which is the same as (a), except that all the parameters are scaled to a new technology using Eqs. (1) and (2). Although we assumed CT ¼1 aF and RT ¼1 MO for the new technology, they are completely arbitrary. These values are not inaccessible in the current SED technology and have been used in some physical implementations [16–18]. Using this technology, CSF and RSF will be equal to 1/120 and 1, respectively. Table 1 Circuit parameters for the NOT gate using different designs. Parameter Old design in old technology [13]
Optimized design in old technology
Old design in Optimized design in new new technology technology
CT (aF) Cin (aF) Ct (aF) Cb (aF) RT (MO) VIL (mV) VIH (mV) VOL (mV) VOH (mV) Vb
120 96 12 12 1 0.36 0.36 0.36 0.36 6.66 mV
1 0.33 0.33 0.33 1 12 12 76 76 240 mV
ð14Þ
From the inequalities in Eq. (9), the quality index, DQ, is limited as 0 o DQ o
Fmax ¼
ð10Þ
where TE is the error caused by temperature and FE is the error caused by the frequency. Both terms are exponential functions of the distance between the applied voltage (across the tunnel junction) and the tunneling threshold voltage VT ¼ q=2CT [15]:
DQ ¼ ðVT VÞ=VT
Considering a specific TFE, a maximum frequency, Fmax, and a maximum temperature, Tmax, can be defined from the above mentioned equations. Fmax is the maximum frequency for a given TFE when the temperature is zero while Tmax is the maximum temperature for a given TFE when the frequency is equal to zero.
ð15Þ
As a practical value, we choose DQ¼ 0.44 (therefore Cin ¼ 0.8CT) and present its results as the optimized NOT gate design in the following subsection.
120 40 40 40 1 0.1 0.1 0.63 0.63 2 mV
1 0.8 0.1 0.1 1 44 44 44 44 0.8 V
M. Javad Sharifi, D. Bahrepour / Microelectronics Journal 42 (2011) 942–949
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Fig. 2. Simulation results of the NOT gate using SIMON: (a) the original design in the old technology (mentioned in [13]), (b) the optimized design in the old technology, (c) the original design in the new technology, and (d) the optimized design in the new technology (see Table 1 for parameters of each design).
Fig. 3. Time-transient behavior for the output of the NOT gate when it switches from logic 1 to logic 0 for (a) the original design in the old technology (with CT ¼ 120 aF and RT ¼ 1 MO), (b) the optimized design in the old technology (with CT ¼120 aF, RT ¼1 MO, and DQ ¼ 0.44), (c) the original design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO), and (d) the optimized design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO and DQ ¼0.44). As seen, after changing the technology, the switching speed becomes 120 times faster, and after optimization it again increases 11 times. The circuit parameters are shown in Table 1.
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(d) The optimized design in the new technology, where the circuit is redesigned and also scaled to the new technology (i.e., CT ¼1 aF, RT ¼1 MO with DQ ¼0.44).
Table 1 shows the circuit parameters for the above four versions. It should be noted that, in scaling, the logic function does not change, whereas performance changes significantly. Fig. 2 shows the simulation results of the NOT gate before and after scaling and also with and without optimization by utilizing SIMON in order to verify DC operation. Fig. 3 depicts the switching behavior for the logic 1 to logic 0 transition for above mentioned designs. It is obvious that using a better technology reduces the delay time by about 120 times. In addition, we see that in the optimized design, the speed again increases by about 11 times (the total speed in the d version increases by 1320 times in comparison with the total speed in the a version). Fig. 4 shows the curves of constant error in the frequency– temperature plane for different specific BERs. In the other words, it shows the performance of the designs in terms of error, frequency, and temperature. The curves show in what frequency– temperature combination, the gate can operate as long as the total error rate does not exceed the specified value. As expected, all the curves in Fig. 4 are descending, which means that
increasing the temperature in a specific BER decreases the operating frequency and, vice versa. However, the typical semisquared shape of the curves, especially for small BERs, means that both the maximum frequency, Fmax, and the maximum temperature, Tmax, are achievable almost simultaneously, and, of course, both performances are scaled with the specified total BER value. As seen in Fig. 4, for a specific BER, such as BER¼0.001, the maximum operating frequency and maximum operating temperature
Fig. 5. A two-input NAND gate based on a SEB [13] (Cin ¼Ct ¼Cb ¼40 aF).
Fig. 4. The NOT gate operating frequency variation curves at different temperatures for different BERs: (a) The original design in the old technology (with CT ¼ 120 aF and RT ¼ 1 MO), (b) the optimized design in the old technology (with CT ¼120 aF, RT ¼1 MO, and DQ ¼ 0.44), (c) the original design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO), and (d) the optimized design in the new technology (with CT ¼1 aF, RT ¼ 1 MO, and DQ ¼0.44).
M. Javad Sharifi, D. Bahrepour / Microelectronics Journal 42 (2011) 942–949
pair, (Fmax, Tmax) corresponding to designs (a)–(d) is (0.022 GHz, 0.042 K), (0.26 GHz, 0.49 K), (2.8 GHz, 5.3 K), and (32 GHz, 59 K), respectively. Again we conclude that both optimization and technology have a significant effect on the gate performance. Table 2 The temperature and frequency error probability relations for four different transitions. Transitions
TE
FE
00-11 01,10-11 11-00 11-01,10
eðqðVT Vo00ÞÞ=KT ¼ eðqðVT Vð12ðCin =CT ÞÞÞÞ=KT eðqðVT VÞÞ=KT eðqðVT VÞÞ=KT eðqðVT VÞÞ=KT
eððVT VÞÞ=qRT F eððVT VÞÞ=qRT F eððVT Vð12ðCin =CT ÞÞÞÞ=qRT F eððVT VÞÞ=qRT F
Table 3 Circuit parameters for the NAND gate: four implementations. Parameter Original design Optimized design in old in old technology technology [13]
Optimized Original design in new design in new technology technology
CT (aF) Cin (aF) Ct (aF) Cb (aF) RT (MO) VIL (mV) VIH (mV) Vo 00 (mV) Vo 01 (mV) Vo 11 (mV) Vb (mV)
160 40 40 40 Not specified 0.1 0.1 Not specified
160 57.6 28.8 16 1 0.365 0.365 0.1
1 0.25 0.25 0.25 1 16 16 68
1 0.36 0.18 0.1 1 58.4 58.4 16.35
Not specified
0.365
76
58.4
Not specified
0.365
76
58.4
1.9
3.65
304
584
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4. Optimum design for NAND gate As the second example, we choose another gate in order to demonstrate our optimum design procedure. Fig. 5 shows the new SEB based structure [13]. It is able to implement both NAND and NOR functions by applying appropriate voltages to the Vb. We choose this structure for implementing NAND function. It should be mentioned that computing the optimum design procedure for a NOR function will be the same. In the NAND structure, when the inputs are in 00 or 01state, electrons cannot tunnel through the tunnel junction; hence, the output will remain in high state. When inputs are in the 11 state, the voltage across the tunnel junction exceeds the threshold value. Consequently, one electron tunnels through the tunnel junction which leads to a negative voltage at the island, i.e. low output state. Here again, we will present an optimum design procedure for this circuit and also compare our results with the original one [13] with respect to the performance. The unknown variables for the NAND circuit are VinL, VinH, Vb, Cb, Cin, Ct, RT, Vo 00,Vo 01 and Vo 11 where Vo 00,Vo 01 and Vo 11 are output voltage when the inputs are in 00, 01, and, 11 states, respectively, and the other parameters are the same as the previous example (see also Fig. 5). First of all, the following relations are considered as some of the design requirements. VinL ¼ VinH ¼ V
ð20Þ
Vo01 ¼ V
ð21Þ
Vo11 ¼ V
ð22Þ
Hence, similar to previous section, three unknown variables are obtained. There are also the following equations, which calculate output voltage for different input combinations. Vo00 ¼
Cb Vb 2VCin CT CT
ð23Þ
Fig. 6. Simulation results of the NAND gate using SIMON: (a) the original design in the old technology (the original paper [13]), (b) the optimized design in the old technology, (c) the original design in the new technology, and (d) the optimized design in the new technology (see Table 2 for parameters of each design).
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Vo01 ¼ Vo10 ¼
M. Javad Sharifi, D. Bahrepour / Microelectronics Journal 42 (2011) 942–949
Cb Vb ¼V CT
ð24Þ
calculated by TFE ¼
C V 2VCin q ¼ V Vo11 ¼ b b þ CT CT CT
ð25Þ
In these equations Vb and Cb are always appear in a product form, thus, as previous, we can say that Vb scales Cb and we can choose Cb by considering the requirements of Vb. Again as previous, both RT and CT, (here CT ¼2Cin þCb þCt) are determined by the selected technology. Now, four unknown variables and three equations remain, and so, we have one degree of freedom that can be spent for optimization. In summary, we first had ten unknown variables and after applying the design requirements, choosing the desired value for Vb, and selecting the desired technology, a single parameter (say, V) remains, which now we are going to adjust it so that it optimizes the circuit performance. Again the performance is considered as minimum gate error, and other characteristics such as minimum area occupation and small power consumption are ignored based on the reasons stated previously. For each two-input gate, there are twelve possible transitions. The temperature fluctuations and/or the speed limitations can cause error transitions. Therefore the total mean error, TFE, is
12 1 X TE þ FEi 16 i ¼ 1 i
ð26Þ
where TEi and FEi are the temperature and the frequency errors for the ith possible transition, respectively. In a NAND gate, only six out of the twelve input combinations lead to a transition at the output and only four of them (namely 00–11, 01–11, 11–00, 11–01) are distinguishable due to the symmetry. The temperature and frequency error probabilities for these four transitions are illustrated in Table 2. Two of the error factors demonstrated in Table 2 are very small compared to others and can be ignored (00-11 for TE and 11-00 for FE). After eliminating these two errors, one can see that the remaining errors are a function of VT V. Now similar to the previous section, a dimensionless quality factor is introduced as DQ ¼
VT V VT
ð27Þ
The dimensionless feature of DQ ensures us that the optimization process will be independent of the selected technology. In other words, when a design is optimum in one technology it will be optimum in all other technologies. The lower bound of DQ is equal to zero (for V¼VT) and the upper bound is achieved by
Fig. 7. NAND gate operating frequency variation curves at different temperatures for different BERs: (a) the original design in the old technology (with CT ¼ 120 aF and RT ¼ 1 MO), (b) the optimized design in the old technology (with CT ¼120 aF, RT ¼1 MO, and DQ ¼ 0.27), (c) the original design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO), and (d) the optimized design in the new technology (with CT ¼1 aF, RT ¼ 1 MO and DQ ¼0.27).
M. Javad Sharifi, D. Bahrepour / Microelectronics Journal 42 (2011) 942–949
this assumption that Vo–00 should not be smaller than zero. By applying this condition (i.e., Vo 00 ¼0) to Eqs. (23) and (24), the upper bound of DQ is found to be equal to 0.33 (achieved when Cin ¼CT/2). In following we introduce the optimum design for the NAND gate with DQ ¼0.27. Table 3 shows the circuit parameters for four versions of the NAND gate. Fig. 6 shows the simulation results of the NAND gate for the four versions (before and after scaling; with and without optimization) by utilizing SIMON to verify the DC operation. Fig. 7, which is the same as Fig. 4, shows the frequency and temperature curves in different BERs for these four versions of NAND gate. Again, Fmax and Tmax are achieved from Eqs. (16) and (17), respectively. As seen in Fig. 7 for a specific BER, such as BER¼0.0001, the maximum operating frequency and maximum operating temperature pair, (Fmax, Tmax) corresponding to designs (a)–(d) is equal to (15 MHz, 38 mK), (2.42 GHz, 6.15 K), (81 MHz, 207 mK), and (13.1 GHz, 33.2 K), respectively. This figure shows that, by scaling the original design into the new technology, the performance increases 160 times and by optimizing the scaled design, the performance further increases about 5.4 times, which totally means 864 times better performance.
5. Conclusions In this paper, the concept of technology index for SEDs and a method for technology scaling is introduced for the first time. In addition, this paper discussed in detail the design procedure for a sample NOT gate based on SEB and introduced a design quality index, DQ, and also clarified its limitations. Then, using the DQ index, we presented an optimum design procedure. We then calculated the performance of the optimized design for the NOT gate and compared it with the original design in terms of the maximum operating frequency and the maximum operating temperature for a constant total BERs. Then, we chose a SEB based NAND gate as the second example. The proposed optimum design procedure was repeated in order to introduce the performance measures. The simulation results for the NOT and NAND gates illustrated that the frequency– temperature curves have semi-squared shapes; hence, both the maximum frequency and the maximum temperature are approximately achievable simultaneously. This finding is another of this paper’s contributions. Simulation results of the NOT and the NAND gates showed that utilizing the new technology will improve the performance by 120 and 160 times, respectively. Utilizing the optimum design will lead to additional 11 and 5.4 times better
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performance (1320 times and 864 times, totally, respectively). We showed that the design procedure and calculation methods are very similar for NOT and NAND gates. In fact, the proposed concepts are quite general and can be applied to almost all SED structures and designs. References [1] H. Iwamura, M. Akazawa, Y. Amemiya, Single electron majority logic circuits, IEICE Trans. Electron. E81-C (1) (1998) 42–46. [2] M.M. Dasigenis, I. Karafyllidis, A. Thanailakis, A single-electron XOR gate, Microelectron. J. 32 (2001) 117–119. [3] T.Y. Ono, A. Fujiwara, H. Inokawa, Silicon single-electron devices for logic applications, in: Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), May 2000, pp. 411–420. [4] Y. Takahashi, Y. Ono, A. Fujiwara, H. Inokawa, Multigate single-electron transistors and their application to an exclusive-OR gate, Appl. Phys. Lett. 76 (2000) 637–639. [5] T. Oya, T. Asai, T. Fukui, Y. Amemiya, A majority logic device using an irreversible single-electron box, IEEE Trans. Nanotechnol. 2 (2) (2003) 15–22. [6] S.E. Rehan, A novel half-adder using single electron tunneling technology, in: Proceedings of the 2nd IEEE International Conference on Nano/Micro Engineered and Molecular Systems, Bangkok, January 2007, pp. 245–249. [7] G.T. Zardalidis, I. Karafyllidis, A single electron half-adder, Microelectron. J. 33 (2002) 265–269. [8] C. Wasshuber, H. Kosina, S. Selberherr, SIMON—a simulator for singleelectron tunnel devices and circuits, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 16 (1997) 937–944. [9] G.T. Zardalidis, I. Karafyllidis, Design and simulation of a nanoelectronic single-electron control—NOT gate, Microelectron. J. 37 (2006) 94–97. [10] C. Meenderinck, C. Lageweg, S. Cotofana, Design methodology for single electron based building blocks, in: Proceedings of the 5th IEEE Conference on Nanotechnology, July 2005. [11] F. Zhang, R. Tang, Y. Kim, SET-based nano-circuit simulation and design method using HSPICE, Microelectron. J. 36 (2005) 741–748. [12] C. Lageweg, S. Cotofana, S. Vassiliadis, Buffer design trade-offs for single electron logic gates, in: Proceedings of the 5th IEEE Conference on Nanotechnology, July 2005. [13] R.H. Klunder, J. Hoekstra, Programmable logic using a SET electron box, in: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, 2001, pp. 1445–1448. [14] K.K. Likharev, Single-electron devices and their applications, Proc. IEEE 87 (1999) 606–632. [15] M.J. Sharifi, Transient response of single electron devices and their time constants, J. Korean Phys. Soc. 58 (2011) 1. [16] K. Matsumoto, M. Ishii, J. Shirakashi, K. Segawa, Y. Oka, B.J. Vartanian, J.S. Harris, Comparison of experimental and theoretical results of room temperature operated single electron transistor made by STWAFM nanooxidation process, in: Proceeding of the International Electron Device Meeting, Washington DC, 1995, pp. 363–366. [17] K. Matsumoto, STM/AFM nano-oxidation process to room-temperatureoperated single-electron transistor and other devices, Proc. IEEE 85 (1997) 4. [18] J. Shirakashi, K. Matsumoto, N. Miural, M. Konagail, Room temperature Nb/Nb oxide-based single-electron transistors, in: Proceeding of the International Electron Device Meeting, Washington DC, 1997, pp. 175–178.
Contents lists available at ScienceDirect
Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits Mohammad Javad Sharifi a,n, Davoud Bahrepour b a b
Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Velenjak, Tehran, Iran Science and Research Branch, Islamic Azad University, Tehran, Iran
a r t i c l e i n f o
a b s t r a c t
Article history: Received 15 October 2010 Received in revised form 27 January 2011 Accepted 27 April 2011
Single electron devices (SEDs) are utilized in designing many logic gates; however, in most cases the examination of the circuits is limited to a DC analysis that only indicates the correct performance of the circuits’ logic function. This paper focuses mainly on the issue of optimization. In this regard, comparison of different designs is needed, but it is not possible to compare two different designs unless they both belong to a single technology or can be scaled to a same technology. So, we first introduce a technology index for SEDs, which allows meaningful comparisons between various designs of different technologies. Then, we describe a method for scaling these designs into a single identical technology, and clarifying the relations between the involved concepts. Using two examples, we explain an optimum design method for digital logic gates based on SEDs. Finally, the results of these two examples are presented and compared with the original designs. The comparison showed that all the three major performance features, including lower bit error rate, higher operation frequency, and higher temperature operation are improved in the proposed optimized design. & 2011 Elsevier Ltd. All rights reserved.
Keywords: Optimum design procedure Technology index Single electron device Digital gate
1. Introduction
2. Technology index and scaling
Due to their ultra small dimensions and lower power consumption, single-electron devices (SEDs) are good candidates for future ULSI applications. Although they are utilized in many digital logic gates [1–7], gate operation is usually examined merely by a simple verification using SIMON [8], and optimum design procedures are either less studied or the procedures presented are incomplete [9–11] or very complex [12]. This paper aims to present a method for achieving optimum performance of SED-based digital gates by introducing a simple quality index. In Section 2, the technology concepts are discussed and a technology index for SEDs is introduced. In Section 3, we consider a NOT gate as our first example and propose a design procedure for optimum gate performance. This design procedure is based on a single index, the quality index, that characterizes the performance. The design procedure and optimum design will be repeated for a NAND gate, as the second example, in Section 4. Finally, conclusions are provided in Section 5.
For any comparison between the performances of two different designs to be valid, the first important parameter is that the two designs must be implemented in a same technology. In other words, comparison of two designs, which are implemented in two different technologies, is not valid unless the two designs are scaled into a single technology. Therefore, we need an index for SED technology.
n
Corresponding author. Tel.: þ98 9123045891; fax: þ 98 21 29902284. E-mail addresses: m_j_sharifi@sbu.ac.ir (M. Javad Sharifi), [email protected] (D. Bahrepour). 0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2011.04.014
2.1. Introducing the technology index On one hand, a good technology index should be based on real technological limitations, and on the other hand, it should also have a clear relation with the performance of the circuits that are based on that technology. A well-known technology index is the minimum feature size for MOSFET technology. This indexes MOSFET technology in an excellent fashion because it not only reveals the most important limitations of the technology but it also has a clear relation with MOSFET circuit performances. Here, regarding SEDs and the two technology index criteria mentioned above, we introduce the total capacitor of the island, CT, and the tunneling resistor, RT, as the technology index. These two parameters are related to the SEDs’ technological limitations; because CT reveals the possibility of miniaturization and RT is associated with the technology’s manufacturing tolerance, which is of growing importance. As we see later,
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these two parameters will also determine the SED circuit performances. 2.2. Scaling method Using the above-mentioned technology index, one can transfer a design from one technology to another, and a comparison of designs in different technologies would then be possible. For this purpose, the scaling factors are defined as follows: CT,new CT,old
ð1Þ
RT,new RSF9 RT,old
ð2Þ
CSF9
Fig. 1. A simple NOT gate based on a SEB [13] (Cin ¼Ct ¼ Cb ¼40 aF).
where CSF is the capacitance scaling factor, CT,new is the total capacitor in the new technology, CT,old is the total capacitor in the old technology, RSF is the tunneling resistance scaling factor, RT,new is the tunneling resistance in the new technology, and RT,old is the tunneling resistance in the old technology. For a logic circuit design consists of more than one island or tunnel junction, the total capacitance for each island and the tunneling resistance for each tunnel junction should be considered, and then the smallest total capacitance and the smallest tunneling resistance should be selected as the technology of that design. The scaling process is as follows: The capacitors and the tunneling resistors are multiplied by CSF and RSF, respectively, and the voltages are divided by CSF. By doing so, the logic function remains unchanged.
technology. There are also the following equations: VOH ¼
Vb Cb VIL Cin CT CT
ð3Þ
VOL ¼
Vb Cb VIH Cin q þ CT CT CT
ð4Þ
where q is the unit charge. Assuming the symmetry of the logic levels around zero, the equality of the input and output voltages (VOL ¼VIL,VOH ¼VIH, VIL ¼ VIH), and VOH ¼V, we have V¼
Vb Cb VCin CT CT
V ¼
Vb Cb VCin q þ CT CT CT
In this section, the concept of design procedure and optimum design along with the method of using the proposed technology index in a design procedure is discussed. Here, as an applicable example, we choose a simple NOT gate [13] since it enables us to present the details of the design computations in an easy way. This section consists of three subsections. Section 3.1 describes the design procedure and shows when the desired requirements are applied to the describing equations, a single degree of freedom remains that can be spent for optimization. Section 3.2 discusses the concept of optimum design, introduces a quality index, and presents the optimized design. In Section 3.3, the simulation results are presented. We considered both the original and the selected technologies (here after called the new technology) as well as the original and the new optimized design. On the whole, we have introduced and compared four designs including the original design in the old technology, the optimized design in the old technology, the original design in the new technology, and the optimized design in the new technology. 3.1. Design procedure A NOT gate based on a single-electron box (SEB) is introduced by Klunder [13]. In this paper, this gate is used as an applicable example because of its simple structure. Fig. 1 shows the SEB-based NOT gate. Regarding the design procedure, there are nine unknown variables to be determined in this circuit: tunnel junction capacitance and resistance (CT, RT), logic 0 and logic 1 levels in the input and output (VIL, VIH, VOL, VOH), bias voltage and bias capacitance (Vb, Cb), and input capacitance (Cin). It should be noted that in this design procedure, CT and RT are left to be determined by the selected
ð6Þ
Substituting Eq. (5) to Eq. (6) yields Vb Cb ¼
3. Calculation method for a NOT gate
ð5Þ
q 2
ð7Þ
From Eq. (7), it can be seen that Cb scales the Vb value. Therefore, depending on the limitations of having a large enough Vb, Cb can be chosen as the smallest possible. Here, Cb must be small because our main limitation, based on the selected technology, is the total capacitance, CT, which must therefore be carefully spent. Up to now, seven out of nine variables have been determined, and following equation is for the last two unknown variables (V and Cin): V¼
q VC in 2CT CT
ð8Þ
with the requirement that all capacitance values should be positive. Applying this restriction to V leads the following two inequalities (the upper bound drives from the Cin ¼0, and the lower bound from the CT ¼ 0) q q oV o 2ð2CT Cb Þ 2CT
ð9Þ
In summary, four assumptions are made: predefined CT and RT, identical input and output logic levels, the symmetry of logic levels around zero, and a selected value for Vb. These assumptions are applied to satisfy this paper’s design procedure, and one degree of freedom still remains that can be used for design optimization. 3.2. Optimum performance design An optimum logic design usually has three main characteristics: (i) small physical dimensions (i.e., occupying the smallest possible area on the chip), (ii) low power consumption, and (iii) high-speed switching. By carefully considering these measures, it is obvious that the first one is fixed by the selection of the SED technology because a smaller CT means a smaller size, and vice versa. Regarding the second measure, it should be noted that
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it is also fixed by the selection of the SED technology because the energy dissipation of SEDs in a logic transition is only a function of CT (equal to e2/CT). Moreover, the power consumption in SEDs is extremely low and, in fact, does not require any optimization. For instance, in a SED circuit with CT ¼1 aF, energy consumption is 2.56 10 20 J (power consumption¼256 pW for 10 GHz clock frequency) and can be ignored. Therefore, there is no need to further consider these two measures and it can be concluded that optimization in SED-based circuits is related only to switching speed. Thus our goal is to determine the circuit elements and logic levels for the inputs and outputs to achieve the highest possible speed. However, the concept of speed in SEDs is slightly different from that in classical devices, which is discussed in the following. In the orthodox theory, which is the basic theory for SEDs, an electron’s transit time through a tunneling barrier is assumed to be zero [14]. Hence what remains from the time behavior is the tunneling time latency, which is a random time an electron waits behind a tunneling barrier before crossing. The probability density function of this waiting time has an exponential form. Consequently, if one waits any length of time, there is still a nonzero probability that the electron tunneling does not tunnel, and hence, no logic output is established. In this way, a bit error in the logic gate output is caused by the random time of transfer through a tunneling barrier. This error is a function of clock frequency, and increasing the clock frequency increases the bit error rate (BER). Besides the clock frequency, temperature can also cause errors, in that an electron without having received a command from the input can tunnel from a tunneling barrier by only obtaining energy from the environment. If TFE is the total error rate, we have TFE ¼ TE þFE
TEpeðqðVT VÞÞ=KB T
ð11Þ
FEpeGtp ¼ eG=F ¼ eððVT VÞÞ=qRt F
ð12Þ
where KB is the Boltzmann constant, T is absolute temperature, G is the tunneling rate at 0 K, tp is the clock period, F is the clock frequency, and V is the tunnel junction voltage described in Eq. (8). As seen from Eqs. (11) and (12), both the error terms are related to the V term, and this issue leads us to define a design quality index, DQ, as ð13Þ
The variable DQ is a unique quality index because it affects both error terms mentioned in Eqs. (11) and (12). In addition, note that DQ is dimensionless; hence, it is independent of SED technology, and therefore the results of an optimization process based on this index will be independent of the technology as well. This means that any circuit optimized with this method remains optimized in all technologies. By using Eq. (8), DQ is equal to DQ ¼
Cin CT þ Cin
CT Cb 2CT Cb
DQ 2Rt CT lnðTFEÞjT ¼ 0
ð16Þ
Tmax ¼
DQq2 2KB CT lnðTFEÞjF ¼ 0
ð17Þ
From Eqs. (16) and (17), we can find the scaling rules for Fmax and Tmax Fmaxnew ¼
Fmaxold CSF RSF
ð18Þ
Tmaxnew ¼
Tmaxold CSF
ð19Þ
These two formulas complete the set of scaling rules for the SED technology. We may conclude that: 1. Fmax and Tmax are linear functions of DQ; hence, they are optimized identically by DQ 2. Fmaxnew is a function of two technology parameters, i.e., reduction in dimensions and reduction in tolerance; decreasing CT and RT (up to its quantum limitation value, 25.8 KO) lead to a better Fmax. 3. Tmaxnew is only a function of CSF and therefore it improves only by shrinking the dimensions
3.3. Results and discussion This section compares four different versions of the NOT gate: (a) The original design in the old technology (mentioned in [13]). In this case, CT was equal to 120 aF and the RT value was not stated, which we consider it equal to 1 MO. (b) The optimized design in the old technology, where the technology is the same as (a) (i.e., CT ¼120 aF, RT ¼1 MO) but the circuit is redesigned according to the method introduced in this paper (with DQ ¼0.44); (c) The original design in the new technology, which is the same as (a), except that all the parameters are scaled to a new technology using Eqs. (1) and (2). Although we assumed CT ¼1 aF and RT ¼1 MO for the new technology, they are completely arbitrary. These values are not inaccessible in the current SED technology and have been used in some physical implementations [16–18]. Using this technology, CSF and RSF will be equal to 1/120 and 1, respectively. Table 1 Circuit parameters for the NOT gate using different designs. Parameter Old design in old technology [13]
Optimized design in old technology
Old design in Optimized design in new new technology technology
CT (aF) Cin (aF) Ct (aF) Cb (aF) RT (MO) VIL (mV) VIH (mV) VOL (mV) VOH (mV) Vb
120 96 12 12 1 0.36 0.36 0.36 0.36 6.66 mV
1 0.33 0.33 0.33 1 12 12 76 76 240 mV
ð14Þ
From the inequalities in Eq. (9), the quality index, DQ, is limited as 0 o DQ o
Fmax ¼
ð10Þ
where TE is the error caused by temperature and FE is the error caused by the frequency. Both terms are exponential functions of the distance between the applied voltage (across the tunnel junction) and the tunneling threshold voltage VT ¼ q=2CT [15]:
DQ ¼ ðVT VÞ=VT
Considering a specific TFE, a maximum frequency, Fmax, and a maximum temperature, Tmax, can be defined from the above mentioned equations. Fmax is the maximum frequency for a given TFE when the temperature is zero while Tmax is the maximum temperature for a given TFE when the frequency is equal to zero.
ð15Þ
As a practical value, we choose DQ¼ 0.44 (therefore Cin ¼ 0.8CT) and present its results as the optimized NOT gate design in the following subsection.
120 40 40 40 1 0.1 0.1 0.63 0.63 2 mV
1 0.8 0.1 0.1 1 44 44 44 44 0.8 V
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Fig. 2. Simulation results of the NOT gate using SIMON: (a) the original design in the old technology (mentioned in [13]), (b) the optimized design in the old technology, (c) the original design in the new technology, and (d) the optimized design in the new technology (see Table 1 for parameters of each design).
Fig. 3. Time-transient behavior for the output of the NOT gate when it switches from logic 1 to logic 0 for (a) the original design in the old technology (with CT ¼ 120 aF and RT ¼ 1 MO), (b) the optimized design in the old technology (with CT ¼120 aF, RT ¼1 MO, and DQ ¼ 0.44), (c) the original design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO), and (d) the optimized design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO and DQ ¼0.44). As seen, after changing the technology, the switching speed becomes 120 times faster, and after optimization it again increases 11 times. The circuit parameters are shown in Table 1.
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(d) The optimized design in the new technology, where the circuit is redesigned and also scaled to the new technology (i.e., CT ¼1 aF, RT ¼1 MO with DQ ¼0.44).
Table 1 shows the circuit parameters for the above four versions. It should be noted that, in scaling, the logic function does not change, whereas performance changes significantly. Fig. 2 shows the simulation results of the NOT gate before and after scaling and also with and without optimization by utilizing SIMON in order to verify DC operation. Fig. 3 depicts the switching behavior for the logic 1 to logic 0 transition for above mentioned designs. It is obvious that using a better technology reduces the delay time by about 120 times. In addition, we see that in the optimized design, the speed again increases by about 11 times (the total speed in the d version increases by 1320 times in comparison with the total speed in the a version). Fig. 4 shows the curves of constant error in the frequency– temperature plane for different specific BERs. In the other words, it shows the performance of the designs in terms of error, frequency, and temperature. The curves show in what frequency– temperature combination, the gate can operate as long as the total error rate does not exceed the specified value. As expected, all the curves in Fig. 4 are descending, which means that
increasing the temperature in a specific BER decreases the operating frequency and, vice versa. However, the typical semisquared shape of the curves, especially for small BERs, means that both the maximum frequency, Fmax, and the maximum temperature, Tmax, are achievable almost simultaneously, and, of course, both performances are scaled with the specified total BER value. As seen in Fig. 4, for a specific BER, such as BER¼0.001, the maximum operating frequency and maximum operating temperature
Fig. 5. A two-input NAND gate based on a SEB [13] (Cin ¼Ct ¼Cb ¼40 aF).
Fig. 4. The NOT gate operating frequency variation curves at different temperatures for different BERs: (a) The original design in the old technology (with CT ¼ 120 aF and RT ¼ 1 MO), (b) the optimized design in the old technology (with CT ¼120 aF, RT ¼1 MO, and DQ ¼ 0.44), (c) the original design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO), and (d) the optimized design in the new technology (with CT ¼1 aF, RT ¼ 1 MO, and DQ ¼0.44).
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pair, (Fmax, Tmax) corresponding to designs (a)–(d) is (0.022 GHz, 0.042 K), (0.26 GHz, 0.49 K), (2.8 GHz, 5.3 K), and (32 GHz, 59 K), respectively. Again we conclude that both optimization and technology have a significant effect on the gate performance. Table 2 The temperature and frequency error probability relations for four different transitions. Transitions
TE
FE
00-11 01,10-11 11-00 11-01,10
eðqðVT Vo00ÞÞ=KT ¼ eðqðVT Vð12ðCin =CT ÞÞÞÞ=KT eðqðVT VÞÞ=KT eðqðVT VÞÞ=KT eðqðVT VÞÞ=KT
eððVT VÞÞ=qRT F eððVT VÞÞ=qRT F eððVT Vð12ðCin =CT ÞÞÞÞ=qRT F eððVT VÞÞ=qRT F
Table 3 Circuit parameters for the NAND gate: four implementations. Parameter Original design Optimized design in old in old technology technology [13]
Optimized Original design in new design in new technology technology
CT (aF) Cin (aF) Ct (aF) Cb (aF) RT (MO) VIL (mV) VIH (mV) Vo 00 (mV) Vo 01 (mV) Vo 11 (mV) Vb (mV)
160 40 40 40 Not specified 0.1 0.1 Not specified
160 57.6 28.8 16 1 0.365 0.365 0.1
1 0.25 0.25 0.25 1 16 16 68
1 0.36 0.18 0.1 1 58.4 58.4 16.35
Not specified
0.365
76
58.4
Not specified
0.365
76
58.4
1.9
3.65
304
584
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4. Optimum design for NAND gate As the second example, we choose another gate in order to demonstrate our optimum design procedure. Fig. 5 shows the new SEB based structure [13]. It is able to implement both NAND and NOR functions by applying appropriate voltages to the Vb. We choose this structure for implementing NAND function. It should be mentioned that computing the optimum design procedure for a NOR function will be the same. In the NAND structure, when the inputs are in 00 or 01state, electrons cannot tunnel through the tunnel junction; hence, the output will remain in high state. When inputs are in the 11 state, the voltage across the tunnel junction exceeds the threshold value. Consequently, one electron tunnels through the tunnel junction which leads to a negative voltage at the island, i.e. low output state. Here again, we will present an optimum design procedure for this circuit and also compare our results with the original one [13] with respect to the performance. The unknown variables for the NAND circuit are VinL, VinH, Vb, Cb, Cin, Ct, RT, Vo 00,Vo 01 and Vo 11 where Vo 00,Vo 01 and Vo 11 are output voltage when the inputs are in 00, 01, and, 11 states, respectively, and the other parameters are the same as the previous example (see also Fig. 5). First of all, the following relations are considered as some of the design requirements. VinL ¼ VinH ¼ V
ð20Þ
Vo01 ¼ V
ð21Þ
Vo11 ¼ V
ð22Þ
Hence, similar to previous section, three unknown variables are obtained. There are also the following equations, which calculate output voltage for different input combinations. Vo00 ¼
Cb Vb 2VCin CT CT
ð23Þ
Fig. 6. Simulation results of the NAND gate using SIMON: (a) the original design in the old technology (the original paper [13]), (b) the optimized design in the old technology, (c) the original design in the new technology, and (d) the optimized design in the new technology (see Table 2 for parameters of each design).
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Vo01 ¼ Vo10 ¼
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Cb Vb ¼V CT
ð24Þ
calculated by TFE ¼
C V 2VCin q ¼ V Vo11 ¼ b b þ CT CT CT
ð25Þ
In these equations Vb and Cb are always appear in a product form, thus, as previous, we can say that Vb scales Cb and we can choose Cb by considering the requirements of Vb. Again as previous, both RT and CT, (here CT ¼2Cin þCb þCt) are determined by the selected technology. Now, four unknown variables and three equations remain, and so, we have one degree of freedom that can be spent for optimization. In summary, we first had ten unknown variables and after applying the design requirements, choosing the desired value for Vb, and selecting the desired technology, a single parameter (say, V) remains, which now we are going to adjust it so that it optimizes the circuit performance. Again the performance is considered as minimum gate error, and other characteristics such as minimum area occupation and small power consumption are ignored based on the reasons stated previously. For each two-input gate, there are twelve possible transitions. The temperature fluctuations and/or the speed limitations can cause error transitions. Therefore the total mean error, TFE, is
12 1 X TE þ FEi 16 i ¼ 1 i
ð26Þ
where TEi and FEi are the temperature and the frequency errors for the ith possible transition, respectively. In a NAND gate, only six out of the twelve input combinations lead to a transition at the output and only four of them (namely 00–11, 01–11, 11–00, 11–01) are distinguishable due to the symmetry. The temperature and frequency error probabilities for these four transitions are illustrated in Table 2. Two of the error factors demonstrated in Table 2 are very small compared to others and can be ignored (00-11 for TE and 11-00 for FE). After eliminating these two errors, one can see that the remaining errors are a function of VT V. Now similar to the previous section, a dimensionless quality factor is introduced as DQ ¼
VT V VT
ð27Þ
The dimensionless feature of DQ ensures us that the optimization process will be independent of the selected technology. In other words, when a design is optimum in one technology it will be optimum in all other technologies. The lower bound of DQ is equal to zero (for V¼VT) and the upper bound is achieved by
Fig. 7. NAND gate operating frequency variation curves at different temperatures for different BERs: (a) the original design in the old technology (with CT ¼ 120 aF and RT ¼ 1 MO), (b) the optimized design in the old technology (with CT ¼120 aF, RT ¼1 MO, and DQ ¼ 0.27), (c) the original design in the new technology (with CT ¼ 1 aF and RT ¼ 1 MO), and (d) the optimized design in the new technology (with CT ¼1 aF, RT ¼ 1 MO and DQ ¼0.27).
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this assumption that Vo–00 should not be smaller than zero. By applying this condition (i.e., Vo 00 ¼0) to Eqs. (23) and (24), the upper bound of DQ is found to be equal to 0.33 (achieved when Cin ¼CT/2). In following we introduce the optimum design for the NAND gate with DQ ¼0.27. Table 3 shows the circuit parameters for four versions of the NAND gate. Fig. 6 shows the simulation results of the NAND gate for the four versions (before and after scaling; with and without optimization) by utilizing SIMON to verify the DC operation. Fig. 7, which is the same as Fig. 4, shows the frequency and temperature curves in different BERs for these four versions of NAND gate. Again, Fmax and Tmax are achieved from Eqs. (16) and (17), respectively. As seen in Fig. 7 for a specific BER, such as BER¼0.0001, the maximum operating frequency and maximum operating temperature pair, (Fmax, Tmax) corresponding to designs (a)–(d) is equal to (15 MHz, 38 mK), (2.42 GHz, 6.15 K), (81 MHz, 207 mK), and (13.1 GHz, 33.2 K), respectively. This figure shows that, by scaling the original design into the new technology, the performance increases 160 times and by optimizing the scaled design, the performance further increases about 5.4 times, which totally means 864 times better performance.
5. Conclusions In this paper, the concept of technology index for SEDs and a method for technology scaling is introduced for the first time. In addition, this paper discussed in detail the design procedure for a sample NOT gate based on SEB and introduced a design quality index, DQ, and also clarified its limitations. Then, using the DQ index, we presented an optimum design procedure. We then calculated the performance of the optimized design for the NOT gate and compared it with the original design in terms of the maximum operating frequency and the maximum operating temperature for a constant total BERs. Then, we chose a SEB based NAND gate as the second example. The proposed optimum design procedure was repeated in order to introduce the performance measures. The simulation results for the NOT and NAND gates illustrated that the frequency– temperature curves have semi-squared shapes; hence, both the maximum frequency and the maximum temperature are approximately achievable simultaneously. This finding is another of this paper’s contributions. Simulation results of the NOT and the NAND gates showed that utilizing the new technology will improve the performance by 120 and 160 times, respectively. Utilizing the optimum design will lead to additional 11 and 5.4 times better
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performance (1320 times and 864 times, totally, respectively). We showed that the design procedure and calculation methods are very similar for NOT and NAND gates. In fact, the proposed concepts are quite general and can be applied to almost all SED structures and designs. References [1] H. Iwamura, M. Akazawa, Y. Amemiya, Single electron majority logic circuits, IEICE Trans. Electron. E81-C (1) (1998) 42–46. [2] M.M. Dasigenis, I. Karafyllidis, A. Thanailakis, A single-electron XOR gate, Microelectron. J. 32 (2001) 117–119. [3] T.Y. Ono, A. Fujiwara, H. Inokawa, Silicon single-electron devices for logic applications, in: Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), May 2000, pp. 411–420. [4] Y. Takahashi, Y. Ono, A. Fujiwara, H. Inokawa, Multigate single-electron transistors and their application to an exclusive-OR gate, Appl. Phys. Lett. 76 (2000) 637–639. [5] T. Oya, T. Asai, T. Fukui, Y. Amemiya, A majority logic device using an irreversible single-electron box, IEEE Trans. Nanotechnol. 2 (2) (2003) 15–22. [6] S.E. Rehan, A novel half-adder using single electron tunneling technology, in: Proceedings of the 2nd IEEE International Conference on Nano/Micro Engineered and Molecular Systems, Bangkok, January 2007, pp. 245–249. [7] G.T. Zardalidis, I. Karafyllidis, A single electron half-adder, Microelectron. J. 33 (2002) 265–269. [8] C. Wasshuber, H. Kosina, S. Selberherr, SIMON—a simulator for singleelectron tunnel devices and circuits, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 16 (1997) 937–944. [9] G.T. Zardalidis, I. Karafyllidis, Design and simulation of a nanoelectronic single-electron control—NOT gate, Microelectron. J. 37 (2006) 94–97. [10] C. Meenderinck, C. Lageweg, S. Cotofana, Design methodology for single electron based building blocks, in: Proceedings of the 5th IEEE Conference on Nanotechnology, July 2005. [11] F. Zhang, R. Tang, Y. Kim, SET-based nano-circuit simulation and design method using HSPICE, Microelectron. J. 36 (2005) 741–748. [12] C. Lageweg, S. Cotofana, S. Vassiliadis, Buffer design trade-offs for single electron logic gates, in: Proceedings of the 5th IEEE Conference on Nanotechnology, July 2005. [13] R.H. Klunder, J. Hoekstra, Programmable logic using a SET electron box, in: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, vol. 1, 2001, pp. 1445–1448. [14] K.K. Likharev, Single-electron devices and their applications, Proc. IEEE 87 (1999) 606–632. [15] M.J. Sharifi, Transient response of single electron devices and their time constants, J. Korean Phys. Soc. 58 (2011) 1. [16] K. Matsumoto, M. Ishii, J. Shirakashi, K. Segawa, Y. Oka, B.J. Vartanian, J.S. Harris, Comparison of experimental and theoretical results of room temperature operated single electron transistor made by STWAFM nanooxidation process, in: Proceeding of the International Electron Device Meeting, Washington DC, 1995, pp. 363–366. [17] K. Matsumoto, STM/AFM nano-oxidation process to room-temperatureoperated single-electron transistor and other devices, Proc. IEEE 85 (1997) 4. [18] J. Shirakashi, K. Matsumoto, N. Miural, M. Konagail, Room temperature Nb/Nb oxide-based single-electron transistors, in: Proceeding of the International Electron Device Meeting, Washington DC, 1997, pp. 175–178.