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Investigation of high performance Edge Lifted Capacitors reliability for GaAs and GaN MMIC technology
Microelectronics Reliability 54 (2014) 2697–2703
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Investigation of high performance Edge Lifted Capacitors reliability for GaAs and GaN MMIC technology Ming-Hung Weng a,b,⇑, Chao-Hung Chen a, Che-Kai Lin a, Shih-Hui Huang a, Jhih-Han Du a, Sheng-Wen Peng a, Walter Wohlmuth a, Frank Yung-Shi Chou a, Chang-Hwang Hua a a b
WIN Semiconductors Corp., No. 35, Technology 7th Road, Hwaya Technology Park, Kuei Shan Hsiang, Tao Yuan Shien 333, Taiwan Current address: School of Electrical and Electronic Engineering, Newcastle University, Newcastle, NE1 7RU, UK
a r t i c l e
i n f o
Article history: Received 7 July 2014 Received in revised form 16 September 2014 Accepted 19 September 2014 Available online 20 November 2014 Keywords: ELC MIM Refractive index TDDB ESD bHAST
a b s t r a c t This paper reports extensive investigations of Edge Lifted Capacitors (ELC) and standard metal–insulator– metal (MIM) capacitors with different refractive index and thickness of Silicon Nitride (Si3N4) dielectric films. The wafer-level electrical measurements reveal size dependence of capacitances and breakdown voltages. Physical characterization was performed using Fourier transform infrared spectroscopy (FTIR) to understand intrinsic properties of the studied films and failure-related cross sections were used to predict possible leakage mechanisms. Reliability testing of Human Body Model (HBM) and Machine Model (MM) electrostatic discharge (ESD), time-dependent dielectric breakdown (TDDB), and biased high temperature accelerated stress testing (bHAST) were performed and will be reviewed for GaAs and GaN monolithic microwave integrated circuit (MMIC) applications. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction In recent years, foundry services for GaN HEMTs on SiC devices [1–4] have gained remarkable attention due to the device’s potential to revolutionize power and radio frequency (RF) electronics with predictions that the overall commercial and military markets will be multi-billion dollar markets by 2020 [5]. The move to high efficiency, low power consumption RF amplifier building blocks is seen to increase the GaN-based component demand. Since GaN HEMTs are operated at high voltage, passive components such as capacitors are also required to tolerate high voltages during circuit operation. GaN RF transistors typically operate at 28 to 50V and subsequently require capacitors, within the circuit, to withstand blocking voltages of > 200 V without damage [6–9]. The Silicon Nitride (Si3N4) dielectric film can be optimized by changing the Si3N4 composition and film stress using multi-layer plasmaenhanced chemical vapour deposition (PECVD) processes. The breakdown voltage is highly correlated to the electric field intensity within the capacitor dielectric. Therefore, a new Metal Insulator Metal (MIM) capacitor structure termed the Edge Lifted Capacitor (ELC) was developed. The high electric field around the
⇑ Corresponding author. http://dx.doi.org/10.1016/j.microrel.2014.09.023 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
capacitor periphery is effectively relieved in the ELC and thus the breakdown performance is significantly enhanced.
2. Devices structure and experiments Capacitor fabrication starts with Metal1 as the bottom metal layer and Metal2 as the contact metal layer as shown in Fig. 1. A SPAN layer is formed to provide mechanical and structural support for the air bridge to minimize the parasitic capacitance. The overlay distance between SPAN and Metal1 creates desirable lifted metal edges of Metal2. In order to achieve high breakdown (VBD) and simultaneously have high specific capacitance (CP), the use of different capacitor arrays, ranging from 200 to 3.5 105 lm2, and various Si3N4 stoichiometric film properties with refractive index (R.I.), ranging from 1.9 to 2.1, were used and compared. 123 different sites were characterized for each 100 mm wafer. Table 1 shows a summary of Si3N4 thickness and refractive index used in the experiments. A total of five Si3N4 films have been studied with a 150 nm thick dielectric film used for Film_1 to Film_3 and a 300 nm thick dielectric film used for Film_4 and Film_5. The reference films, the process of record (POR) films, were also compared in this study. The difference in material properties of SiC substrates, such as transparency and higher thermal conductivity (300 W m 1 K 1 in SiC)
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Fig. 1. Schematic cross section of an Edge Lifted Capacitor (ELC).
Table 1 Summary table of Si3N4 thickness and refractive index. Film
Thickness (nm)
R.I.
1 2 3 4 5 Ref. POR1 Ref. POR2
150 150 150 300 300 150 150
2.1 2.0 1.9 2.0 1.9 1.95 2.0
as compared to GaAs substrates requires optimization of the Si3N4 film growth conditions. The flow rate, power, pressure and NH3:SiH4 ratio in the deposition process was varied resulting in different Si–N bond density and dielectric film refractive index. The bonding configurations within the film were examined by Fourier Transform Infrared Spectroscopy (FTIR). Before deposition of the Si3N4 film for the capacitor, a 200 nm thick Si3N4 film was deposited over the whole wafer isolating the substrate from the capacitor preventing leakage paths from contact pads to the substrate. Wafer-level electrical tests were performed using an Agilent 4072 high power supply with a Precio Octo auto prober. A voltage and current compliance of 200 V and 100 lA, respectively, is used to prevent probe melt-down. The intrinsic and
extrinsic breakdown mechanisms are also characterized and fit to the Frenkel–Poole equation. The reliability performance testing included: human-body-model (HBM) and machine-model (MM) electrostatic discharge (ESD) [10], time-dependent dielectric breakdown (TDDB) [11], and biased high temperature accelerated stress (bHAST) [12] following JEDEC standards and guidelines to verify the reliability of the ELC capacitors. Finally, the capacitor geometry scaling is modelled using Advanced Design System (ADS). 3. Measurement results and discussion Fig. 2 shows cross-sectional comparisons of the conventional MIM and the ELC designs. The conventional MIM design features a metal skirt which unintentionally results in a leakage path due to possible metal migration and concentrated electrical field. The ELC, on the other hand, provides a more robust capacitor, better leakage uniformity, and a 10 to 20% enhancement in the leakage behavior. This advantage is observed in the electrical characterization comparison between the MIM capacitors and the ELC with 1500 Å thick silicon nitride layers are manufactured with the SiH4/NH3 gas ratio (R = 0.65) and R.I. = 2 as shown in Fig. 3. These capacitors electrical characterization summarizes the leakage at the compliance current of 100 lA. As can be seen, the weak leakage
Fig. 2. SEM cross-section and side views of the ELC and MIM capacitors.
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Fig. 3. Breakdown performance comparisons of ELC and MIM capacitors.
Fig. 4. Leakage comparison of the capacitor array with total Si3N4 thickness of 200 nm using single and double step deposition. The VBD reached the 200 V compliance limit of the test system for the 30 60 lm2 ELC using the double step deposition.
characteristics of these two capacitors design significantly decreased, when the capacitor area was increased due to larger metal area the level of defects and roughness can be increased [13]. The ELC exhibits better uniformity and higher capacitance in comparison to the MIM capacitor. The metal skirts which cause early failure in MIM capacitors are only revealed in cross-section images and are difficult to observe during visual microscope inspection. Fig. 4 compares leakage performance versus an array of various sized capacitors with single and double step PECVD Si3N4 deposition. The multi-layer Si3N4 film was reported to exhibit lower leakage current and higher dielectric breakdown voltage [14]. The double step film can also have a reduction of pinholes density [15], different glass transition temperature and different optical properties [16]. In this study, the dielectric constants are determined to be 6.57 for the double step film deposition, and a slightly lower value of 6.15 for the single step film deposition which is comparable to previously reported Si3N4 dielectric constants in literature [15]. The improvement in leakage behavior with a double step versus a single step deposition was determined to be minimal in this paper as an average increase of only 5–6 V in VBD was extracted across the capacitor array. Fig. 5 shows the normalized capacitance per unit area of the fabricated Si3N4 films. The capacitor size increases from left to right for each grouping from 200 to 3.5 105 lm2. An alternative process for better leakage behavior capacitors is also available for Film_5 and Film_6 with an averaged CP at 160 pF/mm2. The higher
Fig. 5. Normalized capacitance to area and film comparison. Each box plot contains 123 test points. The horizontal red lines show normalized capacitance of 160 and 320 pF/mm2. The largest ELC is shown in the uppermost right-hand side of each group, with an area of 3.5 105 lm2. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
capacitance values extracted in Film_1 were confirmed to not be related to the physical thickness variation of the films as determined by scanning electron microscopy (SEM) cross-sections (images not shown). The summary of dielectric breakdown is illustrated in Fig. 6 where each box plot represents 123 tested capacitors across a wafer. The three groups of 150 nm thick Si3N4 films indicate a significant improvement of 50 V for VBD from comparing Film_1 to Film_3. In addition, a remarkable blocking voltage is achieved in Film_5 showing that the robustness of this process has achieved VBD beyond the testing tool limitation of 200 V at an estimated breakdown between 265 and 330 V by Keithley 2657 A manual measurement. It is noticeable in both the VBD and CP plots that the smaller capacitors have different average values in comparison to the larger capacitors. Fig. 7 illustrates potential issues that cause this difference. As the ELC is scaled down in size, the parasitic contribution from the ELC edge becomes significant. The parasitic capacitance is attributable to the edge-lifted under-side, air bridges, inter-connects and probe pads. The considerable peripheral to effective dielectric areas aspect ratio in the capacitors are
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Fig. 6. Leakage VBD plots with current sourced at 100 lA and voltage compliance of 210 V. Each box plot contains 123 test points. The 150 nm films are grouped in squares. The capacitor sizes, for each film, increases from left to right. The dashed arrows show the box plots of capacitors with the same area size of capacitor for Films 1, 2 and 3.
Fig. 8. FTIR spectra overlay of the various Si3N4 films.
Table 2 FTIR averaged integrated band intensities in the various films. Film property
Absorption Ref. POR1 Ref. POR2 Film 1 peaks (cm 1)
R.I. N–H 3350 Si–H 2150 NH/SiH ratio
1.95 0.403 0.415 0.971
2 0.310 0.323 0.958
2.1 0.0237 0.0459 0.5174
Film 2 Film 3 2 0.110 0.126 0.873
1.9 0.222 0.235 0.947
Fig. 7. Capacitance and size dependence in the capacitor arrays. The insets with the graphs show measured (not normalized) capacitance and one of the smallest capacitors with minimum effective capacitor area.
calculated to be as high as 247:1 among small capacitors and 1:6 for the larger capacitors presented. Fig. 8 and Table 2, together, show the intrinsic Si3N4 film properties determined by FTIR. As shown in Table 2, the peaks at 2150 and 3350 cm 1 can be attributed to the Si–H and the N–H bond absorptions [17], respectively. Film_3 exhibits higher N–H and Si–H bond concentrations and higher N–H to Si–H ratio FTIR peaks than Film_1 and Film_2. Film_1 suffers poor leakage characteristics and contains lower Si–H and N–H bonds, than the other films from the FTIR bond absorption peaks. Reference films POR1 and POR2 (Ref. POR1 and Ref. POR2) are the proven high quality Si3N4 films used in the production GaAs ELC technology and were chosen as the baseline for GaN ELC. According to FTIR analysis and the leakage performance results, Film_3 has similar NH to SiH ratio in comparison to the Ref. POR1 and Ref. POR2 films and therefore has been used as film of choice for the GaN technologies. GaN transistor with field-plate is disposed between the gate and drain, so tha and an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current. In order to understand the basic behavior of the tested Si3N4 dielectric layers, the field plate to gate capacitor’s leakage characteristics for the three different Si3N4 films have been
Fig. 9. MIM capacitor leakage behavior in GaN technology with different Si3N4 R.I.
recorded. As can be seen in Fig. 9, the three Si3N4 films exhibit quite different leakage current behavior. The field plate to gate capacitor with Film_1 shows the highest leakage current. The field plate to gate capacitor with Film_3 exhibits the lowest leakage current behavior of all three Si3N4 types. A leakage stress analysis reveals that higher R.I. Si3N4 films with lower NH3/SiH4 ratio showed poorer leakage performance. Time Dependent Dielectric Breakdown characterization at 125 °C is done to verify the lifetime of the capacitors. Fig. 10 compares the standard MIM capacitor and the ELC in GaAs MMIC technology. The required operating and breakdown voltages are different for the GaAs capacitors in comparison to the GaN capacitors, however, both MIM capacitor and ELC achieve above 100 V operation but the TDDB lifetime of the ELC at 20 V is at about 2 orders of magnitude greater than the minimum requirement of
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Fig. 10. (a) TDDB comparison of MIM capacitor and ELC. (b) Distinguishable failures on the edges and non-edges are observed.
Fig. 11. TDDB performance of the ELC in GaN technology with 230 nm Si3N4 film thickness.
20 years (6.3 108 s) under 100 200 lm2 capacitor size. The breakdown fields are calculated at 6.67 MV/cm and 7.0 MV/cm for the MIM capacitor and the ELC, respectively. The failure modes for the MIM capacitor are significantly different from the ELC. In the ELC, failures occur randomly within the capacitor and appear as Si3N4 film punch-through; whilst in the MIM capacitors the failures are mostly located on the edge of the capacitor in the vicinity of the metal skirts and the highly concentrated electrical field. Fig. 11 shows the TDDB performance in the GaN technology. A capacitor breakdown voltage of between 210 and 260 V indicates
a maximum electrical field of 11.3 MV/cm. A blocking voltage in excess of 100 V is found to have 20 years lifetime. GaN MMICs amplifier operation in class E or F can generate voltages in excess of 3 times the operating voltage necessitating the need for close to 100 V breakdown capacitors for 28 V transistor operation. The graph also shows that there is no influence of substrate thickness on the GaN ELC performance when comparing bulk (500 lm) and thinned (100 lm) substrates. Electrostatic discharge (ESD) has been known to be one of the major causes of yield and reliability failures in IC manufacturing. In this study, the ESD characteristics of MIM and ELC capacitors have been investigated using both Human Body Model (HBM) and Machine Model (MM) testing. As shown in Fig. 12, a direct comparison of MM and HBM was performed on the GaAs MIM capacitor and ELC with two dimension types (type1: 200 200 lm2, type2: 450 900 lm2). As expected, the ESD voltage of the MIM capacitor and the ELC show some dependence on the capacitor area, where the ESD voltage increases with increasing capacitor area. It is clear that there is no significant difference in ESD performance between the capacitors. Biased HAST (bHAST) testing is used to evaluate the ability of electronic components to resist moisture ingress. To evaluate the impact of moisture ingress on the GaAs MIM capacitor and ELC, a 70 140 lm MIM capacitor and ELC were employed for the dielevel bHAST tests. These capacitors are then exposed to JEDEC standard bHAST test conditions, which are a temperature of 130 °C, 85% relative humidity and 33.3 psi of pressure for a period of 96 h under 8 V bias in the case of GaAs transistors used in this study. Fig. 13 shows the appearance and yield loss after bHAST results
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Fig. 12. (a) Human body model mode and (b) machine model mode ESD comparison graph for GaAs MIM capacitors and ELCs.
for both the MIM capacitor and the ELC. The ELC shows significantly enhanced moisture resistance and better yield after bHAST testing in comparison to the MIM capacitor. After bHAST inspection of the failed MIM capacitors, it was revealed that the failures were mainly observed near the edge of the devices in the vicinity of the metal skirts. Fig. 14 shows good matching between the modeled and measured data. The design rules of the ELC are completed and this capacitor structure is released as the preferable option in the design kit for foundry customers in the GaAs and GaN technologies. A less than 5% error between measured and modeled data is confirmed for ELCs ranging from 50 50 lm2 to 200 200 lm2. 4. Conclusion
Fig. 13. Image of ELC and MIM capacitors plus summary table of yield loss after bHAST test.
An effective and highly manufacturable process for improving the breakdown voltage, leakage behavior uniformity, and average specific capacitance is reported with high quality Si3N4 films and
Fig. 14. Measured data (red line) and modeled (blue line) of selected GaN ELC. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
M.-H. Weng et al. / Microelectronics Reliability 54 (2014) 2697–2703
novel ELC design for GaAs and GaN MMIC applications. The ELC is designed to eliminate the high electrical field associated with metal skirts that exist in MIM capacitors and to improve quality control. Quality control is improved by eliminating the metal skirts which are difficult to detect during visual microscopy inspection. The use of Si3N4 films with low refractive index for the capacitors further improves the reliability. The size dependence performance of VBD and CP for the ELCs was confirmed with wafer level measurements. Small capacitors were reported for scientific study only, as the high parasitic capacitance prevents accurate modeling and therefore limited applicability in MMIC design. The comparisons of ESD, TDDB and bHAST of both MIM and ELC designs were presented. A comprehensive model and PDK have been created for the ELC providing designers and customers a highly reliable and uniform capacitor for use in advanced high power and high frequency GaAs and GaN MMIC technology enabling new markets and applications. Acknowledgements The authors would like to thank all the members who support the GaAs and GaN technology development in WIN Semiconductors including the teams from: the Testing, Device Characterization and Model; and the Process and Manufacturing groups. Recognition of support and help is also given to J.H Lin, Nicole Lin, Y.H. Shih, S.Y. Wan and Carol Chen from the Testing, Failure Analysis and Quality Control teams. References [1] Weng MH, Lin CK, Du JH, Wang WC, Wang WK, Wohlmuth W. Pure play GaN foundry 0.25 lm HEMT TECHNOLOGY for RF applications. In: IEEE CSIC symposium, Monterey California, USA, Oct 2013.
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[2] Wohlmuth W, Weng MH, Lin CK, Du JH, Ho SY, Chou TY, et al. AlGaN/GaN HEMT development targeted for X-band applications. In: IEEE COMCAS, Israel, Oct 2013. [3] Wang WC, Chen CH, Du JH, Weng MH, Lin CK, Huang CC, et al. Development and control of a 0.25 lm gate process module for AlGaN/GaN HEMT Production. In: CS MANTECH conference, New Orleans, Louisiana, USA, May 2013. [4] van der Wel PJ, de Beer JR, van Boxtel RJM, Hsieh YY, Wang YC. Reliability assessment of extrinsic defects in sinx metal–insulator–metal capacitors. In: Reliability of compound semiconductors workshop, San Antonio, Texas, November 2006. p. 35–40. [5] Hindle P. Future RF market opportunities for GaN. Microw J 2012;55(6):22–4. [6] Pengelly RS, Wood SM, Milligan JW, Sheppard ST, Pribble WL. A review of GaN on SiC high electron-mobility power transistors and MMICs. IEEE Trans Microw Theory Tech 2012;60(6). [7] Wu Y-F, Saxler A, Moore M, Smith RP, Sheppard S, Chavarkar PM, et al. 30-W/ mm GaN HEMTs by field plate optimization. IEEE Electron Device Lett 2004;25(3):117–9. [8] Waltereit P, Bronner W, Kiefer R, Quay R, Kuehn J, van Raay F, et al. High efficiency and low leakage AlGaN/GaN HEMTs for a robust, reproducible and reliable X-band MMIC space technology. In: CS MANTECH conference, Portland, Oregon, USA, May 2010. [9] Tapajna M, Killat N, Chowdhury U, Jimenez JL, Kuball M. The role of surface barrier oxidation on AlGaN/GaN HEMTs reliability. Microelectron Reliab 2012;52(1):29–32. [10] JEDEC standard JESD22-A114F and JESD22-A115C.. [11] JEDEC standard JESD35. . [12] JEDEC standard JESD22-A110. . [13] Wang Cong, Kim Nam-Young. Fabrication of Metal–insulator–metal Capacitors with SiNx Thin Films Deposited by Plasma-enhanced Chemical Vapor Deposition. Trans Electr Electron Mater 2009;10(5):147–51. [14] Zhou H, Shi FG, Zhao B, Yota J. Temperature accelerated dielectric breakdown of PECVD low-k carbon doped silicon dioxide dielectric thin films. Appl Phys A 2005;81(4):767–71. [15] Jiro Yota. Effects of deposition method of PECVD silicon nitride as MIM capacitor dielectric for GaAs HBT technology. In: Symposium on silicon nitride, silicon dioxide, and emerging dielectrics of the 2011 electrochemical society (ECS) meeting, Montreal, Canada, May 2011. [16] Zhou H, Kim HK, Shi FG, Zhao B, Yota J. Microelectron J 2002;33:999. [17] Ritu Daipuria, Daipuria, Sindhu Dayal, Robert Laishram, Somna Mahajan, Rawal DS, Bhat KM, Sharma HS, Sehgal BK, Muralidharan R. Silicon nitride films for passivation of pHEMT based MMIC. In: Physics of Semiconductor Devices, Mumbai, India, Dec 2007. p. 431–34.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Investigation of high performance Edge Lifted Capacitors reliability for GaAs and GaN MMIC technology Ming-Hung Weng a,b,⇑, Chao-Hung Chen a, Che-Kai Lin a, Shih-Hui Huang a, Jhih-Han Du a, Sheng-Wen Peng a, Walter Wohlmuth a, Frank Yung-Shi Chou a, Chang-Hwang Hua a a b
WIN Semiconductors Corp., No. 35, Technology 7th Road, Hwaya Technology Park, Kuei Shan Hsiang, Tao Yuan Shien 333, Taiwan Current address: School of Electrical and Electronic Engineering, Newcastle University, Newcastle, NE1 7RU, UK
a r t i c l e
i n f o
Article history: Received 7 July 2014 Received in revised form 16 September 2014 Accepted 19 September 2014 Available online 20 November 2014 Keywords: ELC MIM Refractive index TDDB ESD bHAST
a b s t r a c t This paper reports extensive investigations of Edge Lifted Capacitors (ELC) and standard metal–insulator– metal (MIM) capacitors with different refractive index and thickness of Silicon Nitride (Si3N4) dielectric films. The wafer-level electrical measurements reveal size dependence of capacitances and breakdown voltages. Physical characterization was performed using Fourier transform infrared spectroscopy (FTIR) to understand intrinsic properties of the studied films and failure-related cross sections were used to predict possible leakage mechanisms. Reliability testing of Human Body Model (HBM) and Machine Model (MM) electrostatic discharge (ESD), time-dependent dielectric breakdown (TDDB), and biased high temperature accelerated stress testing (bHAST) were performed and will be reviewed for GaAs and GaN monolithic microwave integrated circuit (MMIC) applications. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction In recent years, foundry services for GaN HEMTs on SiC devices [1–4] have gained remarkable attention due to the device’s potential to revolutionize power and radio frequency (RF) electronics with predictions that the overall commercial and military markets will be multi-billion dollar markets by 2020 [5]. The move to high efficiency, low power consumption RF amplifier building blocks is seen to increase the GaN-based component demand. Since GaN HEMTs are operated at high voltage, passive components such as capacitors are also required to tolerate high voltages during circuit operation. GaN RF transistors typically operate at 28 to 50V and subsequently require capacitors, within the circuit, to withstand blocking voltages of > 200 V without damage [6–9]. The Silicon Nitride (Si3N4) dielectric film can be optimized by changing the Si3N4 composition and film stress using multi-layer plasmaenhanced chemical vapour deposition (PECVD) processes. The breakdown voltage is highly correlated to the electric field intensity within the capacitor dielectric. Therefore, a new Metal Insulator Metal (MIM) capacitor structure termed the Edge Lifted Capacitor (ELC) was developed. The high electric field around the
⇑ Corresponding author. http://dx.doi.org/10.1016/j.microrel.2014.09.023 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
capacitor periphery is effectively relieved in the ELC and thus the breakdown performance is significantly enhanced.
2. Devices structure and experiments Capacitor fabrication starts with Metal1 as the bottom metal layer and Metal2 as the contact metal layer as shown in Fig. 1. A SPAN layer is formed to provide mechanical and structural support for the air bridge to minimize the parasitic capacitance. The overlay distance between SPAN and Metal1 creates desirable lifted metal edges of Metal2. In order to achieve high breakdown (VBD) and simultaneously have high specific capacitance (CP), the use of different capacitor arrays, ranging from 200 to 3.5 105 lm2, and various Si3N4 stoichiometric film properties with refractive index (R.I.), ranging from 1.9 to 2.1, were used and compared. 123 different sites were characterized for each 100 mm wafer. Table 1 shows a summary of Si3N4 thickness and refractive index used in the experiments. A total of five Si3N4 films have been studied with a 150 nm thick dielectric film used for Film_1 to Film_3 and a 300 nm thick dielectric film used for Film_4 and Film_5. The reference films, the process of record (POR) films, were also compared in this study. The difference in material properties of SiC substrates, such as transparency and higher thermal conductivity (300 W m 1 K 1 in SiC)
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Fig. 1. Schematic cross section of an Edge Lifted Capacitor (ELC).
Table 1 Summary table of Si3N4 thickness and refractive index. Film
Thickness (nm)
R.I.
1 2 3 4 5 Ref. POR1 Ref. POR2
150 150 150 300 300 150 150
2.1 2.0 1.9 2.0 1.9 1.95 2.0
as compared to GaAs substrates requires optimization of the Si3N4 film growth conditions. The flow rate, power, pressure and NH3:SiH4 ratio in the deposition process was varied resulting in different Si–N bond density and dielectric film refractive index. The bonding configurations within the film were examined by Fourier Transform Infrared Spectroscopy (FTIR). Before deposition of the Si3N4 film for the capacitor, a 200 nm thick Si3N4 film was deposited over the whole wafer isolating the substrate from the capacitor preventing leakage paths from contact pads to the substrate. Wafer-level electrical tests were performed using an Agilent 4072 high power supply with a Precio Octo auto prober. A voltage and current compliance of 200 V and 100 lA, respectively, is used to prevent probe melt-down. The intrinsic and
extrinsic breakdown mechanisms are also characterized and fit to the Frenkel–Poole equation. The reliability performance testing included: human-body-model (HBM) and machine-model (MM) electrostatic discharge (ESD) [10], time-dependent dielectric breakdown (TDDB) [11], and biased high temperature accelerated stress (bHAST) [12] following JEDEC standards and guidelines to verify the reliability of the ELC capacitors. Finally, the capacitor geometry scaling is modelled using Advanced Design System (ADS). 3. Measurement results and discussion Fig. 2 shows cross-sectional comparisons of the conventional MIM and the ELC designs. The conventional MIM design features a metal skirt which unintentionally results in a leakage path due to possible metal migration and concentrated electrical field. The ELC, on the other hand, provides a more robust capacitor, better leakage uniformity, and a 10 to 20% enhancement in the leakage behavior. This advantage is observed in the electrical characterization comparison between the MIM capacitors and the ELC with 1500 Å thick silicon nitride layers are manufactured with the SiH4/NH3 gas ratio (R = 0.65) and R.I. = 2 as shown in Fig. 3. These capacitors electrical characterization summarizes the leakage at the compliance current of 100 lA. As can be seen, the weak leakage
Fig. 2. SEM cross-section and side views of the ELC and MIM capacitors.
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Fig. 3. Breakdown performance comparisons of ELC and MIM capacitors.
Fig. 4. Leakage comparison of the capacitor array with total Si3N4 thickness of 200 nm using single and double step deposition. The VBD reached the 200 V compliance limit of the test system for the 30 60 lm2 ELC using the double step deposition.
characteristics of these two capacitors design significantly decreased, when the capacitor area was increased due to larger metal area the level of defects and roughness can be increased [13]. The ELC exhibits better uniformity and higher capacitance in comparison to the MIM capacitor. The metal skirts which cause early failure in MIM capacitors are only revealed in cross-section images and are difficult to observe during visual microscope inspection. Fig. 4 compares leakage performance versus an array of various sized capacitors with single and double step PECVD Si3N4 deposition. The multi-layer Si3N4 film was reported to exhibit lower leakage current and higher dielectric breakdown voltage [14]. The double step film can also have a reduction of pinholes density [15], different glass transition temperature and different optical properties [16]. In this study, the dielectric constants are determined to be 6.57 for the double step film deposition, and a slightly lower value of 6.15 for the single step film deposition which is comparable to previously reported Si3N4 dielectric constants in literature [15]. The improvement in leakage behavior with a double step versus a single step deposition was determined to be minimal in this paper as an average increase of only 5–6 V in VBD was extracted across the capacitor array. Fig. 5 shows the normalized capacitance per unit area of the fabricated Si3N4 films. The capacitor size increases from left to right for each grouping from 200 to 3.5 105 lm2. An alternative process for better leakage behavior capacitors is also available for Film_5 and Film_6 with an averaged CP at 160 pF/mm2. The higher
Fig. 5. Normalized capacitance to area and film comparison. Each box plot contains 123 test points. The horizontal red lines show normalized capacitance of 160 and 320 pF/mm2. The largest ELC is shown in the uppermost right-hand side of each group, with an area of 3.5 105 lm2. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
capacitance values extracted in Film_1 were confirmed to not be related to the physical thickness variation of the films as determined by scanning electron microscopy (SEM) cross-sections (images not shown). The summary of dielectric breakdown is illustrated in Fig. 6 where each box plot represents 123 tested capacitors across a wafer. The three groups of 150 nm thick Si3N4 films indicate a significant improvement of 50 V for VBD from comparing Film_1 to Film_3. In addition, a remarkable blocking voltage is achieved in Film_5 showing that the robustness of this process has achieved VBD beyond the testing tool limitation of 200 V at an estimated breakdown between 265 and 330 V by Keithley 2657 A manual measurement. It is noticeable in both the VBD and CP plots that the smaller capacitors have different average values in comparison to the larger capacitors. Fig. 7 illustrates potential issues that cause this difference. As the ELC is scaled down in size, the parasitic contribution from the ELC edge becomes significant. The parasitic capacitance is attributable to the edge-lifted under-side, air bridges, inter-connects and probe pads. The considerable peripheral to effective dielectric areas aspect ratio in the capacitors are
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Fig. 6. Leakage VBD plots with current sourced at 100 lA and voltage compliance of 210 V. Each box plot contains 123 test points. The 150 nm films are grouped in squares. The capacitor sizes, for each film, increases from left to right. The dashed arrows show the box plots of capacitors with the same area size of capacitor for Films 1, 2 and 3.
Fig. 8. FTIR spectra overlay of the various Si3N4 films.
Table 2 FTIR averaged integrated band intensities in the various films. Film property
Absorption Ref. POR1 Ref. POR2 Film 1 peaks (cm 1)
R.I. N–H 3350 Si–H 2150 NH/SiH ratio
1.95 0.403 0.415 0.971
2 0.310 0.323 0.958
2.1 0.0237 0.0459 0.5174
Film 2 Film 3 2 0.110 0.126 0.873
1.9 0.222 0.235 0.947
Fig. 7. Capacitance and size dependence in the capacitor arrays. The insets with the graphs show measured (not normalized) capacitance and one of the smallest capacitors with minimum effective capacitor area.
calculated to be as high as 247:1 among small capacitors and 1:6 for the larger capacitors presented. Fig. 8 and Table 2, together, show the intrinsic Si3N4 film properties determined by FTIR. As shown in Table 2, the peaks at 2150 and 3350 cm 1 can be attributed to the Si–H and the N–H bond absorptions [17], respectively. Film_3 exhibits higher N–H and Si–H bond concentrations and higher N–H to Si–H ratio FTIR peaks than Film_1 and Film_2. Film_1 suffers poor leakage characteristics and contains lower Si–H and N–H bonds, than the other films from the FTIR bond absorption peaks. Reference films POR1 and POR2 (Ref. POR1 and Ref. POR2) are the proven high quality Si3N4 films used in the production GaAs ELC technology and were chosen as the baseline for GaN ELC. According to FTIR analysis and the leakage performance results, Film_3 has similar NH to SiH ratio in comparison to the Ref. POR1 and Ref. POR2 films and therefore has been used as film of choice for the GaN technologies. GaN transistor with field-plate is disposed between the gate and drain, so tha and an electric field is distributed between gate and drain regions to reduce a peak value and to reduce gate leakage current. In order to understand the basic behavior of the tested Si3N4 dielectric layers, the field plate to gate capacitor’s leakage characteristics for the three different Si3N4 films have been
Fig. 9. MIM capacitor leakage behavior in GaN technology with different Si3N4 R.I.
recorded. As can be seen in Fig. 9, the three Si3N4 films exhibit quite different leakage current behavior. The field plate to gate capacitor with Film_1 shows the highest leakage current. The field plate to gate capacitor with Film_3 exhibits the lowest leakage current behavior of all three Si3N4 types. A leakage stress analysis reveals that higher R.I. Si3N4 films with lower NH3/SiH4 ratio showed poorer leakage performance. Time Dependent Dielectric Breakdown characterization at 125 °C is done to verify the lifetime of the capacitors. Fig. 10 compares the standard MIM capacitor and the ELC in GaAs MMIC technology. The required operating and breakdown voltages are different for the GaAs capacitors in comparison to the GaN capacitors, however, both MIM capacitor and ELC achieve above 100 V operation but the TDDB lifetime of the ELC at 20 V is at about 2 orders of magnitude greater than the minimum requirement of
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Fig. 10. (a) TDDB comparison of MIM capacitor and ELC. (b) Distinguishable failures on the edges and non-edges are observed.
Fig. 11. TDDB performance of the ELC in GaN technology with 230 nm Si3N4 film thickness.
20 years (6.3 108 s) under 100 200 lm2 capacitor size. The breakdown fields are calculated at 6.67 MV/cm and 7.0 MV/cm for the MIM capacitor and the ELC, respectively. The failure modes for the MIM capacitor are significantly different from the ELC. In the ELC, failures occur randomly within the capacitor and appear as Si3N4 film punch-through; whilst in the MIM capacitors the failures are mostly located on the edge of the capacitor in the vicinity of the metal skirts and the highly concentrated electrical field. Fig. 11 shows the TDDB performance in the GaN technology. A capacitor breakdown voltage of between 210 and 260 V indicates
a maximum electrical field of 11.3 MV/cm. A blocking voltage in excess of 100 V is found to have 20 years lifetime. GaN MMICs amplifier operation in class E or F can generate voltages in excess of 3 times the operating voltage necessitating the need for close to 100 V breakdown capacitors for 28 V transistor operation. The graph also shows that there is no influence of substrate thickness on the GaN ELC performance when comparing bulk (500 lm) and thinned (100 lm) substrates. Electrostatic discharge (ESD) has been known to be one of the major causes of yield and reliability failures in IC manufacturing. In this study, the ESD characteristics of MIM and ELC capacitors have been investigated using both Human Body Model (HBM) and Machine Model (MM) testing. As shown in Fig. 12, a direct comparison of MM and HBM was performed on the GaAs MIM capacitor and ELC with two dimension types (type1: 200 200 lm2, type2: 450 900 lm2). As expected, the ESD voltage of the MIM capacitor and the ELC show some dependence on the capacitor area, where the ESD voltage increases with increasing capacitor area. It is clear that there is no significant difference in ESD performance between the capacitors. Biased HAST (bHAST) testing is used to evaluate the ability of electronic components to resist moisture ingress. To evaluate the impact of moisture ingress on the GaAs MIM capacitor and ELC, a 70 140 lm MIM capacitor and ELC were employed for the dielevel bHAST tests. These capacitors are then exposed to JEDEC standard bHAST test conditions, which are a temperature of 130 °C, 85% relative humidity and 33.3 psi of pressure for a period of 96 h under 8 V bias in the case of GaAs transistors used in this study. Fig. 13 shows the appearance and yield loss after bHAST results
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Fig. 12. (a) Human body model mode and (b) machine model mode ESD comparison graph for GaAs MIM capacitors and ELCs.
for both the MIM capacitor and the ELC. The ELC shows significantly enhanced moisture resistance and better yield after bHAST testing in comparison to the MIM capacitor. After bHAST inspection of the failed MIM capacitors, it was revealed that the failures were mainly observed near the edge of the devices in the vicinity of the metal skirts. Fig. 14 shows good matching between the modeled and measured data. The design rules of the ELC are completed and this capacitor structure is released as the preferable option in the design kit for foundry customers in the GaAs and GaN technologies. A less than 5% error between measured and modeled data is confirmed for ELCs ranging from 50 50 lm2 to 200 200 lm2. 4. Conclusion
Fig. 13. Image of ELC and MIM capacitors plus summary table of yield loss after bHAST test.
An effective and highly manufacturable process for improving the breakdown voltage, leakage behavior uniformity, and average specific capacitance is reported with high quality Si3N4 films and
Fig. 14. Measured data (red line) and modeled (blue line) of selected GaN ELC. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.)
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novel ELC design for GaAs and GaN MMIC applications. The ELC is designed to eliminate the high electrical field associated with metal skirts that exist in MIM capacitors and to improve quality control. Quality control is improved by eliminating the metal skirts which are difficult to detect during visual microscopy inspection. The use of Si3N4 films with low refractive index for the capacitors further improves the reliability. The size dependence performance of VBD and CP for the ELCs was confirmed with wafer level measurements. Small capacitors were reported for scientific study only, as the high parasitic capacitance prevents accurate modeling and therefore limited applicability in MMIC design. The comparisons of ESD, TDDB and bHAST of both MIM and ELC designs were presented. A comprehensive model and PDK have been created for the ELC providing designers and customers a highly reliable and uniform capacitor for use in advanced high power and high frequency GaAs and GaN MMIC technology enabling new markets and applications. Acknowledgements The authors would like to thank all the members who support the GaAs and GaN technology development in WIN Semiconductors including the teams from: the Testing, Device Characterization and Model; and the Process and Manufacturing groups. Recognition of support and help is also given to J.H Lin, Nicole Lin, Y.H. Shih, S.Y. Wan and Carol Chen from the Testing, Failure Analysis and Quality Control teams. References [1] Weng MH, Lin CK, Du JH, Wang WC, Wang WK, Wohlmuth W. Pure play GaN foundry 0.25 lm HEMT TECHNOLOGY for RF applications. In: IEEE CSIC symposium, Monterey California, USA, Oct 2013.
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[2] Wohlmuth W, Weng MH, Lin CK, Du JH, Ho SY, Chou TY, et al. AlGaN/GaN HEMT development targeted for X-band applications. In: IEEE COMCAS, Israel, Oct 2013. [3] Wang WC, Chen CH, Du JH, Weng MH, Lin CK, Huang CC, et al. Development and control of a 0.25 lm gate process module for AlGaN/GaN HEMT Production. In: CS MANTECH conference, New Orleans, Louisiana, USA, May 2013. [4] van der Wel PJ, de Beer JR, van Boxtel RJM, Hsieh YY, Wang YC. Reliability assessment of extrinsic defects in sinx metal–insulator–metal capacitors. In: Reliability of compound semiconductors workshop, San Antonio, Texas, November 2006. p. 35–40. [5] Hindle P. Future RF market opportunities for GaN. Microw J 2012;55(6):22–4. [6] Pengelly RS, Wood SM, Milligan JW, Sheppard ST, Pribble WL. A review of GaN on SiC high electron-mobility power transistors and MMICs. IEEE Trans Microw Theory Tech 2012;60(6). [7] Wu Y-F, Saxler A, Moore M, Smith RP, Sheppard S, Chavarkar PM, et al. 30-W/ mm GaN HEMTs by field plate optimization. IEEE Electron Device Lett 2004;25(3):117–9. [8] Waltereit P, Bronner W, Kiefer R, Quay R, Kuehn J, van Raay F, et al. High efficiency and low leakage AlGaN/GaN HEMTs for a robust, reproducible and reliable X-band MMIC space technology. In: CS MANTECH conference, Portland, Oregon, USA, May 2010. [9] Tapajna M, Killat N, Chowdhury U, Jimenez JL, Kuball M. The role of surface barrier oxidation on AlGaN/GaN HEMTs reliability. Microelectron Reliab 2012;52(1):29–32. [10] JEDEC standard JESD22-A114F and JESD22-A115C.