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Investigation of the gate-bias induced instability for InGaZnO TFTs under dark and light illumination
Thin Solid Films 520 (2011) 1422–1426
Contents lists available at SciVerse ScienceDirect
Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Investigation of the gate-bias induced instability for InGaZnO TFTs under dark and light illumination T.C. Chen a, T.C. Chang a,⁎, T.Y. Hsieh a, C.T. Tsai a, S.C. Chen a, C.S. Lin b, F.Y. Jian a, M.Y. Tsai c a b c
Department of Physics and Center for Nanoscience & Nanotechnology, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 804, Taiwan, ROC Department of Electrical Engineering, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung, Taiwan, ROC Department of Electro-Optical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC
a r t i c l e
i n f o
Available online 8 September 2011 Keywords: InGaZnO TFTs Light illumination Gate-bias induced instability
a b s t r a c t Mechanism of the instability for indium–gallium–zinc oxide thin film transistors caused by gate-bias stress performed in the dark and light illumination was investigated in this paper. The parallel Vt shift with no degradation of subthreshold swing (S.S) and the fine fitting to the stretched-exponential equation indicate that charge trapping model dominates the degradation behavior under positive gate-bias stress. In addition, the significant gate-bias dependence of Vt shift demonstrates that electron trapping effect easily occurs under large gate-bias since the average effective energy barrier of electron injection decreases with increasing gate bias. Moreover, the noticeable decrease of threshold voltage (Vt) shift under illuminated positive gatebias stress and the accelerated recovery rate in the light indicate that the charge detrapping mechanism occurs under light illumination. Finally, the apparent negative Vt shift under illuminated negative gate-bias stress was investigated in this paper. The average effectively energy barrier of electron and hole injection were extracted to clarify that the serious Vt degradation behavior comparing with positive gate-bias stress was attributed to the lower energy barrier for hole injection. © 2011 Elsevier B.V. All rights reserved.
1. Introduction Recently, thin film transistors (TFTs) with active layers of oxide semiconductors, such as ZnO and amorphous InGaZnO (a-IGZO) have attracted considerable attentions to serve as the active layer of thin film transistors (TFTs) for the application in next generation display industry, because of their high mobility (N10 cm 2/Vs), low processing temperature, and good transparency to visible light [1–5]. Although oxide-based TFTs have shown high performance, they have also demonstrated limitations such as instability under bias stress and in different ambient gases [6–8]. Since switching and driving TFTs in transparent AM-OLED panels always operate under the illumination of OLED and outer environment lights, therefore, the excellent reliability suffering from gate-bias stress and/or visiblelight illumination is of crucial importance for ZnO-based TFTs. In the previous studies, the instability of a-IGZO TFT under positive gate-bias has been attributed to the electron trapping mechanism and the degradation behavior under negative gate-bias stress is
⁎ Corresponding author at: Department of Physics, National Sun Yat-Sen University, 70 Lien-Hai Road, Kaohsiung, 80424, Taiwan, ROC. Tel.: + 886 7 5252000 3708; fax: + 886 7 5253709. E-mail address: [email protected] (T.C. Chang). 0040-6090/$ – see front matter © 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2011.09.002
negligible since the lack of holes in the n-type ZnO-based material [9–13]. However, the physic mechanism of electron trapping is not investigated in detail and the instability under illuminated gate-bias stress is worth of further investigation to conform the real operating conditions. In this letter, the charge trapping effect was analyzed under different gate-biases and environments, in addition, the degradation mechanism was investigated using theoretical fitting to analyze the electron and hole trapping efficiency. 2. Experiment Inverted coplanar a-IGZO TFTs were produced on glass substrate in this work. The shaped Ti/Al/Ti (50/200/50 nm) gate electrodes were capped with 300-nm-thick SiOx gate dielectric. The source/drain electrodes were formed with DC-sputtered Ti/Al/Ti (50/200/50 nm) and then patterned by wet-etching. An active layer of 30-nm-thick a-IGZO film was deposited by a DC magnetron sputtering system using a target of In:Ga:Zn = 1:1:1 atomic ratio. Finally, the device was capped with a 200 nm SiOx layer by PECVD at 170 °C. In this work, the threshold voltage (Vt) is defined as the gate voltage (VG) when the normalized drain current (NId = Id × L/W) reaches 1 nA and the all transfer characteristics were measured with a fixed drain voltage (VD) of 5 V in the dark. Furthermore, all the light illumination condition was performed with light intensity of 10,000 lx.
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The parallel threshold voltage (Vt) of 9.3 V after 1000 s stress time without significant subthreshold swing (S.S) degradation indicates that the state creation can be excluded. Although the positive AC gate bias stress will induce trap states generation by analyzing the off-state C–V characteristics in the previous study, the C–V characteristics shown in the inset exhibit an apparent positive Vt shift without off-state stretch out phenomenon [14]. This behavior indicates that the charge trapping effect is the dominant degradation mechanism for the positive Vt shift under positive DC gate bias stress. Furthermore, in previous studies, the bias stress-induced degradation of a-IGZO TFTs has been attributed to the charge trapping effect, with the time dependence of ΔVt under stress following a stretched-exponential equation, as follows n h io β ΔVt ¼ V0 1– exp −ðt=τÞ
Fig. 1 shows the dark transfer ID–VG characteristics as a function of applied stress time for a-IGZO TFTs with a positive gate-bias stress (PBS) condition of VG = 60 V and VS/D = 0 V performed in the dark.
where ΔVt,trap. is the Vt shift before recovery phase, V0 = VG − Vt0 where Vt0 is the threshold voltage before stress, β is the stretched-exponential exponent and τtrap. = τ0,trap.exp(Eτ,trap./kT) represents the characteristic trapping time of carriers, Eτ,trap. is the average effective energy barrier that electrons in the a-IGZO TFT channel need to overcome for injection into the insulator, and τ0,trap is the thermal prefactor for emission over the barrier [9–11]. The fine fitting of the simulation to the experimental data under different temperatures shown in Fig. 2 (a) illustrates that the degradation behavior is attributed to the electron trapping in the gate dielectric and/or at the channel/dielectric interface. To further investigate the bias-induced charge trapping mechanism, the average
Fig. 2. (a) Time dependence of ΔVt,trap. under bias-stress at different temperatures, and fitting with the stretched-exponential equation. (b) The plot of ln τtrap. as a function of reciprocal temperature (1000/T). Inset shows the schematic energy band diagram for electron injection into the trap states through thermionic-field emission, operating with positive gate-bias.
Fig. 3. (a) Time dependence of ΔVt,trap. under different gate-bias stresses of VG = 50, 60, 70 V. (b) The plot of ln τtrap. as a function of reciprocal temperature (1000/T) under different gate-bias stresses of VG = 50, 60, 70 V, the inset shows schematic band diagram for electron trapping under different gate-bias stresses of VG = 50, 60, 70 V.
Fig. 1. Normalized I–V characteristics of a-IGZO TFTs after 1000 s gate-bias stress, VG = 60 V, VS/D = 0 V. Inset shows the C–V characteristics after positive gate bias stress after 1000 s.
3. Result and discussion
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effective energy barrier (Eτ,trap.) of 0.38 eV can be derived from the slope of Fig. 2 (b), which shows the evolution of ln τtrap. as a function of reciprocal temperature. This result indicates that electrons have to overcome an effective energy barrier of 0.38 eV at least for injection into the trap states through thermionic-field emission, and the corresponding schematic band diagram is shown in the inset of Fig. 2 (b). In order to analyze the bias dependence for charge trapping effect, the time dependence of ΔVt,trap. and the evolution of ln τtrap. as a function of reciprocal temperature under different gate biases are shown in Fig. 3 (a) and (b), respectively. The ΔVt,trap increase with increasing stress gate bias shown in Fig. 3 (a) illustrates that larger vertical electrical field will enhance the charge trapping effect. To further investigate the instability behavior under different gate biases, the average effective energy barrier of 0.59, 0.38, 0.23 eV for VG = 50, 60, 70 V, respectively, were extracted from the slope of Fig. 3 (b). The higher gate bias will induce more serious band banding, thus, the thermionic-
Fig. 5. Time dependence of Vt shift during PBS of VG = 60 V and recovery phase in the dark/light environment.
field emission mechanism will be triggered easily (the schematic energy band diagram is shown in the inset of Fig. 3 (b)). Fig. 4 (a) shows the evolution of transfer curves for a-IGZO TFTs which are stressed by VG = 60 V under light illumination (light intensity is 10,000 lx), whereas the transfer characteristics are measured in the dark. The smaller Vt shift of 3.5 V after 1000 s positive gate-bias illumination stress (PBIS) compared with PBS (Vt shift of 9.3 V) indicates that illumination can suppress the positive Vt shift. It had been verified that the photo-generated carriers in ZnO-based layer will increase free electron concentration to cause the negative Vt shift [15]. These generated free carriers will not be recombined completely after removing illumination. Therefore, the reduction of positive Vt shift under illuminated
Fig. 4. (a) Normalized I–V characteristics of a-IGZO TFTs after 1000 s bias stress of VG = 60 V under 10,000 lx visible light illumination. The inset shows the transfer curve after 1000 s illumination without gate-bias stress. [All of the I–V characteristics were measured in the dark.] (b) Time dependence of ΔVt,trap. under PBIS operation with different light intensities. (c) Time dependence of ΔVt,trap. under PBS and PBIS operation with different gate-biases.
Fig. 6. (a) Time dependence of Vt shift during recovery phase at different temperatures. (b) The variation in the extracted fitting parameters τdet. as a function of reciprocal temperature. The inset shows the schematic energy band diagram for electron detrapping after positive gate-bias stress.
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Fig. 7. (a) Normalized I–V characteristics of a-IGZO TFTs under negative gate-bias stress (NBS) for 1000 s with VG = − 60 V, VS/D = 0 V. (b) Normalized I–V characteristics of a-IGZO TFTs under negative gate-bias illumination stress (NBIS) for 1000 s with VG = − 60 V, VS/D = 0 V. (c) C–V characteristics under NBIS for 1000 s with VG = − 60 V, VS/D = 0 V. (d) Time dependence of ΔVt, under NBIS in different temperatures and the fitting with stretched-exponential equation.
positive gate-bias stress was possibly compensated by the light-induced negative Vt shift. The inset of Fig. 4 (a) exhibits the normalized I–V curves measured in the dark after illumination. The slight negative Vt shift of 1.1 V after 1000 s light illumination exhibits that the light-induced negative Vt shift is not large enough to dominate the suppression of positive Vt shift. Since the positive Vt shift under PBS is caused by electron trapping effect and the light-induced negative Vt shift can be excluded for the dominant mechanism, the suppression of Vt shift under PBIS operation can be attributed to the light-induced electron detrapping mechanism during stress. Fig. 4 (b) shows the dependence of the light intensity for Vt suppression effect under PBIS operation and the results indicate that higher light intensity can cause more apparent electron detrapping effect. Furthermore, the light-induced electron detrapping mechanism under PBIS operation occurs in different gate biases as shown in Fig. 4 (c). In order to realize the influence of light illumination on the reliability of a-IGZO TFTs under positive gate-bias stress, the recovery characteristics after positive gate-bias stress were investigated. Fig. 5 shows the recovery behaviors in the dark and light environment following a 1000 s bias stress of VG = 60 V in the dark, which the transfer curves were characterized without illumination. Obviously, the Vt can recover rapidly to the initial state after standing within 1000 s in the light environment, whereas the Vt shift remains over 2 V even standing for 2400 s in the dark environment. The recovery behaviors can be regarded as the electron detrapping from the existing traps and the efficient recovery rate demonstrates that light illumination can provide extra energy to excite the trapped electrons and enhance detrapping process [16]. To further verify that the electron detrapping mechanism is responsible for the suppression of Vt shift under PBIS operation, the experimental data are fitted well to the stretched-exponential equation for charge detrapping process defined as h i β ΔVt;det: ¼ ΔVmax: exp −ðt=τdet: Þ
Fig. 8. Plot of ln τtrap. as a function of reciprocal temperature (1000/T) for electron trapping and hole trapping under VG = 60 V and VG = − 60 V, respectively. The insets show the corresponding energy band diagram for electron trapping and hole trapping.
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is shown in Fig. 6 (a) (where ΔVmax is the maximum Vt shift before recovery phase, τdet. = τ0,det. exp(Eτ,det./kT) represents the characteristic detrapping time, the Eτ,det. is the average effective energy barrier that the carriers need to overcome for detrapping). Furthermore, the value of Eτ,det. = 0.23 eV can be extracted from a linear fitting to the plot of ln τdet. −1000/T which is shown as Fig. 6 (b). During recovery phase, the trapped electrons will be thermally activated and emitted by the internal electrical field (caused by trapped electrons). Therefore, the Eτ,det. of 0.23 eV can be regarded as the effective energy barrier that the trapped electrons have to overcome for detrapping through thermionic-field emission (the schematic band diagram is shown in the inset of Fig. 6 (b)). In this work, the effective energy barrier of electron detrapping (Eτ,det. = 0.23 eV) is lower than that of electron trapping (Eτ,trap. = 0.38 eV), agreeing with that the electrical behavior will prefer to excite the trapped charges from the existing states rather than electron trapping. Therefore, the Vt shift can be suppressed by light illumination under PBIS operation. Fig. 7 (a) exhibits the transfer of I–V curves under negative gate-bias stress (NBS) of VG = −60 V for 1000 s in the dark. The unapparent Vt shift under NBS operation can be attributed to the negligible holes in the n-type oxide semiconductor valence bands; therefore, the hole trapping in the gate dielectric and/or at the channel/dielectric interface can be ignored [12]. On the other hand, the obvious negative Vt shift more than 30 V under negative gate-bias illumination stress (NBIS) shown in Fig. 7 (b) indicates that numerous photo-generated holes will be trapped in the gate insulator or a-IGZO interface, resulting in a dramatic parallel negative Vt shift [15]. In order to exclude the subgap trap states creation under NBIS operation mentioned in the previous study [17], the C–V characteristics were measured and the parallel negative Vt shift without off-state stretch-out phenomenon shown in Fig. 7 (c) illustrates that subgap states creation is not the dominant degradation mechanism. Fig. 7 (d) shows the Vt shift versus stress time under different temperatures and the fine fitting to the well-accepted stretchedexponential model also verifies that the hole trapping mechanism is the dominant degradation mechanism under NBIS. In the previous work, the Vt shift caused by electron trapping effect under PBS (VG = 60 V) operation was 9.3 V, whereas the apparent Vt shift of 35.2 V under NBIS (Vg = −60 V) operation with same electrical field intensity but reverse direction. This obvious difference indicates that the trapping efficiency of a hole is better than an electron. Fig. 8 exhibits the evolution of ln τtrap. as a function of reciprocal temperature for PBS and NBIS, and the average effective energy barrier (Eτ,det) of electron and hole trapping were extracted as 0.38 and 0.21 eV, respectively. The difference of Eτ,det can be attributed to the energy band structure of IGZO and SiOX since the distance of conduction band for IGZO and SiOX is 4.5 eV whereas the distance of valance band for IGZO and SiOX is 1.3 eV [18]. Therefore, the average effective energy barrier for a hole is lower than an electron even with same electrical field intensity which results in apparent Vt shift under NBIS operation compared with PBS operation. 4. Conclusion In conclusion, the electron trapping effect under PBS operation was investigated under different electrical field intensities and the
Vt shift is more obvious in the higher electrical field. As a result of the average effective energy barrier extracted under different gatebiases, we can realize that the higher gate-bias can enhance energy band lowering and the thermionic-field emission effect occurs easily resulting in higher electron trapping efficiency. Furthermore, the slight degradation behavior under PBIS operation compared with PBS operation indicates that light-induced electron detrapping effect occurs during light illumination and suppresses positive Vt shift. On the other hand, the apparent Vt shift under NBIS in comparison with NBS operation indicates that photo-generated holes are trapped in the gate insulator or a-IGZO interface. Furthermore, the apparent Vt shift caused by hole trapping compared with electron trapping can be attributed to the lower energy barrier for hole injection.
Acknowledgment This work was performed at National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in KaohsiungPingtung area. The authors would like to acknowledge the financial support of the National Science Council of the Republic of China under contract nos. NSC99-2120-M-110-001 and NSC 97-2112-M-110009-MY3.
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Contents lists available at SciVerse ScienceDirect
Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Investigation of the gate-bias induced instability for InGaZnO TFTs under dark and light illumination T.C. Chen a, T.C. Chang a,⁎, T.Y. Hsieh a, C.T. Tsai a, S.C. Chen a, C.S. Lin b, F.Y. Jian a, M.Y. Tsai c a b c
Department of Physics and Center for Nanoscience & Nanotechnology, National Sun Yat-sen University, 70 Lien-hai Road, Kaohsiung 804, Taiwan, ROC Department of Electrical Engineering, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung, Taiwan, ROC Department of Electro-Optical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan, ROC
a r t i c l e
i n f o
Available online 8 September 2011 Keywords: InGaZnO TFTs Light illumination Gate-bias induced instability
a b s t r a c t Mechanism of the instability for indium–gallium–zinc oxide thin film transistors caused by gate-bias stress performed in the dark and light illumination was investigated in this paper. The parallel Vt shift with no degradation of subthreshold swing (S.S) and the fine fitting to the stretched-exponential equation indicate that charge trapping model dominates the degradation behavior under positive gate-bias stress. In addition, the significant gate-bias dependence of Vt shift demonstrates that electron trapping effect easily occurs under large gate-bias since the average effective energy barrier of electron injection decreases with increasing gate bias. Moreover, the noticeable decrease of threshold voltage (Vt) shift under illuminated positive gatebias stress and the accelerated recovery rate in the light indicate that the charge detrapping mechanism occurs under light illumination. Finally, the apparent negative Vt shift under illuminated negative gate-bias stress was investigated in this paper. The average effectively energy barrier of electron and hole injection were extracted to clarify that the serious Vt degradation behavior comparing with positive gate-bias stress was attributed to the lower energy barrier for hole injection. © 2011 Elsevier B.V. All rights reserved.
1. Introduction Recently, thin film transistors (TFTs) with active layers of oxide semiconductors, such as ZnO and amorphous InGaZnO (a-IGZO) have attracted considerable attentions to serve as the active layer of thin film transistors (TFTs) for the application in next generation display industry, because of their high mobility (N10 cm 2/Vs), low processing temperature, and good transparency to visible light [1–5]. Although oxide-based TFTs have shown high performance, they have also demonstrated limitations such as instability under bias stress and in different ambient gases [6–8]. Since switching and driving TFTs in transparent AM-OLED panels always operate under the illumination of OLED and outer environment lights, therefore, the excellent reliability suffering from gate-bias stress and/or visiblelight illumination is of crucial importance for ZnO-based TFTs. In the previous studies, the instability of a-IGZO TFT under positive gate-bias has been attributed to the electron trapping mechanism and the degradation behavior under negative gate-bias stress is
⁎ Corresponding author at: Department of Physics, National Sun Yat-Sen University, 70 Lien-Hai Road, Kaohsiung, 80424, Taiwan, ROC. Tel.: + 886 7 5252000 3708; fax: + 886 7 5253709. E-mail address: [email protected] (T.C. Chang). 0040-6090/$ – see front matter © 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.tsf.2011.09.002
negligible since the lack of holes in the n-type ZnO-based material [9–13]. However, the physic mechanism of electron trapping is not investigated in detail and the instability under illuminated gate-bias stress is worth of further investigation to conform the real operating conditions. In this letter, the charge trapping effect was analyzed under different gate-biases and environments, in addition, the degradation mechanism was investigated using theoretical fitting to analyze the electron and hole trapping efficiency. 2. Experiment Inverted coplanar a-IGZO TFTs were produced on glass substrate in this work. The shaped Ti/Al/Ti (50/200/50 nm) gate electrodes were capped with 300-nm-thick SiOx gate dielectric. The source/drain electrodes were formed with DC-sputtered Ti/Al/Ti (50/200/50 nm) and then patterned by wet-etching. An active layer of 30-nm-thick a-IGZO film was deposited by a DC magnetron sputtering system using a target of In:Ga:Zn = 1:1:1 atomic ratio. Finally, the device was capped with a 200 nm SiOx layer by PECVD at 170 °C. In this work, the threshold voltage (Vt) is defined as the gate voltage (VG) when the normalized drain current (NId = Id × L/W) reaches 1 nA and the all transfer characteristics were measured with a fixed drain voltage (VD) of 5 V in the dark. Furthermore, all the light illumination condition was performed with light intensity of 10,000 lx.
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The parallel threshold voltage (Vt) of 9.3 V after 1000 s stress time without significant subthreshold swing (S.S) degradation indicates that the state creation can be excluded. Although the positive AC gate bias stress will induce trap states generation by analyzing the off-state C–V characteristics in the previous study, the C–V characteristics shown in the inset exhibit an apparent positive Vt shift without off-state stretch out phenomenon [14]. This behavior indicates that the charge trapping effect is the dominant degradation mechanism for the positive Vt shift under positive DC gate bias stress. Furthermore, in previous studies, the bias stress-induced degradation of a-IGZO TFTs has been attributed to the charge trapping effect, with the time dependence of ΔVt under stress following a stretched-exponential equation, as follows n h io β ΔVt ¼ V0 1– exp −ðt=τÞ
Fig. 1 shows the dark transfer ID–VG characteristics as a function of applied stress time for a-IGZO TFTs with a positive gate-bias stress (PBS) condition of VG = 60 V and VS/D = 0 V performed in the dark.
where ΔVt,trap. is the Vt shift before recovery phase, V0 = VG − Vt0 where Vt0 is the threshold voltage before stress, β is the stretched-exponential exponent and τtrap. = τ0,trap.exp(Eτ,trap./kT) represents the characteristic trapping time of carriers, Eτ,trap. is the average effective energy barrier that electrons in the a-IGZO TFT channel need to overcome for injection into the insulator, and τ0,trap is the thermal prefactor for emission over the barrier [9–11]. The fine fitting of the simulation to the experimental data under different temperatures shown in Fig. 2 (a) illustrates that the degradation behavior is attributed to the electron trapping in the gate dielectric and/or at the channel/dielectric interface. To further investigate the bias-induced charge trapping mechanism, the average
Fig. 2. (a) Time dependence of ΔVt,trap. under bias-stress at different temperatures, and fitting with the stretched-exponential equation. (b) The plot of ln τtrap. as a function of reciprocal temperature (1000/T). Inset shows the schematic energy band diagram for electron injection into the trap states through thermionic-field emission, operating with positive gate-bias.
Fig. 3. (a) Time dependence of ΔVt,trap. under different gate-bias stresses of VG = 50, 60, 70 V. (b) The plot of ln τtrap. as a function of reciprocal temperature (1000/T) under different gate-bias stresses of VG = 50, 60, 70 V, the inset shows schematic band diagram for electron trapping under different gate-bias stresses of VG = 50, 60, 70 V.
Fig. 1. Normalized I–V characteristics of a-IGZO TFTs after 1000 s gate-bias stress, VG = 60 V, VS/D = 0 V. Inset shows the C–V characteristics after positive gate bias stress after 1000 s.
3. Result and discussion
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effective energy barrier (Eτ,trap.) of 0.38 eV can be derived from the slope of Fig. 2 (b), which shows the evolution of ln τtrap. as a function of reciprocal temperature. This result indicates that electrons have to overcome an effective energy barrier of 0.38 eV at least for injection into the trap states through thermionic-field emission, and the corresponding schematic band diagram is shown in the inset of Fig. 2 (b). In order to analyze the bias dependence for charge trapping effect, the time dependence of ΔVt,trap. and the evolution of ln τtrap. as a function of reciprocal temperature under different gate biases are shown in Fig. 3 (a) and (b), respectively. The ΔVt,trap increase with increasing stress gate bias shown in Fig. 3 (a) illustrates that larger vertical electrical field will enhance the charge trapping effect. To further investigate the instability behavior under different gate biases, the average effective energy barrier of 0.59, 0.38, 0.23 eV for VG = 50, 60, 70 V, respectively, were extracted from the slope of Fig. 3 (b). The higher gate bias will induce more serious band banding, thus, the thermionic-
Fig. 5. Time dependence of Vt shift during PBS of VG = 60 V and recovery phase in the dark/light environment.
field emission mechanism will be triggered easily (the schematic energy band diagram is shown in the inset of Fig. 3 (b)). Fig. 4 (a) shows the evolution of transfer curves for a-IGZO TFTs which are stressed by VG = 60 V under light illumination (light intensity is 10,000 lx), whereas the transfer characteristics are measured in the dark. The smaller Vt shift of 3.5 V after 1000 s positive gate-bias illumination stress (PBIS) compared with PBS (Vt shift of 9.3 V) indicates that illumination can suppress the positive Vt shift. It had been verified that the photo-generated carriers in ZnO-based layer will increase free electron concentration to cause the negative Vt shift [15]. These generated free carriers will not be recombined completely after removing illumination. Therefore, the reduction of positive Vt shift under illuminated
Fig. 4. (a) Normalized I–V characteristics of a-IGZO TFTs after 1000 s bias stress of VG = 60 V under 10,000 lx visible light illumination. The inset shows the transfer curve after 1000 s illumination without gate-bias stress. [All of the I–V characteristics were measured in the dark.] (b) Time dependence of ΔVt,trap. under PBIS operation with different light intensities. (c) Time dependence of ΔVt,trap. under PBS and PBIS operation with different gate-biases.
Fig. 6. (a) Time dependence of Vt shift during recovery phase at different temperatures. (b) The variation in the extracted fitting parameters τdet. as a function of reciprocal temperature. The inset shows the schematic energy band diagram for electron detrapping after positive gate-bias stress.
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Fig. 7. (a) Normalized I–V characteristics of a-IGZO TFTs under negative gate-bias stress (NBS) for 1000 s with VG = − 60 V, VS/D = 0 V. (b) Normalized I–V characteristics of a-IGZO TFTs under negative gate-bias illumination stress (NBIS) for 1000 s with VG = − 60 V, VS/D = 0 V. (c) C–V characteristics under NBIS for 1000 s with VG = − 60 V, VS/D = 0 V. (d) Time dependence of ΔVt, under NBIS in different temperatures and the fitting with stretched-exponential equation.
positive gate-bias stress was possibly compensated by the light-induced negative Vt shift. The inset of Fig. 4 (a) exhibits the normalized I–V curves measured in the dark after illumination. The slight negative Vt shift of 1.1 V after 1000 s light illumination exhibits that the light-induced negative Vt shift is not large enough to dominate the suppression of positive Vt shift. Since the positive Vt shift under PBS is caused by electron trapping effect and the light-induced negative Vt shift can be excluded for the dominant mechanism, the suppression of Vt shift under PBIS operation can be attributed to the light-induced electron detrapping mechanism during stress. Fig. 4 (b) shows the dependence of the light intensity for Vt suppression effect under PBIS operation and the results indicate that higher light intensity can cause more apparent electron detrapping effect. Furthermore, the light-induced electron detrapping mechanism under PBIS operation occurs in different gate biases as shown in Fig. 4 (c). In order to realize the influence of light illumination on the reliability of a-IGZO TFTs under positive gate-bias stress, the recovery characteristics after positive gate-bias stress were investigated. Fig. 5 shows the recovery behaviors in the dark and light environment following a 1000 s bias stress of VG = 60 V in the dark, which the transfer curves were characterized without illumination. Obviously, the Vt can recover rapidly to the initial state after standing within 1000 s in the light environment, whereas the Vt shift remains over 2 V even standing for 2400 s in the dark environment. The recovery behaviors can be regarded as the electron detrapping from the existing traps and the efficient recovery rate demonstrates that light illumination can provide extra energy to excite the trapped electrons and enhance detrapping process [16]. To further verify that the electron detrapping mechanism is responsible for the suppression of Vt shift under PBIS operation, the experimental data are fitted well to the stretched-exponential equation for charge detrapping process defined as h i β ΔVt;det: ¼ ΔVmax: exp −ðt=τdet: Þ
Fig. 8. Plot of ln τtrap. as a function of reciprocal temperature (1000/T) for electron trapping and hole trapping under VG = 60 V and VG = − 60 V, respectively. The insets show the corresponding energy band diagram for electron trapping and hole trapping.
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is shown in Fig. 6 (a) (where ΔVmax is the maximum Vt shift before recovery phase, τdet. = τ0,det. exp(Eτ,det./kT) represents the characteristic detrapping time, the Eτ,det. is the average effective energy barrier that the carriers need to overcome for detrapping). Furthermore, the value of Eτ,det. = 0.23 eV can be extracted from a linear fitting to the plot of ln τdet. −1000/T which is shown as Fig. 6 (b). During recovery phase, the trapped electrons will be thermally activated and emitted by the internal electrical field (caused by trapped electrons). Therefore, the Eτ,det. of 0.23 eV can be regarded as the effective energy barrier that the trapped electrons have to overcome for detrapping through thermionic-field emission (the schematic band diagram is shown in the inset of Fig. 6 (b)). In this work, the effective energy barrier of electron detrapping (Eτ,det. = 0.23 eV) is lower than that of electron trapping (Eτ,trap. = 0.38 eV), agreeing with that the electrical behavior will prefer to excite the trapped charges from the existing states rather than electron trapping. Therefore, the Vt shift can be suppressed by light illumination under PBIS operation. Fig. 7 (a) exhibits the transfer of I–V curves under negative gate-bias stress (NBS) of VG = −60 V for 1000 s in the dark. The unapparent Vt shift under NBS operation can be attributed to the negligible holes in the n-type oxide semiconductor valence bands; therefore, the hole trapping in the gate dielectric and/or at the channel/dielectric interface can be ignored [12]. On the other hand, the obvious negative Vt shift more than 30 V under negative gate-bias illumination stress (NBIS) shown in Fig. 7 (b) indicates that numerous photo-generated holes will be trapped in the gate insulator or a-IGZO interface, resulting in a dramatic parallel negative Vt shift [15]. In order to exclude the subgap trap states creation under NBIS operation mentioned in the previous study [17], the C–V characteristics were measured and the parallel negative Vt shift without off-state stretch-out phenomenon shown in Fig. 7 (c) illustrates that subgap states creation is not the dominant degradation mechanism. Fig. 7 (d) shows the Vt shift versus stress time under different temperatures and the fine fitting to the well-accepted stretchedexponential model also verifies that the hole trapping mechanism is the dominant degradation mechanism under NBIS. In the previous work, the Vt shift caused by electron trapping effect under PBS (VG = 60 V) operation was 9.3 V, whereas the apparent Vt shift of 35.2 V under NBIS (Vg = −60 V) operation with same electrical field intensity but reverse direction. This obvious difference indicates that the trapping efficiency of a hole is better than an electron. Fig. 8 exhibits the evolution of ln τtrap. as a function of reciprocal temperature for PBS and NBIS, and the average effective energy barrier (Eτ,det) of electron and hole trapping were extracted as 0.38 and 0.21 eV, respectively. The difference of Eτ,det can be attributed to the energy band structure of IGZO and SiOX since the distance of conduction band for IGZO and SiOX is 4.5 eV whereas the distance of valance band for IGZO and SiOX is 1.3 eV [18]. Therefore, the average effective energy barrier for a hole is lower than an electron even with same electrical field intensity which results in apparent Vt shift under NBIS operation compared with PBS operation. 4. Conclusion In conclusion, the electron trapping effect under PBS operation was investigated under different electrical field intensities and the
Vt shift is more obvious in the higher electrical field. As a result of the average effective energy barrier extracted under different gatebiases, we can realize that the higher gate-bias can enhance energy band lowering and the thermionic-field emission effect occurs easily resulting in higher electron trapping efficiency. Furthermore, the slight degradation behavior under PBIS operation compared with PBS operation indicates that light-induced electron detrapping effect occurs during light illumination and suppresses positive Vt shift. On the other hand, the apparent Vt shift under NBIS in comparison with NBS operation indicates that photo-generated holes are trapped in the gate insulator or a-IGZO interface. Furthermore, the apparent Vt shift caused by hole trapping compared with electron trapping can be attributed to the lower energy barrier for hole injection.
Acknowledgment This work was performed at National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in KaohsiungPingtung area. The authors would like to acknowledge the financial support of the National Science Council of the Republic of China under contract nos. NSC99-2120-M-110-001 and NSC 97-2112-M-110009-MY3.
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