- Email: [email protected]
Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures
Thin Solid Films 528 (2013) 57–60
Contents lists available at SciVerse ScienceDirect
Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures Ming-Yen Tsai a, Ting-Chang Chang b, c,⁎, Ann-Kuo Chu a, Te-Chih Chen b, Tien-Yu Hsieh b, Yu-Te Chen a, Wu-Wei Tsai d, Wen-Jen Chiang d, Jing-Yi Yan d a
Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan Department of Physics and Institute of Electro-Optical Engineering, & Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan d Industrial Technology Research Institute, 195, Sec. 4, Chung Hsing Rd., Hsinchu, 31040, Taiwan b c
a r t i c l e
i n f o
Available online 6 November 2012 Keywords: Indium gallium zinc oxide (IGZO) Thin film transistors (TFTs) Hot-carrier Kick-back effect
a b s t r a c t This letter studies the hot-carrier effect in indium–gallium–zinc oxide (IGZO) thin film transistors with symmetric and asymmetric source/drain structures. The different degradation behaviors after hot-carrier stress in symmetric and asymmetric source/drain devices indicate that different mechanisms dominate the degradation. Since the C–V measurement is highly sensitive to trap states compared to the I–V characterization, C–V curves are utilized to analyze the hot-carrier stress-induced trap state generation. Furthermore, the asymmetric C–V measurements CGD (gate-to-drain capacitance) and CGS (gate-to-source capacitance) are used to analyze the trap state in channel location. The asymmetric source/drain structure under hot-carrier stress induces an asymmetric electrical field and causes different degradation behaviors. In this work, the on-current and subthreshold swing (S.S.) degrade under low electrical field, whereas an apparent Vt shift occurs under large electrical field. The different degradation behaviors indicate that trap states are generated under a low electrical field and the channel-hot-electron (CHE) effect occurs under a large electrical field. © 2012 Elsevier B.V. All rights reserved.
1. Introduction Amorphous indium–gallium–zinc-oxide (a-IGZO) thin film transistors (TFTs) have attracted much attention for active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) due to their high electron mobility (>10 cm2/Vs), high transparency to visible light and low-temperature process [1–5]. Furthermore, amorphous oxide semiconductor-based materials are also expected to be adopted as nonvolatile memory devices [6–8]. Among a variety of amorphous oxide semiconductors, a-IGZO TFTs are thought to be the most promising for practical applications. Although zinc-oxide based TFTs have shown excellent performance, they still have reliability issues such as instability under light illumination and bias stress in different ambient gases [9–13]. TFTs play an important role in AMLCDs and AMOLEDs, and therefore the effect of hot-carriers on TFT reliability is worthy of study. Pixel circuits in AMLCDs are composed of a switching TFT, a storage capacitor and a liquid crystal capacitor. The parasitical capacitor across the switching TFT gate and drain, however, can affect the amount of stored charge in the storage capacitor. The fluctuation of stored charges during ⁎ Corresponding author at: Department of Physics and Institute of Electro-Optical Engineering, & Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan. E-mail address: [email protected] (T.-C. Chang). 0040-6090/$ – see front matter © 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.tsf.2012.10.095
display operation causes data signal variation and further results in the blinking phenomenon known as the kick-back effect [14]. With asymmetrically structured TFTs being widely employed in practical applications to minimize this kick-back effect, the degradations of an asymmetric device after hot-carrier stress are worthy of further investigation [15,16]. 2. Experiment The n-type a-IGZO TFTs were prepared with a bottom gate and back-channel-etching (BCE) structure. The gate metal and gate insulator layer were Ti/Al/Ti (50/200/50 nm) and SiOx (300 nm), respectively. An a-IGZO active layer was deposited by a DC-type sputtering system with a target of In2O3:Ga2O3:ZnO=1:1:1 atomic ratio and then patterned. The S/D electrode of Mo/Al/Ti was sequentially deposited and then patterned. In this study, symmetric and asymmetric structures are employed. The source and drain electrodes in the symmetric structure were both patterned in an I-shape, as shown in Fig. 1(b). In the asymmetric structure, one of the source and drain electrode was patterned in a U-shape and the other an I-shape for researching the kick-back effect, as shown in Fig. 1(b). No post-annealing was performed. Finally, the device was coated with non-acryl-based photosensitive organic material (2 μm) as a passivation layer. In this work, the I–V and C–V measurements were performed by an Agilent B1500A semiconductor device analyzer. Measurements were carried out in a darkened vacuum
58
M.-Y. Tsai et al. / Thin Solid Films 528 (2013) 57–60
Fig. 2. The Id–Vg characteristic transfer curves under forward- and reverse-operation modes for the symmetric structure device before and after hot-carrier stress. The solid symbol is forward-operation mode and the open symbol is reverse-operation mode (source and drain interchanged).
Fig. 1. (a) Symmetric and (b) asymmetric TFT structures with source/drain electrodes patterned as I-shape and U-shape.
environment of 1×10−3 Torr atmospheric pressure controlled by a vacuum pump. The device dimensions are width/length=50 μm/4 μm. The threshold voltage is defined as the gate voltage when the normalized drain current (NId = Id × L/W) reaches 1 nA with Vd = 0.5 V, where L and W are channel length and channel width, respectively. All Id–Vg transfer curves shown in this letter are measured with Vd = 10.1 V. In the C–V measurement, CGD (gate-to-drain capacitance) and CGS (gate-to-source capacitance) are measured with 100 k Hz and the AC level at 250 mV. In the CGD measurement, with a floating source, capacitance-measurement-high (CMH) is applied to the gate electrode and drain electrode is connected to capacitance-measurement-low (CML).
degradation under forward- and reverse-operation mode can recover as shown in Fig. 2. The C–V measurement is highly sensitive to the trap state when compared with the I–V characterization, therefore C–V curves are utilized to analyze the hot-carrier stress-induced trap state generation [17], as shown in Fig. 3. The CGD and the CGS represent gate-to-drain capacitance and gate-to-source capacitance, respectively. The CGD curve is measured with a floating source and the CGS curve is measured with a floating drain. In the CGD curve after stress, there is a severe stretch-out and a parallel shift, which is consistent with results obtained from I–V measurements. At the subthreshold region, as Vg increases, the band bends downward, but most of the carriers are captured by the high density trap states shown in the inset of Fig. 3. Since most of the carriers are trapped, it is relatively harder for the channel to form when compared to initial state. Then, as applied gate bias becomes high enough, the capacitance characteristic curve turns to on-state when trap states are occupied and inversion layer is formed. Furthermore, since the CGS curve is measured with a floating drain and carriers inject into channel from the source instead of the drain, it can be observed that the stretch-out phenomenon in CGS curve occurs at higher voltage than CGD. This is because the channel gradually extends from the source to drain during CGS
3. Result and discussion The hot-carrier stress is performed with Vg = 10 V, Vd = 25 V and a grounded source. After 1000 s stress of the symmetric device, only a parallel shift is observed in the Id–Vg transfer curve in the saturation region under forward-operation mode, as shown in Fig. 2. However, under reverse-operation mode (with source/drain interchanged), on-current degradation occurs in addition to a Vt shift in the Id–Vg curve measured in the saturation region. The degradation phenomena under different operation modes show that the hot-carrier induced trap state generation is near the drain side. Since the trap states are depleted by high drain bias under forward-operation, on-current (Ion) degradation in the saturation region cannot be observed under forward-operation. Under reverse-operation mode, on the other hand, the trap states can affect Ion due to the interchanged source and drain. As shown in Fig. 2, characteristic degradation behavior under reverseoperation includes a decrease in maximum Ion and a distortion at the subthreshold region. The lower maximum Ion can be ascribed to the trap states-induced mobility degradation; nevertheless, mobility degradation is not solely sufficient to explain the distortion. After the recovery phase (Vgs = Vds = 0 V) for 1000 s, both the Vt shift and S.S.
Fig. 3. Gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) characteristic curves for symmetric device before and after stress. The insets show the energy band diagrams with Fermi-level at and above the trap state level, respectively.
M.-Y. Tsai et al. / Thin Solid Films 528 (2013) 57–60
measurement, and distortion can take place only when the channel reaches the trap states near the drain side. The high density trap states also cause the subthreshold region degradation in the Id–Vg curve. Under reverse-operation mode, the trap states are not depleted by drain bias, causing the channel formation to be more difficult at the subthreshold region, which is similar to the results found in the C–V curves. In TFTs which act as switching devices in LCD and OLED panels, parasitical capacitance originates from the overlapped gate and drain inducing the kick-back effect. Asymmetric source/drain electrode TFT structures can be employed to solve this problem by reducing the overlap of gate and drain. As shown in Fig. 4, the hot-carrier stress is performed with I-shaped source and U-shaped drain, and vice versa. The stress bias condition is Vg = 10 V, Vd = 25 V and Vs =0 V. After 1000 s stress of devices with an I-shaped source and a U-shaped drain, the degradation behaviors of Id–Vg transfer curves are quite similar to the results of the symmetric structure. Only a parallel shift is observed under forward-operation mode, and on-current degradation and a distortion at subthreshold region occur under reverse-operation mode. These measurement results indicate that the degradation behavior can also be attributed to trap state generation near the drain side. Fig. 5 shows the capacitance–voltage characteristics at initial state and after stress. The parasitical capacitance values of CGD and CGS at off-state are different, with CGD (0.53 pF) higher than CGS (0.49 pF), which is caused by the different gate/drain and gate/source overlap areas. Despite the fact that off-state capacitances are different, onstate capacitances are identical owing to the same channel area. The results obtained from CGD and CGS characteristic curves after stress are also consistent with the symmetric structure. In the CGD curve, a severe stretch-out phenomenon and parallel shift can be observed. Due to the fact that most of the carriers are trapped by high density trap state at the transitional region, it is harder for the channel to form and as Vg increases, the capacitance characteristic curve rises gradually until the Fermi level, which becomes higher than the trap states in the energy band. In addition, the stretch-out phenomenon occurs at larger Vg in the CGS curve because carriers inject into the channel from the source in the CGS measurement, and degradation occurs at higher gate bias. Since parasitical capacitance originates from the overlap of gate and drain, to achieve a smaller parasitical capacitance, the I-shaped electrode must be designated as the drain. In this case, the hot-carrier effect is compared with that of the U-shaped drain structure. The hot-carrier stress is performed under identical conditions, and the results are shown in Fig. 6, with the Id–Vg curve under forwardoperation mode exhibiting a parallel shift caused by electron trapping. Furthermore, the parallel shift is more pronounced under reverse-
Fig. 4. The Id–Vg characteristic transfer curves under forward- and reverse-operation modes for asymmetric structure device with U-shaped drain and I-shaped source before and after hot-carrier stress. The solid symbol is forward-operation mode and the open symbol is reverse-operation mode (source and drain interchanged).
59
Fig. 5. The characteristic curves of gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) for asymmetric device with U-shaped drain and I-shaped source before and after hot-carrier stress.
operation mode, which can be ascribed to more evident electrontrapping at the IGZO/gate dielectric interface or within the gate dielectric layer. From these results, it can be deduced that channel-hot-electron injected into the IGZO/gate dielectric interface or gate dielectric layer near the drain side dominates the Vt instability. With the channelhot-electron injected near the drain side, the barrier height for carriers to inject into channel is higher under reverse-operation than forwardoperation. In addition, the barrier height is partially depleted by drain bias under the forward-operation mode, and therefore the Id–Vg curve shows a less significant parallel shift when compared to that under reverse-operation. From these phenomena, it can be deduced that a higher electric field is generated when the I-shaped electrode is designated as the drain. This is due to the denser electric field lines near the I-shaped drain than those near the U-shaped drain. To further analyze the origin responsible for this phenomenon, capacitance–voltage measurement is carried out, as shown in Fig. 7, with results consistent with Id–Vg measurements. The more severe parallel shift in the CGD and the two-stage capacitance characteristic curve in the CGS are due to more electrons injecting into the IGZO/gate dielectric layer interface or gate dielectric layer near the drain. In the CGD, the carriers inject into channel from the drain, and higher gate bias is needed to reduce the barrier height generated by channel-hot-electron injection. Nevertheless, only the channel portion of the barrier near the drain has risen. In the CGS, carriers inject into channel from the source, and the barrier height near the
Fig. 6. The Id–Vg characteristic transfer curves under forward- and reverse-operation modes for asymmetric structure device with I-shaped drain and U-shaped source before and after hot-carrier stress. The solid symbol is forward-operation mode and the open symbol is reverse-operation mode (source and drain interchanged).
60
M.-Y. Tsai et al. / Thin Solid Films 528 (2013) 57–60
In contrast, for the device with an I-shaped drain and U-shaped source, due to the edge effect inducing a higher electric field near the I-shaped drain, pronounced channel-hot-electron trapped near the drain dominate the degradation. Moreover, the C–V measurement results strongly support the proposed mechanism.
Acknowledgment This work was performed at National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in KaohsiungPingtung area, and assisted by AU Optronics. The authors would like to acknowledge the financial support of the National Science Council of the Republic of China under contract no. NSC 100-2120-M-110-003.
References Fig. 7. The characteristic curves of gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) for asymmetric device with I-shaped drain and U-shaped source before and after hot-carrier stress.
drain side does not influence the CGS characteristic at first and CGS rises sharply. At the second stage, the CGS is kept at a certain level because the channel extension is blocked by extra electron trapping-induced barrier height near the drain side. Therefore, pronounced electrontrapping near the drain side results in the two-staged rise in capacitance characteristic curves. 4. Conclusion In this work, hot-carrier effects on symmetric and asymmetric InGaZnO thin-film transistors are investigated. The symmetric device shows Ion degradation and subthreshold region stretch-out in Id–Vg transfer curves under reverse-operation mode after stress. This phenomenon is due to trap state generation near the drain side, and the proposed mechanism can be further verified by capacitance–voltage measurement. The same hot-carrier stress condition leads to different degradation behaviors on asymmetric devices depending on the designation of source and drain. For the device with U-shaped drain and I-shaped source, the obtained results resemble those for the symmetric device. By analyzing Id–Vg and the C–V characteristic curves, the degradation mechanism can be ascribed to trap state generation near the drain side.
[1] Kenji Nomura, Hiromichi Ohta, Akihiro Takagi, Toshio Kamiya, Masahiro Hirano, Hideo Hosono, Nature 432 (2004) 488. [2] W.F. Chung, T.C. Chang, H.W. Li, C.W. Chen, Y.C. Chen, S.C. Chen, T.Y. Tseng, Y.H. Tai, Electrochem. Solid State Lett. 14 (3) (2011) H114. [3] Hisato Yabuta, Masafumi Sano, Katsumi Abe, Toshiaki Aiba, Tohru Den, Hideya Kumomi, Appl. Phys. Lett. 89 (2006) 112123. [4] Sunho Jeong, Young-Geun Ha, Jooho Moon, Antonio Facchetti, Tobin J. Marks, Adv. Mater. 22 (2010) 1346. [5] M.C. Chen, T.C. Chang, S.Y. Huang, K.C. Chang, H.W. Li, S.C. Chen, J. Lu, Y. Shi, Appl. Phys. Lett. 94 (2009) 162111. [6] M.C. Chen, T.C. Chang, S.Y. Huang, S.C. Chen, C.W. Hu, C.T. Tsai, Simon M. Sze, Electrochem. Solid State Lett. 13 (6) (2010) H191. [7] M.C. Chen, T.C. Chang, C.T. Tsai, S.Y. Huang, S.C. Chen, C.W. Hu, S.M. Sze, M.J. Tsai, Appl. Phys. Lett. 96 (2010) 262110. [8] T.C. Chang, F.Y. Jian, S.C. Chen, Y.T. Tsai, Mater. Today 14 (12) (2011) 608. [9] C.T. Tsai, T.C. Chang, S.C. Chen, I. Lo, S.W. Tsao, M.C. Hung, J.J. Chang, C.Y. Wu, C.Y. Huang, Appl. Phys. Lett. 96 (2010) 242105. [10] T.C. Chen, T.C. Chang, T.Y. Hsieh, C.T. Tsai, S.C. Chen, C.S. Lin, M.C. Hung, C.H. Tu, J.J. Chang, P.L. Chen, Appl. Phys. Lett. 97 (2010) 192103. [11] T.C. Chen, T.C. Chang, C.T. Tsai, T.Y. Hsieh, S.C. Chen, C.S. Lin, M.C. Hung, C.H. Tu, J.J. Chang, P.L. Chen, Appl. Phys. Lett. 97 (2010) 112104. [12] Y.C. Chen, T.C. Chang, H.W. Li, S.C. Chen, J. Lu, W.F. Chung, Y.H. Tai, T.Y. Tseng, Appl. Phys. Lett. 96 (2010) 262104. [13] W.F. Chung, T.C. Chang, H.W. Li, S.C. Chen, Y.C. Chen, T.Y. Tseng, Y.H. Tai, Appl. Phys. Lett. 98 (2011) 152109. [14] Bing J. Sheu, Chenming Hu, IEEE J. Solid State Circuits SC-19 (4) (1984) 519. [15] Yue Kuo, J. Electrochem. Soc. 143 (8) (1996) 2680. [16] Yue Kuo, Thin Film Transistors: Amorphous silicon thin film transistors (Kluwer Academic Publishers), pp 183–201. [17] Kook Chul Moon, Jae-Hoon Lee, Min-Koo Han, IEEE Trans. Electron Dev. 52 (4) (2005) 512.
Contents lists available at SciVerse ScienceDirect
Thin Solid Films journal homepage: www.elsevier.com/locate/tsf
Investigating the degradation behavior under hot carrier stress for InGaZnO TFTs with symmetric and asymmetric structures Ming-Yen Tsai a, Ting-Chang Chang b, c,⁎, Ann-Kuo Chu a, Te-Chih Chen b, Tien-Yu Hsieh b, Yu-Te Chen a, Wu-Wei Tsai d, Wen-Jen Chiang d, Jing-Yi Yan d a
Department of Photonics, National Sun Yat-Sen University, 70 Lien-hai Road, Kaohsiung 80424, Taiwan Department of Physics and Institute of Electro-Optical Engineering, & Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan d Industrial Technology Research Institute, 195, Sec. 4, Chung Hsing Rd., Hsinchu, 31040, Taiwan b c
a r t i c l e
i n f o
Available online 6 November 2012 Keywords: Indium gallium zinc oxide (IGZO) Thin film transistors (TFTs) Hot-carrier Kick-back effect
a b s t r a c t This letter studies the hot-carrier effect in indium–gallium–zinc oxide (IGZO) thin film transistors with symmetric and asymmetric source/drain structures. The different degradation behaviors after hot-carrier stress in symmetric and asymmetric source/drain devices indicate that different mechanisms dominate the degradation. Since the C–V measurement is highly sensitive to trap states compared to the I–V characterization, C–V curves are utilized to analyze the hot-carrier stress-induced trap state generation. Furthermore, the asymmetric C–V measurements CGD (gate-to-drain capacitance) and CGS (gate-to-source capacitance) are used to analyze the trap state in channel location. The asymmetric source/drain structure under hot-carrier stress induces an asymmetric electrical field and causes different degradation behaviors. In this work, the on-current and subthreshold swing (S.S.) degrade under low electrical field, whereas an apparent Vt shift occurs under large electrical field. The different degradation behaviors indicate that trap states are generated under a low electrical field and the channel-hot-electron (CHE) effect occurs under a large electrical field. © 2012 Elsevier B.V. All rights reserved.
1. Introduction Amorphous indium–gallium–zinc-oxide (a-IGZO) thin film transistors (TFTs) have attracted much attention for active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs) due to their high electron mobility (>10 cm2/Vs), high transparency to visible light and low-temperature process [1–5]. Furthermore, amorphous oxide semiconductor-based materials are also expected to be adopted as nonvolatile memory devices [6–8]. Among a variety of amorphous oxide semiconductors, a-IGZO TFTs are thought to be the most promising for practical applications. Although zinc-oxide based TFTs have shown excellent performance, they still have reliability issues such as instability under light illumination and bias stress in different ambient gases [9–13]. TFTs play an important role in AMLCDs and AMOLEDs, and therefore the effect of hot-carriers on TFT reliability is worthy of study. Pixel circuits in AMLCDs are composed of a switching TFT, a storage capacitor and a liquid crystal capacitor. The parasitical capacitor across the switching TFT gate and drain, however, can affect the amount of stored charge in the storage capacitor. The fluctuation of stored charges during ⁎ Corresponding author at: Department of Physics and Institute of Electro-Optical Engineering, & Center for Nanoscience and Nanotechnology, National Sun Yat-Sen University, Kaohsiung, 804, Taiwan. E-mail address: [email protected] (T.-C. Chang). 0040-6090/$ – see front matter © 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.tsf.2012.10.095
display operation causes data signal variation and further results in the blinking phenomenon known as the kick-back effect [14]. With asymmetrically structured TFTs being widely employed in practical applications to minimize this kick-back effect, the degradations of an asymmetric device after hot-carrier stress are worthy of further investigation [15,16]. 2. Experiment The n-type a-IGZO TFTs were prepared with a bottom gate and back-channel-etching (BCE) structure. The gate metal and gate insulator layer were Ti/Al/Ti (50/200/50 nm) and SiOx (300 nm), respectively. An a-IGZO active layer was deposited by a DC-type sputtering system with a target of In2O3:Ga2O3:ZnO=1:1:1 atomic ratio and then patterned. The S/D electrode of Mo/Al/Ti was sequentially deposited and then patterned. In this study, symmetric and asymmetric structures are employed. The source and drain electrodes in the symmetric structure were both patterned in an I-shape, as shown in Fig. 1(b). In the asymmetric structure, one of the source and drain electrode was patterned in a U-shape and the other an I-shape for researching the kick-back effect, as shown in Fig. 1(b). No post-annealing was performed. Finally, the device was coated with non-acryl-based photosensitive organic material (2 μm) as a passivation layer. In this work, the I–V and C–V measurements were performed by an Agilent B1500A semiconductor device analyzer. Measurements were carried out in a darkened vacuum
58
M.-Y. Tsai et al. / Thin Solid Films 528 (2013) 57–60
Fig. 2. The Id–Vg characteristic transfer curves under forward- and reverse-operation modes for the symmetric structure device before and after hot-carrier stress. The solid symbol is forward-operation mode and the open symbol is reverse-operation mode (source and drain interchanged).
Fig. 1. (a) Symmetric and (b) asymmetric TFT structures with source/drain electrodes patterned as I-shape and U-shape.
environment of 1×10−3 Torr atmospheric pressure controlled by a vacuum pump. The device dimensions are width/length=50 μm/4 μm. The threshold voltage is defined as the gate voltage when the normalized drain current (NId = Id × L/W) reaches 1 nA with Vd = 0.5 V, where L and W are channel length and channel width, respectively. All Id–Vg transfer curves shown in this letter are measured with Vd = 10.1 V. In the C–V measurement, CGD (gate-to-drain capacitance) and CGS (gate-to-source capacitance) are measured with 100 k Hz and the AC level at 250 mV. In the CGD measurement, with a floating source, capacitance-measurement-high (CMH) is applied to the gate electrode and drain electrode is connected to capacitance-measurement-low (CML).
degradation under forward- and reverse-operation mode can recover as shown in Fig. 2. The C–V measurement is highly sensitive to the trap state when compared with the I–V characterization, therefore C–V curves are utilized to analyze the hot-carrier stress-induced trap state generation [17], as shown in Fig. 3. The CGD and the CGS represent gate-to-drain capacitance and gate-to-source capacitance, respectively. The CGD curve is measured with a floating source and the CGS curve is measured with a floating drain. In the CGD curve after stress, there is a severe stretch-out and a parallel shift, which is consistent with results obtained from I–V measurements. At the subthreshold region, as Vg increases, the band bends downward, but most of the carriers are captured by the high density trap states shown in the inset of Fig. 3. Since most of the carriers are trapped, it is relatively harder for the channel to form when compared to initial state. Then, as applied gate bias becomes high enough, the capacitance characteristic curve turns to on-state when trap states are occupied and inversion layer is formed. Furthermore, since the CGS curve is measured with a floating drain and carriers inject into channel from the source instead of the drain, it can be observed that the stretch-out phenomenon in CGS curve occurs at higher voltage than CGD. This is because the channel gradually extends from the source to drain during CGS
3. Result and discussion The hot-carrier stress is performed with Vg = 10 V, Vd = 25 V and a grounded source. After 1000 s stress of the symmetric device, only a parallel shift is observed in the Id–Vg transfer curve in the saturation region under forward-operation mode, as shown in Fig. 2. However, under reverse-operation mode (with source/drain interchanged), on-current degradation occurs in addition to a Vt shift in the Id–Vg curve measured in the saturation region. The degradation phenomena under different operation modes show that the hot-carrier induced trap state generation is near the drain side. Since the trap states are depleted by high drain bias under forward-operation, on-current (Ion) degradation in the saturation region cannot be observed under forward-operation. Under reverse-operation mode, on the other hand, the trap states can affect Ion due to the interchanged source and drain. As shown in Fig. 2, characteristic degradation behavior under reverseoperation includes a decrease in maximum Ion and a distortion at the subthreshold region. The lower maximum Ion can be ascribed to the trap states-induced mobility degradation; nevertheless, mobility degradation is not solely sufficient to explain the distortion. After the recovery phase (Vgs = Vds = 0 V) for 1000 s, both the Vt shift and S.S.
Fig. 3. Gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) characteristic curves for symmetric device before and after stress. The insets show the energy band diagrams with Fermi-level at and above the trap state level, respectively.
M.-Y. Tsai et al. / Thin Solid Films 528 (2013) 57–60
measurement, and distortion can take place only when the channel reaches the trap states near the drain side. The high density trap states also cause the subthreshold region degradation in the Id–Vg curve. Under reverse-operation mode, the trap states are not depleted by drain bias, causing the channel formation to be more difficult at the subthreshold region, which is similar to the results found in the C–V curves. In TFTs which act as switching devices in LCD and OLED panels, parasitical capacitance originates from the overlapped gate and drain inducing the kick-back effect. Asymmetric source/drain electrode TFT structures can be employed to solve this problem by reducing the overlap of gate and drain. As shown in Fig. 4, the hot-carrier stress is performed with I-shaped source and U-shaped drain, and vice versa. The stress bias condition is Vg = 10 V, Vd = 25 V and Vs =0 V. After 1000 s stress of devices with an I-shaped source and a U-shaped drain, the degradation behaviors of Id–Vg transfer curves are quite similar to the results of the symmetric structure. Only a parallel shift is observed under forward-operation mode, and on-current degradation and a distortion at subthreshold region occur under reverse-operation mode. These measurement results indicate that the degradation behavior can also be attributed to trap state generation near the drain side. Fig. 5 shows the capacitance–voltage characteristics at initial state and after stress. The parasitical capacitance values of CGD and CGS at off-state are different, with CGD (0.53 pF) higher than CGS (0.49 pF), which is caused by the different gate/drain and gate/source overlap areas. Despite the fact that off-state capacitances are different, onstate capacitances are identical owing to the same channel area. The results obtained from CGD and CGS characteristic curves after stress are also consistent with the symmetric structure. In the CGD curve, a severe stretch-out phenomenon and parallel shift can be observed. Due to the fact that most of the carriers are trapped by high density trap state at the transitional region, it is harder for the channel to form and as Vg increases, the capacitance characteristic curve rises gradually until the Fermi level, which becomes higher than the trap states in the energy band. In addition, the stretch-out phenomenon occurs at larger Vg in the CGS curve because carriers inject into the channel from the source in the CGS measurement, and degradation occurs at higher gate bias. Since parasitical capacitance originates from the overlap of gate and drain, to achieve a smaller parasitical capacitance, the I-shaped electrode must be designated as the drain. In this case, the hot-carrier effect is compared with that of the U-shaped drain structure. The hot-carrier stress is performed under identical conditions, and the results are shown in Fig. 6, with the Id–Vg curve under forwardoperation mode exhibiting a parallel shift caused by electron trapping. Furthermore, the parallel shift is more pronounced under reverse-
Fig. 4. The Id–Vg characteristic transfer curves under forward- and reverse-operation modes for asymmetric structure device with U-shaped drain and I-shaped source before and after hot-carrier stress. The solid symbol is forward-operation mode and the open symbol is reverse-operation mode (source and drain interchanged).
59
Fig. 5. The characteristic curves of gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) for asymmetric device with U-shaped drain and I-shaped source before and after hot-carrier stress.
operation mode, which can be ascribed to more evident electrontrapping at the IGZO/gate dielectric interface or within the gate dielectric layer. From these results, it can be deduced that channel-hot-electron injected into the IGZO/gate dielectric interface or gate dielectric layer near the drain side dominates the Vt instability. With the channelhot-electron injected near the drain side, the barrier height for carriers to inject into channel is higher under reverse-operation than forwardoperation. In addition, the barrier height is partially depleted by drain bias under the forward-operation mode, and therefore the Id–Vg curve shows a less significant parallel shift when compared to that under reverse-operation. From these phenomena, it can be deduced that a higher electric field is generated when the I-shaped electrode is designated as the drain. This is due to the denser electric field lines near the I-shaped drain than those near the U-shaped drain. To further analyze the origin responsible for this phenomenon, capacitance–voltage measurement is carried out, as shown in Fig. 7, with results consistent with Id–Vg measurements. The more severe parallel shift in the CGD and the two-stage capacitance characteristic curve in the CGS are due to more electrons injecting into the IGZO/gate dielectric layer interface or gate dielectric layer near the drain. In the CGD, the carriers inject into channel from the drain, and higher gate bias is needed to reduce the barrier height generated by channel-hot-electron injection. Nevertheless, only the channel portion of the barrier near the drain has risen. In the CGS, carriers inject into channel from the source, and the barrier height near the
Fig. 6. The Id–Vg characteristic transfer curves under forward- and reverse-operation modes for asymmetric structure device with I-shaped drain and U-shaped source before and after hot-carrier stress. The solid symbol is forward-operation mode and the open symbol is reverse-operation mode (source and drain interchanged).
60
M.-Y. Tsai et al. / Thin Solid Films 528 (2013) 57–60
In contrast, for the device with an I-shaped drain and U-shaped source, due to the edge effect inducing a higher electric field near the I-shaped drain, pronounced channel-hot-electron trapped near the drain dominate the degradation. Moreover, the C–V measurement results strongly support the proposed mechanism.
Acknowledgment This work was performed at National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in KaohsiungPingtung area, and assisted by AU Optronics. The authors would like to acknowledge the financial support of the National Science Council of the Republic of China under contract no. NSC 100-2120-M-110-003.
References Fig. 7. The characteristic curves of gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) for asymmetric device with I-shaped drain and U-shaped source before and after hot-carrier stress.
drain side does not influence the CGS characteristic at first and CGS rises sharply. At the second stage, the CGS is kept at a certain level because the channel extension is blocked by extra electron trapping-induced barrier height near the drain side. Therefore, pronounced electrontrapping near the drain side results in the two-staged rise in capacitance characteristic curves. 4. Conclusion In this work, hot-carrier effects on symmetric and asymmetric InGaZnO thin-film transistors are investigated. The symmetric device shows Ion degradation and subthreshold region stretch-out in Id–Vg transfer curves under reverse-operation mode after stress. This phenomenon is due to trap state generation near the drain side, and the proposed mechanism can be further verified by capacitance–voltage measurement. The same hot-carrier stress condition leads to different degradation behaviors on asymmetric devices depending on the designation of source and drain. For the device with U-shaped drain and I-shaped source, the obtained results resemble those for the symmetric device. By analyzing Id–Vg and the C–V characteristic curves, the degradation mechanism can be ascribed to trap state generation near the drain side.
[1] Kenji Nomura, Hiromichi Ohta, Akihiro Takagi, Toshio Kamiya, Masahiro Hirano, Hideo Hosono, Nature 432 (2004) 488. [2] W.F. Chung, T.C. Chang, H.W. Li, C.W. Chen, Y.C. Chen, S.C. Chen, T.Y. Tseng, Y.H. Tai, Electrochem. Solid State Lett. 14 (3) (2011) H114. [3] Hisato Yabuta, Masafumi Sano, Katsumi Abe, Toshiaki Aiba, Tohru Den, Hideya Kumomi, Appl. Phys. Lett. 89 (2006) 112123. [4] Sunho Jeong, Young-Geun Ha, Jooho Moon, Antonio Facchetti, Tobin J. Marks, Adv. Mater. 22 (2010) 1346. [5] M.C. Chen, T.C. Chang, S.Y. Huang, K.C. Chang, H.W. Li, S.C. Chen, J. Lu, Y. Shi, Appl. Phys. Lett. 94 (2009) 162111. [6] M.C. Chen, T.C. Chang, S.Y. Huang, S.C. Chen, C.W. Hu, C.T. Tsai, Simon M. Sze, Electrochem. Solid State Lett. 13 (6) (2010) H191. [7] M.C. Chen, T.C. Chang, C.T. Tsai, S.Y. Huang, S.C. Chen, C.W. Hu, S.M. Sze, M.J. Tsai, Appl. Phys. Lett. 96 (2010) 262110. [8] T.C. Chang, F.Y. Jian, S.C. Chen, Y.T. Tsai, Mater. Today 14 (12) (2011) 608. [9] C.T. Tsai, T.C. Chang, S.C. Chen, I. Lo, S.W. Tsao, M.C. Hung, J.J. Chang, C.Y. Wu, C.Y. Huang, Appl. Phys. Lett. 96 (2010) 242105. [10] T.C. Chen, T.C. Chang, T.Y. Hsieh, C.T. Tsai, S.C. Chen, C.S. Lin, M.C. Hung, C.H. Tu, J.J. Chang, P.L. Chen, Appl. Phys. Lett. 97 (2010) 192103. [11] T.C. Chen, T.C. Chang, C.T. Tsai, T.Y. Hsieh, S.C. Chen, C.S. Lin, M.C. Hung, C.H. Tu, J.J. Chang, P.L. Chen, Appl. Phys. Lett. 97 (2010) 112104. [12] Y.C. Chen, T.C. Chang, H.W. Li, S.C. Chen, J. Lu, W.F. Chung, Y.H. Tai, T.Y. Tseng, Appl. Phys. Lett. 96 (2010) 262104. [13] W.F. Chung, T.C. Chang, H.W. Li, S.C. Chen, Y.C. Chen, T.Y. Tseng, Y.H. Tai, Appl. Phys. Lett. 98 (2011) 152109. [14] Bing J. Sheu, Chenming Hu, IEEE J. Solid State Circuits SC-19 (4) (1984) 519. [15] Yue Kuo, J. Electrochem. Soc. 143 (8) (1996) 2680. [16] Yue Kuo, Thin Film Transistors: Amorphous silicon thin film transistors (Kluwer Academic Publishers), pp 183–201. [17] Kook Chul Moon, Jae-Hoon Lee, Min-Koo Han, IEEE Trans. Electron Dev. 52 (4) (2005) 512.