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Bipolar transistor degradation under dynamic hot carrier stress
Pergamon
0038-1101(94)00184-7
Solid-Sum Ekrronics Vol. 38. No. 4, pp. 717-789. 1995 Copyright s(‘ 1995 Elsewer Science Ltd Printed in Great Britain. All rights reserved 0038.1101/95
BIPOLAR TRANSISTOR DYNAMIC HOT TADAHIKO
HORIUCHIt,
X.9.50+0.00
DEGRADATION UNDER CARRIER STRESS
J. DAVID
BURNETT
and CHENMING
HU
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, U.S.A. (Received
9 June 1994; in revised form
5 August
1994)
Abstract-Hot carrier induced bipolar transistor degradation under dynamic stress is studied. The model, Ala cc (Ik*r)05 , established from d.c. emitter-base reverse bias stress measurements is found to be still valid under pulse stress down to 20 ns pulse width, where AI, is drift of base current, IR is reverse emitter-base current under stress and t is stress time. Although partial degradation recovery is observed under d.c. emitter-base forward bias, AIa from alternating reverse-forward stress representative BiCMOS circuit operation agrees with the Al, model with no significant recovery effect. This is explained by a higher degradation rate after recovery of previous damage. An experimental basis of BiCMOS circuit reliability testing simulation is thus provided.
I. INTRODUCTION
BiCMOS technology has many advantages over CMOS in areas of high speed applications, such as high speed SRAM[l]. However, a BiCMOS gate has a specific reliability problem in bipolar which does not appear in an ECL gate. As shown in Fig. 1, a pull-up bipolar transistor in a BiCMOS gate is subjected to the reverse-biased emitter-base bias at the pull-down transient. Hot carriers are generated in the reverse-biased emitter-base junction and are injected into the oxide overlaying the emitter-base depletion layer. The hot carriers create interface traps or trapped charge which induce /I degradation through an increase in the base leakage current. If we intend to avoid the emitter-base reverse bias by reducing the transistor width of MN3 in Fig. 1, the BiCMOS gate operates with large short current passing through NPNl and NPN2. This is because both NPNI and NPN2 are “ON” at the pull-down transient. The short current induces the increase in power dissipation and the decrease in gate speed. Accordingly, BiCMOS circuit design forces NPNI into the reverse emitter-base bias condition at the pull-down transient. This means that the reliability problems due to hot carrier stressing is the essentially important issues for BiCMOS LSIs. From the reason mentioned above, bipolar hot carrier effects have been extensively investigated in previous works[2-71. However, little is known about bipolar transistor degradation due to dynamic stressing, which is the condition that occurs in actual
ton
leave from NEC Corporation. II20 Shimokuzawa. Sagamihara, Kanagawa 229. Japan.
BiCMOS circuits. The purpose of this paper is to provide an experimental basis of simple reliability testing and simulation of BiCMOS devices. In this paper, the effect of two types of dynamic stress are described. One is the effect of reverse-bias pulses, only. Another is that of bi-directional pulses; the emitter-base is alternatively biased in the forward and reverse directions.
2.
EXPERIMENT
The npn bipolar transistors used in this study were fabricated by a self-aligned polysilicon emitter process[4]. The key processing steps are: (i) starting wafers of an n-type epitaxial layer of 0.5 R cm resistivity and of 2-3 pm thickness grown on an 11+ substrate; (ii) transistor region defined by etching the field oxide; (iii) extrinsic base formed by LOCOS process. (After a thin pad oxide is grown and a layer of silicon nitride is deposited and etched to define the extrinsic area of the transistor, the extrinsic base implant is performed. During the drive-in of the extrinsic base, an oxide is grown.); (iv) intrinsic base implant after removing the nitride and pad oxide over active area; (v) polysilicon emitter. The degree of damage by hot carrier stress was monitored as an increase in the base current with the base grounded and V,-, = 2 V. The constant voltage stress pulse was applied to the base electrode with emitter grounded and VCE= 3 V. If not indicated, the drawn emitter size of tested bipolar transistor in this paper is 2 x 12fim. The impedance throughout the pulse feed line was carefully matched to 50R using resistor terminated wafer probe. The voltage overshoot is kept within 5% of applied pulse height for 15 ns rise and fall time 787
788
Tadahiko
Horiuchi
et al.
period time
fh i } 20nS,
1OOn.S
l
50nS,
100nS
.
5ps,
IO+3
.
5p.3,
6pS
10“
I -
I
MODEL
TIME Fig. 1. Time transient of the base and emitter potential and the emitter-base bias of NPNI indicated in the inset.
used in this study. The base current during the pulsed reverse stress and forward bias was represented by d.c. value at the same emitter-base bias. 1O“O IO’
3. RESULTS AND DISCUSSIONS
Figure 2 shows the typical degradation observed in d.c. measurements. As shown in Fig. 2, the increase in the base current, AIa, follows the model developed in the literature[4,5], in which AIs is expressed as: AI, = DJ;Ih,t’.
I
1
-
MODEL
0 IO-lo IO’
I IO2
l
Jc=lO‘“A/um*
A Jc=l Ow7A/um2 8,,#,,,,1 I I,,,,, IO3
lo4
STRESS TIME [S] Fig. 2. Comparison
0 Jc=l O“A/um’ I 111,,,,1 I ,I I,,,
102
103
104
N-h [S] Fig. 3. Al, under pulse stress, where t, and N are the reversed pulse width and the number of the stress pulse. I, = 200 nA for V, = 4.0 V and 640 nA for VR = 4.3 V, respectively.
(1)
with the typical values being D = I .2, a = 0.6, b = 0.9 and c = 0.5, where t(s) is the stress time, I,(A) is the reverse stress current and Jc(A/pm2) is the collector current density at which AI,(A) is measured. The parameters 4, b, c and D are determined by the dynamics of damage creation, the non-local high field effect and the physical device dimensions of a bipolar transistor[5].
10.’
I
of the A/s model and experimental for d.c. stress.
data
(I) is the starting point of the following dynamic measurement. If we assume no enhanced or suppressed degradation under dynamic stress compared with that under static stress. (I) can be simply extended as[7]: AIs = DJ;I;(NtR)(,
(2)
where N is the number of pulse cycles and tR is the stress pulse width. Figure 3 shows the comparison of experiments and the model based on (2). Under dynamic stress with pulse widths down to 20ns, the Ata model, (2) is approximately valid for different values of Va and J,-, where Va is reverse emitter-base voltage at stress. Because emitter-base forward biasing results in the recovery of degradation[3,6] which causes decrease in the Als, the degradation model may need to include the recovery effects for modeling devices that undergo reverse and forward biases. Figure 4 shows the AI, recovery caused by d.c. forward emitter-base bias applied after d.c. stress. Rapid and significant recovery after applying the bias was observed. The degree of recovery saturates after a long forward bias time. However, it should also be taken into consideration that the recovered emitter-base junction has a higher re-degradation rate than that in the initial state. Figure 5 shows the AIs through a reverseforward-reverse bias sequence. After recovery, Ala degrades at a higher rate in the second reverse bias
789
BJT degradation under dynamic hot carrier stress
1.0
I
I
1
REVERSE
STRESS TIME =
1
Jc=l 0-6Num2
OJ 10’
lo2
lo4
lo3
FORWARD BIAS TIME [S]
10'
Fig. 4. Degradation recovery ratio of AI, after forward emitter-base bias to initial AI, before forward biasing. After d.c. stress (I’, = 4.3 V), forward bias ( Vbe= I .5 V, V, = 3 V, Jc = 5.8 x 10m5A) was applied. The closed symbols indicate the recovery ratio at the time when forward bias time equals reverse stress time.
stress and catches up with the extrapolated line of the initial AIs. One possible explanation is that the recovery process involves passivating the interface traps. This passivation effect, whose chemical nature is unknown, can be reversed easily by subsequent stressing. In order to simulate the stress condition of a bipolar transistor in a BiCMOS gate, an alternating forward and reverse bias pulse train was applied to the emitter-base of the bipolar transistors. The predicted AIs and 60% (from Fig. 5) of that are plotted in Fig. 6. The experimental values of AI, agree well with (2) the model without recovery effects, indicating that no significant recovery effects can be seen after the alternating bias stress. The bipolar reliability
c
’
1o-‘Ol IO2
IO3
IO4
N.~R [S] Fig. 6. AIa due to the alternating pulse train representatives of BiCMOS gate operation. The solid line indicates the model without recovery effect, eqn (2) at /a = I .06 PA. The dashed line indicates the model including recovery effect (from Fig. 4, recovery rate 60% was used). in a BiCMOS circuit can be estimated boundary given by (2).
by worst-case
4. SUMMARY In this study, we experimentally showed that the AI,, model, AZg= DJcIh,(NtR)(, is valid for the BiCMOS circuit reliability simulation. Enhanced or significantly suppressed degradation from that of d.c. stress was not observed under the pulse reverse stress. The degradation recovery effect which is observed after d.c. forward bias soak does not occur under the alternating reverse-forward bias stress applied in this study. BiCMOS circuit reliability can be estimated by a worst case boundary given by the d.c. stress AIs model and the stress duty factor.
I
I
after forward bias
Acknowledgements-This work was partially supported by SRC and by Hewlett Packard under University of California MICRO program.
REFERENCES
before forward bias Jc=l 0AgA/um2
LLlll
I
I ,#,I
I I1
3
1o2
STRESS TiE
[S]
Fig. 5. Effect of a forward bias ( Vk = 0.82 V, V,, = 2 V) in the middle of reverse bias stress (V, =4.5 V) for a 4 x 24 pm’ device. The open squares indicate AI, by second reverse bias stress after forward biasing.
I K. Nakamura. S. Kuhara. M. Takada, H. Suzuki. H. Yoshida and T. Yamazaki, in /.SSCC Dig. Tech. Papers, pp. 258-259 (1994). 2. D. D. Tang and E. Hackbarth. IEEE Trans. Electron Devices ED-35, 2101 (1988). 3. S. P. Joshi, R. Lahri and C. Lage, in IEDM Tech. Dig.. pp. 182-185 (1987). 4. J. D. Burnett and C. Hu, IEEE Trans. Electron Devices ED-35, 2238 (1988). 5. D. Burnett and C. Hu, in Proc. IEEE Inr. Rel. Symp.. pp. 164-169 (1990). 6. H. S. Momose, Y. Niitsu, H. Iwai and K. Maeguchi, in Proc. IEEE 1989 Bipolar Circuits Technol. Meet.. p. 140 (1989). 7. J. D. Burnett and C. Hu. IEEE Trans. Electron Devices ED-35, 1171 (1990).
0038-1101(94)00184-7
Solid-Sum Ekrronics Vol. 38. No. 4, pp. 717-789. 1995 Copyright s(‘ 1995 Elsewer Science Ltd Printed in Great Britain. All rights reserved 0038.1101/95
BIPOLAR TRANSISTOR DYNAMIC HOT TADAHIKO
HORIUCHIt,
X.9.50+0.00
DEGRADATION UNDER CARRIER STRESS
J. DAVID
BURNETT
and CHENMING
HU
Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, U.S.A. (Received
9 June 1994; in revised form
5 August
1994)
Abstract-Hot carrier induced bipolar transistor degradation under dynamic stress is studied. The model, Ala cc (Ik*r)05 , established from d.c. emitter-base reverse bias stress measurements is found to be still valid under pulse stress down to 20 ns pulse width, where AI, is drift of base current, IR is reverse emitter-base current under stress and t is stress time. Although partial degradation recovery is observed under d.c. emitter-base forward bias, AIa from alternating reverse-forward stress representative BiCMOS circuit operation agrees with the Al, model with no significant recovery effect. This is explained by a higher degradation rate after recovery of previous damage. An experimental basis of BiCMOS circuit reliability testing simulation is thus provided.
I. INTRODUCTION
BiCMOS technology has many advantages over CMOS in areas of high speed applications, such as high speed SRAM[l]. However, a BiCMOS gate has a specific reliability problem in bipolar which does not appear in an ECL gate. As shown in Fig. 1, a pull-up bipolar transistor in a BiCMOS gate is subjected to the reverse-biased emitter-base bias at the pull-down transient. Hot carriers are generated in the reverse-biased emitter-base junction and are injected into the oxide overlaying the emitter-base depletion layer. The hot carriers create interface traps or trapped charge which induce /I degradation through an increase in the base leakage current. If we intend to avoid the emitter-base reverse bias by reducing the transistor width of MN3 in Fig. 1, the BiCMOS gate operates with large short current passing through NPNl and NPN2. This is because both NPNI and NPN2 are “ON” at the pull-down transient. The short current induces the increase in power dissipation and the decrease in gate speed. Accordingly, BiCMOS circuit design forces NPNI into the reverse emitter-base bias condition at the pull-down transient. This means that the reliability problems due to hot carrier stressing is the essentially important issues for BiCMOS LSIs. From the reason mentioned above, bipolar hot carrier effects have been extensively investigated in previous works[2-71. However, little is known about bipolar transistor degradation due to dynamic stressing, which is the condition that occurs in actual
ton
leave from NEC Corporation. II20 Shimokuzawa. Sagamihara, Kanagawa 229. Japan.
BiCMOS circuits. The purpose of this paper is to provide an experimental basis of simple reliability testing and simulation of BiCMOS devices. In this paper, the effect of two types of dynamic stress are described. One is the effect of reverse-bias pulses, only. Another is that of bi-directional pulses; the emitter-base is alternatively biased in the forward and reverse directions.
2.
EXPERIMENT
The npn bipolar transistors used in this study were fabricated by a self-aligned polysilicon emitter process[4]. The key processing steps are: (i) starting wafers of an n-type epitaxial layer of 0.5 R cm resistivity and of 2-3 pm thickness grown on an 11+ substrate; (ii) transistor region defined by etching the field oxide; (iii) extrinsic base formed by LOCOS process. (After a thin pad oxide is grown and a layer of silicon nitride is deposited and etched to define the extrinsic area of the transistor, the extrinsic base implant is performed. During the drive-in of the extrinsic base, an oxide is grown.); (iv) intrinsic base implant after removing the nitride and pad oxide over active area; (v) polysilicon emitter. The degree of damage by hot carrier stress was monitored as an increase in the base current with the base grounded and V,-, = 2 V. The constant voltage stress pulse was applied to the base electrode with emitter grounded and VCE= 3 V. If not indicated, the drawn emitter size of tested bipolar transistor in this paper is 2 x 12fim. The impedance throughout the pulse feed line was carefully matched to 50R using resistor terminated wafer probe. The voltage overshoot is kept within 5% of applied pulse height for 15 ns rise and fall time 787
788
Tadahiko
Horiuchi
et al.
period time
fh i } 20nS,
1OOn.S
l
50nS,
100nS
.
5ps,
IO+3
.
5p.3,
6pS
10“
I -
I
MODEL
TIME Fig. 1. Time transient of the base and emitter potential and the emitter-base bias of NPNI indicated in the inset.
used in this study. The base current during the pulsed reverse stress and forward bias was represented by d.c. value at the same emitter-base bias. 1O“O IO’
3. RESULTS AND DISCUSSIONS
Figure 2 shows the typical degradation observed in d.c. measurements. As shown in Fig. 2, the increase in the base current, AIa, follows the model developed in the literature[4,5], in which AIs is expressed as: AI, = DJ;Ih,t’.
I
1
-
MODEL
0 IO-lo IO’
I IO2
l
Jc=lO‘“A/um*
A Jc=l Ow7A/um2 8,,#,,,,1 I I,,,,, IO3
lo4
STRESS TIME [S] Fig. 2. Comparison
0 Jc=l O“A/um’ I 111,,,,1 I ,I I,,,
102
103
104
N-h [S] Fig. 3. Al, under pulse stress, where t, and N are the reversed pulse width and the number of the stress pulse. I, = 200 nA for V, = 4.0 V and 640 nA for VR = 4.3 V, respectively.
(1)
with the typical values being D = I .2, a = 0.6, b = 0.9 and c = 0.5, where t(s) is the stress time, I,(A) is the reverse stress current and Jc(A/pm2) is the collector current density at which AI,(A) is measured. The parameters 4, b, c and D are determined by the dynamics of damage creation, the non-local high field effect and the physical device dimensions of a bipolar transistor[5].
10.’
I
of the A/s model and experimental for d.c. stress.
data
(I) is the starting point of the following dynamic measurement. If we assume no enhanced or suppressed degradation under dynamic stress compared with that under static stress. (I) can be simply extended as[7]: AIs = DJ;I;(NtR)(,
(2)
where N is the number of pulse cycles and tR is the stress pulse width. Figure 3 shows the comparison of experiments and the model based on (2). Under dynamic stress with pulse widths down to 20ns, the Ata model, (2) is approximately valid for different values of Va and J,-, where Va is reverse emitter-base voltage at stress. Because emitter-base forward biasing results in the recovery of degradation[3,6] which causes decrease in the Als, the degradation model may need to include the recovery effects for modeling devices that undergo reverse and forward biases. Figure 4 shows the AI, recovery caused by d.c. forward emitter-base bias applied after d.c. stress. Rapid and significant recovery after applying the bias was observed. The degree of recovery saturates after a long forward bias time. However, it should also be taken into consideration that the recovered emitter-base junction has a higher re-degradation rate than that in the initial state. Figure 5 shows the AIs through a reverseforward-reverse bias sequence. After recovery, Ala degrades at a higher rate in the second reverse bias
789
BJT degradation under dynamic hot carrier stress
1.0
I
I
1
REVERSE
STRESS TIME =
1
Jc=l 0-6Num2
OJ 10’
lo2
lo4
lo3
FORWARD BIAS TIME [S]
10'
Fig. 4. Degradation recovery ratio of AI, after forward emitter-base bias to initial AI, before forward biasing. After d.c. stress (I’, = 4.3 V), forward bias ( Vbe= I .5 V, V, = 3 V, Jc = 5.8 x 10m5A) was applied. The closed symbols indicate the recovery ratio at the time when forward bias time equals reverse stress time.
stress and catches up with the extrapolated line of the initial AIs. One possible explanation is that the recovery process involves passivating the interface traps. This passivation effect, whose chemical nature is unknown, can be reversed easily by subsequent stressing. In order to simulate the stress condition of a bipolar transistor in a BiCMOS gate, an alternating forward and reverse bias pulse train was applied to the emitter-base of the bipolar transistors. The predicted AIs and 60% (from Fig. 5) of that are plotted in Fig. 6. The experimental values of AI, agree well with (2) the model without recovery effects, indicating that no significant recovery effects can be seen after the alternating bias stress. The bipolar reliability
c
’
1o-‘Ol IO2
IO3
IO4
N.~R [S] Fig. 6. AIa due to the alternating pulse train representatives of BiCMOS gate operation. The solid line indicates the model without recovery effect, eqn (2) at /a = I .06 PA. The dashed line indicates the model including recovery effect (from Fig. 4, recovery rate 60% was used). in a BiCMOS circuit can be estimated boundary given by (2).
by worst-case
4. SUMMARY In this study, we experimentally showed that the AI,, model, AZg= DJcIh,(NtR)(, is valid for the BiCMOS circuit reliability simulation. Enhanced or significantly suppressed degradation from that of d.c. stress was not observed under the pulse reverse stress. The degradation recovery effect which is observed after d.c. forward bias soak does not occur under the alternating reverse-forward bias stress applied in this study. BiCMOS circuit reliability can be estimated by a worst case boundary given by the d.c. stress AIs model and the stress duty factor.
I
I
after forward bias
Acknowledgements-This work was partially supported by SRC and by Hewlett Packard under University of California MICRO program.
REFERENCES
before forward bias Jc=l 0AgA/um2
LLlll
I
I ,#,I
I I1
3
1o2
STRESS TiE
[S]
Fig. 5. Effect of a forward bias ( Vk = 0.82 V, V,, = 2 V) in the middle of reverse bias stress (V, =4.5 V) for a 4 x 24 pm’ device. The open squares indicate AI, by second reverse bias stress after forward biasing.
I K. Nakamura. S. Kuhara. M. Takada, H. Suzuki. H. Yoshida and T. Yamazaki, in /.SSCC Dig. Tech. Papers, pp. 258-259 (1994). 2. D. D. Tang and E. Hackbarth. IEEE Trans. Electron Devices ED-35, 2101 (1988). 3. S. P. Joshi, R. Lahri and C. Lage, in IEDM Tech. Dig.. pp. 182-185 (1987). 4. J. D. Burnett and C. Hu, IEEE Trans. Electron Devices ED-35, 2238 (1988). 5. D. Burnett and C. Hu, in Proc. IEEE Inr. Rel. Symp.. pp. 164-169 (1990). 6. H. S. Momose, Y. Niitsu, H. Iwai and K. Maeguchi, in Proc. IEEE 1989 Bipolar Circuits Technol. Meet.. p. 140 (1989). 7. J. D. Burnett and C. Hu. IEEE Trans. Electron Devices ED-35, 1171 (1990).