- Email: [email protected]
Low-frequency noise in low temperature unhydrogenated polysilicon thin film transistors
Microelectronics Reliability 40 (2000) 1891±1896
www.elsevier.com/locate/microrel
Low-frequency noise in low temperature unhydrogenated polysilicon thin ®lm transistors A. Mercha a,*, J. Rhayem b, L. Pichon a, M. Valenza b, J.M. Routoure a, R. Carin a, O. Bonnaud c, D. Rigaud b
a
Groupe de Recherches en Informatique, Image et Instrumentation de Caen (GREYC), UPRESA 6072, ISMRA-Universit e de Caen, 6 bd du Mar echal Juin, 14050 Caen cedex, France b Centre d'Electronique et de Microopto electronique de Montpellier (CEM2), UMR 5507, Universit e de Montpellier II, 34095 Montpellier cedex 5, France c Groupe de Micro electronique et Visualisation (GMV), UPRESA 6076, Universit e de Rennes I, campus de Beaulieu b^ at 11B, 35042 Rennes cedex, France Received 8 December 1999; received in revised form 10 April 2000
Abstract Low-frequency noise measurements are performed in two types of low temperature polysilicon thin ®lm transistors (TFTs). For the ®rst TFT process, the polysilicon two layer structure induces large values of the channel access resistances, whose contribution to noise is dominant for large gate bias. For the second TFT process, the polysilicon single layer structure induces small access resistances and the measured noise is mainly due to channel sources. For small voltages, the channel noise spectral density evolution with gate bias agrees with the mobility ¯uctuation model and is identical for both processes. For large voltages (>2 V), the channel noise spectral density evolution, observed only in the case of the single layer structure, seems to agree with the ¯uctuations of carrier density. However, this interpretation is discussed. The results of static characterization show that the quality of the channel active layer is quite dierent from the two layer structure to the single layer structure. In agreement with these observations, the observed evolution of the relative noise with increasing gate bias in TFTs can be interpreted from intergrain potential lowering. Ó 2000 Elsevier Science Ltd. All rights reserved.
1. Introduction Low temperature polysilicon thin ®lm transistors (TFTs) are of great interest for 3D integrated circuits, active-matrix liquid crystal displays and SRAM memories. In this last application, there is a particular demand for high stability and low noise devices [1]. Measurements of the 1/f noise are also an interesting and sensitive diagnostic tool to qualify the active layer and the technological process used to elaborate the structures [2]. Previous experimental studies on low frequency
*
Corresponding author. Tel.: +33-23145-2923; fax: +3323145-2698. E-mail address: [email protected] (A. Mercha).
noise on poly-Si TFTs show that the noise level is greater than in monocrystalline MOSFETs. In most cases, data were ®tted with the theoretical expression proposed by Ghibaudo et al. [3]. Experimental results were analyzed through the model of carrier density ¯uctuations related to trapping and detrapping in grain boundary traps with correlated mobility ¯uctuations [4,5]. However, Aoki et al. recently proposed that 1/f noise in polysilicon TFT loads is strongly correlated to potential barrier height at grain boundaries [1]. In the present paper, the low frequency noise is measured particularly for TFTs obtained from a ``single layer'' process. This process produces the reduction of channel access resistances and allows a precise channel noise investigation even for large gate bias voltages. Therefore, the in¯uence of the intergrain potential barrier lowering can be studied.
0026-2714/00/$ - see front matter Ó 2000 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 0 ) 0 0 0 6 0 - 3
1892
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
2. Experimental results 2.1. Process and device description The TFTs are made through a four mask aluminum gate process. The active layer is made of low temperature ( 6 600°C) unhydrogenated, undoped polysilicon. However, two dierent deposition processes have been operated (Fig. 1). In process I, the undoped channel layer and the doped drain/source layer are deposited in two sequential steps, with an intermediary etching step. In process II, a single step is used for the deposition of a single amorphous silicon layer for which bottom half part is undoped and the top half part is in situ highly doped. After the silicon crystallization, the main dierence between processes I and II is the presence of a structural interface between the doped and undoped polysilicon for the two layer structure (Fig. 2a), whereas no structural interface is present for the single layer structure (Fig. 2b). As will be seen later, this processing dierence leads to two consequences for the TFT characteristics. First, the structural interface induces large access resistance values between drain/source and channel for the two layer structure. This drawback does not exist for the single layer structure. Secondly, the channel zone is obtained by etching the doped polysilicon and is located in the undoped polysilicon, near the interface. Therefore, the TFT channel location in the initial polysilicon layer is near a disturbed crystallographic interface for the two layer structure, and is in the middle of the columnar crystallites for the single layer structure. So, the crystallographic quality of the polysilicon in the TFT channel is expected to be much better for the single layer structure. 2.1.1. Two step deposition process: ``two layer'' structure (Fig. 1a) At ®rst, a 150 nm thick, undoped amorphous silicon layer is deposited by low pressure chemical vapour de-
a) Process I Deposition first step
+ N doped amorphous silicon
Fig. 2. TEM photographs (after Ref. [6]) and schematic representations of polysilicon layers in the TFT channel region. The in situ N-doped polysilicon layer has not yet been plasma etched to de®ne the source and the drain regions.
position (LPCVD) technique on an h1 0 0i n-type oxidized monosilicon wafer. Samples are then taken out of the reactor and this undoped amorphous polysilicon layer is plasma etched by reactive ion etching (RIE) to form rectangular pieces which will constitute the undoped active layers. Then, a second deposition of a 150 nm thick phosphorus, heavily in situ doped LPCVD amorphous silicon layer with a phosphorus doping concentration equal to 4 1020 cmÿ3 is carried out. The transmission electronic microscopy (TEM) micrographs of polysilicon layers clearly show the structural interface at half height of the ``two layer structure'' (Fig. 2a). Under the deposition and annealing conditions, nucleation is known to start preferentially at the amorphous silicon (a-Si)/SiO2 interface, and therefore, the grains grow up to the surface, leading to a columnar structure. Between the two deposition steps of amorphous layers of ``two layer'' structures, impurities are adsorbed on the ®rst layer surface and remain in spite of an HF rinsing. The presence of these impurities at the junction between the two amorphous layers might lead to a second front of nucleation, responsible for the interface between undoped and doped polysilicon layers in the ``two layer structure'' (Fig. 2a).
Undoped amorphous silicon mono Si substrate
SiO2
Etching
b) Process II Deposition second step
Deposition single step
Fig. 1. Deposition process steps for two layer structure and single layer structure.
2.1.2. One step deposition process: ``single layer'' structure (Fig. 1b) In the second process, a 300 nm thick, LPCVD amorphous silicon layer, with two dierently doped stacked regions, is deposited during the same growth without breaking the vacuum and just by switching on the phosphine opening valve when the thickness of the undoped layer is estimated to be 150 nm. So, the 150 nm thick, lower half layer is undoped and the upper half 150 nm layer is heavily in situ doped. In the one-step deposition process used, no impurities are introduced be-
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
1893
tween the undoped and doped polysilicon layers, nucleation starts from the inferior SiO2 /a-Si interface and grains grow up to the surface of the 300 nm dierentially doped layer leading to a columnar structure (Fig. 2b). 2.1.3. Thin ®lm transistor structure realization These previous amorphous silicon layers deposited at 550°C are then crystallized by solid phase crystallization (SPC) technique. A thermal annealing in vacuum at 600°C during 12 h ensures the crystallization. The heavily in situ doped SPC-polysilicon layer is plasma etched to form the source and the drain regions. Furthermore, to ensure a good active layer/gate insulator interface quality, an radio frequency (RF) oxygen plasma is performed at room temperature on the structure before an Radio Corporation of America (RCA)-type cleaning. Therefore, a 60 nm thick Atmospheric Pressure Chemical Vapour Deposition (APCVD) SiO2 layer is deposited at 450°C with a silane/oxygen gas mixture to insulate the gate electrode. A thermal annealing in nitrogen at 600°C is carried out to ensure densi®cation of the APCVD SiO2 gate insulator. Finally, aluminum is thermally evaporated and wet etched to form source, gate and drain electrodes. Usual post-metallization annealing is performed at 390°C in an atmosphere of forming gas to improve aluminum contacts. The ®nal TFT structure cross-section for both processes I and II is represented in Fig. 3. 2.2. Conduction parameters The drain current transfer versus gate bias for both structures is shown in Fig. 4. First-order parameters are extracted according to the simpli®ed electrical model using the protocol described in Ref. [7]. Extracted electrical parameters for both types of TFTs are shown in Table 1. All of those are improved for the single layer structure. The value of the subthreshold slope S, measured in the switching region, is a relevant illustrative indication of the density of states involved. S depends on ®xed charge density in the surface space charge layer and on the interface density of states through the relation
a) Process I
Al N+doped polysilicon
b) Process II
Undoped polysilicon
SiO 2
Fig. 3. Schematic cross-sections of both TFTs types.
Fig. 4. Drain current transfer characteristics versus gate bias for both TFT structures, VDS 50 mV and W =L 100 lm/38 lm.
Table 1 Electrical parameters for both TFTs types Structure
S (V/ dec)
l (cm2 /V s)
VT (V)
Access resistances (X)
Two layer Single layer
1 0.7
60 >100
4 2
10±100 <1
kT CD CSS S ln 10 1 ; q COX COX
1
where CD is the space charge capacitance per unit area, which is proportional to the square root of the space charge density ND and CSS is the interface capacitance per unit area, which is proportional to the interface density of states NSS . A high space charge density in TFTs (1017 ±1019 cmÿ3 ) arises from trapping states at grain boundaries and at intragrain defects. Nevertheless, CSS remains larger than CD , so a lower density of states at the interface SiO2 /poly-Si is probably responsible for the observed S decrease in single layer structure. The ®eld eect mobility l is also improved as the surface roughness, and the density of states in grain boundaries is lowered in single layer structure. These results are probably correlated with the position of the channel, located in a more disturbed region for the two layer structure. Furthermore, the undoped/doped polysilicon interface existing near the drain and source contacts in the two layer structure probably contributes to the decrease of the apparent ®eld eect mobility. The values of access resistances, a few ten ohms in the two layer structure and an insigni®cant one in the single layer structure, are also in accordance with the presence or absence of the structural interface. The threshold voltage VT gives also a pertinent information on the density of trapping states at SiO2 /Si interface, at grain boundaries and at intragrain defects.
1894
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
In summary, the single layer structure allows a signi®cant improvement of all electrical parameters. This evolution is attributed to a better crystallinity of the grains in the active layer and to the consecutive improvement of the active layer/gate insulator interface. 2.3. Noise analysis In MOS transistors, the 1/f noise is due to the ¯uctuations of the channel conductivity, i.e. ¯uctuations of the carrier number and/or carrier mobility. Two models are generally used to describe the 1/f noise in linear ID ± VDS regime: (i) The Mc Whorter theory [8] (DN model) involves carrier trapping and detrapping. In this case, the current spectral density can be expressed as Si f ID2
SN k l ID VDS ; N2 f COX L2 VGS ÿ VT
2
where k takes into account the electron tunneling from traps near the interface to the conducting channel. (ii) The Hooge empirical relation [9] (Dl model) involves mobility ¯uctuations. The empirical formula suggested by Hooge can be applied to MOSFET transistors in the ohmic range as Si f SG Sl aH : 2 2 l fN ID2 G
Si f SG Sl SN aapparent 2 2 2 : l N fN ID2 G
6
The noise investigations are performed in the linear range (VDS 50 mV). They show that for TFTs made through the ®rst process (two layer structure), the 1/f noise results from mobility ¯uctuations (Si f = ID2 / VGS ÿ VT ÿ1 and aapparent aH is constant with aH 2 10ÿ1 ) (see Figs. 5a and 6a). It can be seen that for high eective gate voltage, an increase of the HoogeÕs parameter occurs. This behavior is associated with the noise of access resistances which can prevail upon the channel noise [10]. The access resistance noise is attributed to a noisy interface between the undoped layer (active layer) and the heavily doped regions (drain and source regions) (Fig. 2a). For the TFTs made of a single polysilicon layer, the 1/f noise of channel access resistance is negligible. In this case, experimental data (Fig. 6b) seem to agree either with the mobility ¯uctuation model for low gate biases or with the density ¯uctuation model for large gate biases (>2 V). However, an alternative interpretation involving eects of the intergrain potential barrier lowering with the gate voltage increase is discussed in the Section 3.
3
For both models, the obtained expressions of Si f =ID2 are given in Table 2 with the help of the current equation in the ohmic range: ID lCOX
W VGS ÿ VT VDS L
4
and the number N of electrons in the channel: COX WL N VGS ÿ VT : q
5
Fig. 5. Relative channel noise variations versus VGS ÿ VT for f 10 Hz, VDS 50 mV and W =L 100 lm/38 lm.
From this table, the dierence between the two models is clearly shown: the DN model leads to equations which can be written following Hooge's formulation with an eective a parameter (noted aapparent ) varying as (VGS ÿ VT ÿ1 . This parameter aapparent is introduced to discriminate the Mc Whorter or Hooge models. Then the normalized spectral density can be expressed as Table 2 Relative noise expressions for both models Si f =ID2 DN model (Mc Whorter) Dl model (Hooge)
2 / 1= COX WL 1= VGS ÿ VT 2 1=f
/ aH = COX WL 1= VGS ÿ VT 1=f
Fig. 6. Hooge's parameter and aapparent for the same studied transistor as in Fig. 5.
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
3. Discussion Charge transport in polycrystalline semiconductors and conduction parameters are strongly in¯uenced by the presence of grain boundaries [11,12]. Each grain boundary constitutes, when electrically charged, a potential barrier for the majority carriers. As a consequence, dominant ¯uctuation phenomena arise from sources located within the boundary or in bulk traps near the boundary [13]. If an impurity, located near the barrier or within the boundary, changes its charge then the local barrier height can ¯uctuate and gives a large current ¯uctuation. Several fundamental studies on 1/f noise in polysilicon ®lm resistors have also shown that the noise is due to mobility ¯uctuations related to the potential barrier. However, the microscopic noise sources have not been identi®ed as yet. These sources may be related to lattice scattering [14], barrier height ¯uctuations [15], carrier capture and release [16] or boundary scattering [17]. It was also found that the 1/f noise of low and moderately doped polysilicon samples is mainly produced in the depletion region [18]. For the present TFTs, it can reasonably be assumed that the intrinsic noise relative to active zone have the same origin in both structures. Thus, it is more convenient to extract intrinsic noise characteristics from the single layer structure results since, in this case, the parasitic contribution of access resistances noise is negligible. Noise measurements were performed with single layer structure for dierent processes and geometries. It was observed that for high mobility devices ( P 100 cm2 / V s), two distinct regimes can be distinguished in the apparent Hooge parameter evolution with eective gate bias VG (Fig. 6b). These two regimes can be attributed to the grain boundary potential barrier evolution with gate bias. At low eective gate biases, when the Hooge parameter is constant, the potential barrier at grain boundaries and associated impedance are high. For larger eective gate biases (VG > 2 V), when the Hooge parameter decreases, the potential barrier at grain boundaries is lower than thermal energy and does not impede the current transport anymore. Therefore, we believe that the TFT small signal model must account for two physical noise causes, the one located in the grain boundaries and the other one located in the grains, near the poly-Si/SiO2 interface. The potential barrier at the grain boundary, by controlling the impedance associated with the ®rst source, can select either source as the dominant one, depending on the impedance value. Recent studies of relative noise evolution with temperature accredit the fact that the observed evolution of the normalized noise is due to a transition of the potential barrier to values lower than thermal energy. For low eective gate biases, the main contribution is thus probably a mobility ¯uctuation noise located in the
1895
grains. In this case, the results obtained for single layer structure can be compared to the results obtained for two layer structure since the access resistance noise is dominant only for large gate biases. Then, we observe (Fig. 6) that the Hooge parameter measured in both structures has the same value 2 10ÿ1 , which suggests that the mobility ¯uctuations noise source involved is common to both processes. For both processes, the interface poly-Si/SiO2 quality and the channel surface roughness present probably similar characteristics because they are related to the same plasma etching and the same oxidation steps [6]. The mobility ¯uctuation in the channel can be attributed to coulombic scattering due to surface roughness and charge in the SiO2 gate insulator. For high eective gate biases, the main noise contribution is probably related to potential barrier ¯uctuation. Then, the barrier is low but may still have in¯uence on second-order characteristics such as activation energy and noise due to an increase of non-homogeneity at grain boundaries as the mean value of potential barrier decreases [19]. The disorder at grain boundaries can induce a non-uniform channel conduction that can generate a decrease of the Hooge parameter [20]. This decrease may also be caused by surface scattering due to surface roughness as the eective channel width is decreased with gate bias increasing. Hooge et al. have shown that boundary scattering do not generate 1/f noise but induces a reduction in the relative noise [21]. At this point, two dierent interpretations can be considered, both including the primordial role played by potential barrier at grain boundaries. The ®rst one interprets the grain boundary 1/f noise source as a mobility ¯uctuation related to the deviation of the electrons forced to pass through the barrier cols. The second one supposes number ¯uctuations associated with capture and release of carriers by oxide traps. The TFT noise model must then be evolved. Its previsions will be carefully compared with experimental results to discriminate between both hypothesis. 4. Conclusions Noise analyses have been performed in poly-Si TFTs for two dierent structures. For the ``two layer structure'', 1/f noise is associated with the mobility ¯uctuation. We have found a Hooge parameter aH value about 2 10ÿ1 . At high gate polarization, we have detected the in¯uence of the access resistance noise attributed to an interface between doped and undoped polysilicon layers in this ``two layer structure''. For the ``single layer structure'', the intrinsic 1/f channel noise is no more hidden by parasitic access resistance noise contribution. The ``single layer'' deposition process permitted to eliminate the noisy interface
1896
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
between the undoped and doped polysilicon regions. For large gate biases, the channel noise seems to be caused by the ¯uctuation of the carrier number. We propose an alternative interpretation to the density ¯uctuation model which is supported by the observed evolution of apparent Hooge parameter with gate bias: the measured aapparent parameter decrease with increasing eective gate bias in TFTs may be due to intergrain potential barrier lowering. However, further investigations are needed to con®rm the microscopic mechanisms causing these ¯uctuations. References [1] Aoki M, Hashimoto T, Yamanaka T, Nagano T. Large 1/f noise in polysilicon TFT loads and its eects on the stability of SRAM cells. Jpn J Appl Phys 1996;35:838±41. [2] Vandamme LKJ. Noise as a diagnostic tool for quality and reliability of electronic devices. IEEE Trans Electron Dev 1994;41:2176±87. [3] Ghibaudo G, Roux O, Nguyen-duc Ch, Balestra F, Brini J. Improved analysis of low frequency noise in ®eld eect MOS transistor. Phys Stat Sol (a) 1991;124:571±81. [4] Dimitriadis CA, Brini J, Kamarinos G, Ghibaudo G. Characterization of low-pressure chemical vapor deposited polycrystalline silicon thin ®lm transistors by low frequency noise measurements. Jpn J Appl Phys 1998;37:72±7. [5] Corradetti A, Leoni R, Carlucio R, Fortunato G, Reita C, Plais F, Pribat D. Evidence of carrier number ¯uctuation as origin of 1/f noise in polycrystalline silicon thin ®lm transistors. J Appl Phys Lett 1995;67:1730±2. [6] Mourgues K, Raoult F, Pichon L, Mohammed-Brahim T, Briand D, Bonnaud O. Performance of thin ®lm transistors on unhydrogenated in situ doped polysilicon ®lms obtained by solid phase crystallization. Mat Res Soc Symp Proc 1997;141:155±60.
[7] Rhayem JM, Valenza M, Rigaud D. 1/f noise investigations in small channel length amorphous silicon thin ®lm transistors. J Appl Phys 1998;83:3660±7. [8] Mc Whorter AL. Semiconductor surface physics, University of Pennsylvania Press, PA, 1957. p. 207±28. [9] Hooge FN. 1/f noise is no surface eect. Phys Lett 1969;29:139±40. [10] Peransin JM, Vignaud P, Rigaud D, Vandamme LKJ. 1/f noise in MOSFETs at low drain bias. IEEE Trans Electron Dev 1990;37:2250±3. [11] Seto JYW. The electrical properties of polycrystalline silicon ®lms. J Appl Phys 1975;46:5247±54. [12] Baccarani G, Ricco B, Spadini G. Transport properties of polycrystalline silicon ®lms. J Appl Phys 1978;49:5565±70. [13] Madenach AJ, Werner J. Noise spectroscopy of silicon grain boundaries. Phys Rev B 1988;38:1958±62. [14] De Graa HC, Huybers MTM. 1/f noise in polycrystalline silicon resistors. J Appl Phys 1983;54:2504±7. [15] Jang SL. A model of 1/f noise in polysilicon resistors. Solid-State Electron 1990;33:1155±62. [16] Surya C, Hsiang TY. Surface mobility ¯uctuations in metal-oxide-semiconductor ®eld eect transistors. Phys Rev B 1987;35:6343±7. [17] Chen XY, Salm C. Doping dependence of low frequency noise in polycrystalline SiGe ®lm resistors. J Appl Phys 1999;75:516±8. [18] Luo M-Y, Bosman G. An analytical model for 1/f noise in polycrystalline silicon thin ®lms. IEEE Trans Electron Dev 1990;37:768±73. [19] Dimitriadis CA. Grain boundary potential barrier inhomogeneities in low pressure chemical vapor deposited polycrystalline silicon thin ®lm transistors. IEEE Trans Electron Dev 1997;44:1563±5. [20] Vandamme LKJ. Model for 1/f noise in MOS transistor biased in the linear region. Solid-State Electron 1980; 33:317±23. [21] Hooge FN, Kedzia J, Vandamme LKJ. Boundary scattering and 1/f noise. J Appl Phys 1979;50:8087±9.
www.elsevier.com/locate/microrel
Low-frequency noise in low temperature unhydrogenated polysilicon thin ®lm transistors A. Mercha a,*, J. Rhayem b, L. Pichon a, M. Valenza b, J.M. Routoure a, R. Carin a, O. Bonnaud c, D. Rigaud b
a
Groupe de Recherches en Informatique, Image et Instrumentation de Caen (GREYC), UPRESA 6072, ISMRA-Universit e de Caen, 6 bd du Mar echal Juin, 14050 Caen cedex, France b Centre d'Electronique et de Microopto electronique de Montpellier (CEM2), UMR 5507, Universit e de Montpellier II, 34095 Montpellier cedex 5, France c Groupe de Micro electronique et Visualisation (GMV), UPRESA 6076, Universit e de Rennes I, campus de Beaulieu b^ at 11B, 35042 Rennes cedex, France Received 8 December 1999; received in revised form 10 April 2000
Abstract Low-frequency noise measurements are performed in two types of low temperature polysilicon thin ®lm transistors (TFTs). For the ®rst TFT process, the polysilicon two layer structure induces large values of the channel access resistances, whose contribution to noise is dominant for large gate bias. For the second TFT process, the polysilicon single layer structure induces small access resistances and the measured noise is mainly due to channel sources. For small voltages, the channel noise spectral density evolution with gate bias agrees with the mobility ¯uctuation model and is identical for both processes. For large voltages (>2 V), the channel noise spectral density evolution, observed only in the case of the single layer structure, seems to agree with the ¯uctuations of carrier density. However, this interpretation is discussed. The results of static characterization show that the quality of the channel active layer is quite dierent from the two layer structure to the single layer structure. In agreement with these observations, the observed evolution of the relative noise with increasing gate bias in TFTs can be interpreted from intergrain potential lowering. Ó 2000 Elsevier Science Ltd. All rights reserved.
1. Introduction Low temperature polysilicon thin ®lm transistors (TFTs) are of great interest for 3D integrated circuits, active-matrix liquid crystal displays and SRAM memories. In this last application, there is a particular demand for high stability and low noise devices [1]. Measurements of the 1/f noise are also an interesting and sensitive diagnostic tool to qualify the active layer and the technological process used to elaborate the structures [2]. Previous experimental studies on low frequency
*
Corresponding author. Tel.: +33-23145-2923; fax: +3323145-2698. E-mail address: [email protected] (A. Mercha).
noise on poly-Si TFTs show that the noise level is greater than in monocrystalline MOSFETs. In most cases, data were ®tted with the theoretical expression proposed by Ghibaudo et al. [3]. Experimental results were analyzed through the model of carrier density ¯uctuations related to trapping and detrapping in grain boundary traps with correlated mobility ¯uctuations [4,5]. However, Aoki et al. recently proposed that 1/f noise in polysilicon TFT loads is strongly correlated to potential barrier height at grain boundaries [1]. In the present paper, the low frequency noise is measured particularly for TFTs obtained from a ``single layer'' process. This process produces the reduction of channel access resistances and allows a precise channel noise investigation even for large gate bias voltages. Therefore, the in¯uence of the intergrain potential barrier lowering can be studied.
0026-2714/00/$ - see front matter Ó 2000 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 0 ) 0 0 0 6 0 - 3
1892
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
2. Experimental results 2.1. Process and device description The TFTs are made through a four mask aluminum gate process. The active layer is made of low temperature ( 6 600°C) unhydrogenated, undoped polysilicon. However, two dierent deposition processes have been operated (Fig. 1). In process I, the undoped channel layer and the doped drain/source layer are deposited in two sequential steps, with an intermediary etching step. In process II, a single step is used for the deposition of a single amorphous silicon layer for which bottom half part is undoped and the top half part is in situ highly doped. After the silicon crystallization, the main dierence between processes I and II is the presence of a structural interface between the doped and undoped polysilicon for the two layer structure (Fig. 2a), whereas no structural interface is present for the single layer structure (Fig. 2b). As will be seen later, this processing dierence leads to two consequences for the TFT characteristics. First, the structural interface induces large access resistance values between drain/source and channel for the two layer structure. This drawback does not exist for the single layer structure. Secondly, the channel zone is obtained by etching the doped polysilicon and is located in the undoped polysilicon, near the interface. Therefore, the TFT channel location in the initial polysilicon layer is near a disturbed crystallographic interface for the two layer structure, and is in the middle of the columnar crystallites for the single layer structure. So, the crystallographic quality of the polysilicon in the TFT channel is expected to be much better for the single layer structure. 2.1.1. Two step deposition process: ``two layer'' structure (Fig. 1a) At ®rst, a 150 nm thick, undoped amorphous silicon layer is deposited by low pressure chemical vapour de-
a) Process I Deposition first step
+ N doped amorphous silicon
Fig. 2. TEM photographs (after Ref. [6]) and schematic representations of polysilicon layers in the TFT channel region. The in situ N-doped polysilicon layer has not yet been plasma etched to de®ne the source and the drain regions.
position (LPCVD) technique on an h1 0 0i n-type oxidized monosilicon wafer. Samples are then taken out of the reactor and this undoped amorphous polysilicon layer is plasma etched by reactive ion etching (RIE) to form rectangular pieces which will constitute the undoped active layers. Then, a second deposition of a 150 nm thick phosphorus, heavily in situ doped LPCVD amorphous silicon layer with a phosphorus doping concentration equal to 4 1020 cmÿ3 is carried out. The transmission electronic microscopy (TEM) micrographs of polysilicon layers clearly show the structural interface at half height of the ``two layer structure'' (Fig. 2a). Under the deposition and annealing conditions, nucleation is known to start preferentially at the amorphous silicon (a-Si)/SiO2 interface, and therefore, the grains grow up to the surface, leading to a columnar structure. Between the two deposition steps of amorphous layers of ``two layer'' structures, impurities are adsorbed on the ®rst layer surface and remain in spite of an HF rinsing. The presence of these impurities at the junction between the two amorphous layers might lead to a second front of nucleation, responsible for the interface between undoped and doped polysilicon layers in the ``two layer structure'' (Fig. 2a).
Undoped amorphous silicon mono Si substrate
SiO2
Etching
b) Process II Deposition second step
Deposition single step
Fig. 1. Deposition process steps for two layer structure and single layer structure.
2.1.2. One step deposition process: ``single layer'' structure (Fig. 1b) In the second process, a 300 nm thick, LPCVD amorphous silicon layer, with two dierently doped stacked regions, is deposited during the same growth without breaking the vacuum and just by switching on the phosphine opening valve when the thickness of the undoped layer is estimated to be 150 nm. So, the 150 nm thick, lower half layer is undoped and the upper half 150 nm layer is heavily in situ doped. In the one-step deposition process used, no impurities are introduced be-
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
1893
tween the undoped and doped polysilicon layers, nucleation starts from the inferior SiO2 /a-Si interface and grains grow up to the surface of the 300 nm dierentially doped layer leading to a columnar structure (Fig. 2b). 2.1.3. Thin ®lm transistor structure realization These previous amorphous silicon layers deposited at 550°C are then crystallized by solid phase crystallization (SPC) technique. A thermal annealing in vacuum at 600°C during 12 h ensures the crystallization. The heavily in situ doped SPC-polysilicon layer is plasma etched to form the source and the drain regions. Furthermore, to ensure a good active layer/gate insulator interface quality, an radio frequency (RF) oxygen plasma is performed at room temperature on the structure before an Radio Corporation of America (RCA)-type cleaning. Therefore, a 60 nm thick Atmospheric Pressure Chemical Vapour Deposition (APCVD) SiO2 layer is deposited at 450°C with a silane/oxygen gas mixture to insulate the gate electrode. A thermal annealing in nitrogen at 600°C is carried out to ensure densi®cation of the APCVD SiO2 gate insulator. Finally, aluminum is thermally evaporated and wet etched to form source, gate and drain electrodes. Usual post-metallization annealing is performed at 390°C in an atmosphere of forming gas to improve aluminum contacts. The ®nal TFT structure cross-section for both processes I and II is represented in Fig. 3. 2.2. Conduction parameters The drain current transfer versus gate bias for both structures is shown in Fig. 4. First-order parameters are extracted according to the simpli®ed electrical model using the protocol described in Ref. [7]. Extracted electrical parameters for both types of TFTs are shown in Table 1. All of those are improved for the single layer structure. The value of the subthreshold slope S, measured in the switching region, is a relevant illustrative indication of the density of states involved. S depends on ®xed charge density in the surface space charge layer and on the interface density of states through the relation
a) Process I
Al N+doped polysilicon
b) Process II
Undoped polysilicon
SiO 2
Fig. 3. Schematic cross-sections of both TFTs types.
Fig. 4. Drain current transfer characteristics versus gate bias for both TFT structures, VDS 50 mV and W =L 100 lm/38 lm.
Table 1 Electrical parameters for both TFTs types Structure
S (V/ dec)
l (cm2 /V s)
VT (V)
Access resistances (X)
Two layer Single layer
1 0.7
60 >100
4 2
10±100 <1
kT CD CSS S ln 10 1 ; q COX COX
1
where CD is the space charge capacitance per unit area, which is proportional to the square root of the space charge density ND and CSS is the interface capacitance per unit area, which is proportional to the interface density of states NSS . A high space charge density in TFTs (1017 ±1019 cmÿ3 ) arises from trapping states at grain boundaries and at intragrain defects. Nevertheless, CSS remains larger than CD , so a lower density of states at the interface SiO2 /poly-Si is probably responsible for the observed S decrease in single layer structure. The ®eld eect mobility l is also improved as the surface roughness, and the density of states in grain boundaries is lowered in single layer structure. These results are probably correlated with the position of the channel, located in a more disturbed region for the two layer structure. Furthermore, the undoped/doped polysilicon interface existing near the drain and source contacts in the two layer structure probably contributes to the decrease of the apparent ®eld eect mobility. The values of access resistances, a few ten ohms in the two layer structure and an insigni®cant one in the single layer structure, are also in accordance with the presence or absence of the structural interface. The threshold voltage VT gives also a pertinent information on the density of trapping states at SiO2 /Si interface, at grain boundaries and at intragrain defects.
1894
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
In summary, the single layer structure allows a signi®cant improvement of all electrical parameters. This evolution is attributed to a better crystallinity of the grains in the active layer and to the consecutive improvement of the active layer/gate insulator interface. 2.3. Noise analysis In MOS transistors, the 1/f noise is due to the ¯uctuations of the channel conductivity, i.e. ¯uctuations of the carrier number and/or carrier mobility. Two models are generally used to describe the 1/f noise in linear ID ± VDS regime: (i) The Mc Whorter theory [8] (DN model) involves carrier trapping and detrapping. In this case, the current spectral density can be expressed as Si f ID2
SN k l ID VDS ; N2 f COX L2 VGS ÿ VT
2
where k takes into account the electron tunneling from traps near the interface to the conducting channel. (ii) The Hooge empirical relation [9] (Dl model) involves mobility ¯uctuations. The empirical formula suggested by Hooge can be applied to MOSFET transistors in the ohmic range as Si f SG Sl aH : 2 2 l fN ID2 G
Si f SG Sl SN aapparent 2 2 2 : l N fN ID2 G
6
The noise investigations are performed in the linear range (VDS 50 mV). They show that for TFTs made through the ®rst process (two layer structure), the 1/f noise results from mobility ¯uctuations (Si f = ID2 / VGS ÿ VT ÿ1 and aapparent aH is constant with aH 2 10ÿ1 ) (see Figs. 5a and 6a). It can be seen that for high eective gate voltage, an increase of the HoogeÕs parameter occurs. This behavior is associated with the noise of access resistances which can prevail upon the channel noise [10]. The access resistance noise is attributed to a noisy interface between the undoped layer (active layer) and the heavily doped regions (drain and source regions) (Fig. 2a). For the TFTs made of a single polysilicon layer, the 1/f noise of channel access resistance is negligible. In this case, experimental data (Fig. 6b) seem to agree either with the mobility ¯uctuation model for low gate biases or with the density ¯uctuation model for large gate biases (>2 V). However, an alternative interpretation involving eects of the intergrain potential barrier lowering with the gate voltage increase is discussed in the Section 3.
3
For both models, the obtained expressions of Si f =ID2 are given in Table 2 with the help of the current equation in the ohmic range: ID lCOX
W VGS ÿ VT VDS L
4
and the number N of electrons in the channel: COX WL N VGS ÿ VT : q
5
Fig. 5. Relative channel noise variations versus VGS ÿ VT for f 10 Hz, VDS 50 mV and W =L 100 lm/38 lm.
From this table, the dierence between the two models is clearly shown: the DN model leads to equations which can be written following Hooge's formulation with an eective a parameter (noted aapparent ) varying as (VGS ÿ VT ÿ1 . This parameter aapparent is introduced to discriminate the Mc Whorter or Hooge models. Then the normalized spectral density can be expressed as Table 2 Relative noise expressions for both models Si f =ID2 DN model (Mc Whorter) Dl model (Hooge)
2 / 1= COX WL 1= VGS ÿ VT 2 1=f
/ aH = COX WL 1= VGS ÿ VT 1=f
Fig. 6. Hooge's parameter and aapparent for the same studied transistor as in Fig. 5.
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
3. Discussion Charge transport in polycrystalline semiconductors and conduction parameters are strongly in¯uenced by the presence of grain boundaries [11,12]. Each grain boundary constitutes, when electrically charged, a potential barrier for the majority carriers. As a consequence, dominant ¯uctuation phenomena arise from sources located within the boundary or in bulk traps near the boundary [13]. If an impurity, located near the barrier or within the boundary, changes its charge then the local barrier height can ¯uctuate and gives a large current ¯uctuation. Several fundamental studies on 1/f noise in polysilicon ®lm resistors have also shown that the noise is due to mobility ¯uctuations related to the potential barrier. However, the microscopic noise sources have not been identi®ed as yet. These sources may be related to lattice scattering [14], barrier height ¯uctuations [15], carrier capture and release [16] or boundary scattering [17]. It was also found that the 1/f noise of low and moderately doped polysilicon samples is mainly produced in the depletion region [18]. For the present TFTs, it can reasonably be assumed that the intrinsic noise relative to active zone have the same origin in both structures. Thus, it is more convenient to extract intrinsic noise characteristics from the single layer structure results since, in this case, the parasitic contribution of access resistances noise is negligible. Noise measurements were performed with single layer structure for dierent processes and geometries. It was observed that for high mobility devices ( P 100 cm2 / V s), two distinct regimes can be distinguished in the apparent Hooge parameter evolution with eective gate bias VG (Fig. 6b). These two regimes can be attributed to the grain boundary potential barrier evolution with gate bias. At low eective gate biases, when the Hooge parameter is constant, the potential barrier at grain boundaries and associated impedance are high. For larger eective gate biases (VG > 2 V), when the Hooge parameter decreases, the potential barrier at grain boundaries is lower than thermal energy and does not impede the current transport anymore. Therefore, we believe that the TFT small signal model must account for two physical noise causes, the one located in the grain boundaries and the other one located in the grains, near the poly-Si/SiO2 interface. The potential barrier at the grain boundary, by controlling the impedance associated with the ®rst source, can select either source as the dominant one, depending on the impedance value. Recent studies of relative noise evolution with temperature accredit the fact that the observed evolution of the normalized noise is due to a transition of the potential barrier to values lower than thermal energy. For low eective gate biases, the main contribution is thus probably a mobility ¯uctuation noise located in the
1895
grains. In this case, the results obtained for single layer structure can be compared to the results obtained for two layer structure since the access resistance noise is dominant only for large gate biases. Then, we observe (Fig. 6) that the Hooge parameter measured in both structures has the same value 2 10ÿ1 , which suggests that the mobility ¯uctuations noise source involved is common to both processes. For both processes, the interface poly-Si/SiO2 quality and the channel surface roughness present probably similar characteristics because they are related to the same plasma etching and the same oxidation steps [6]. The mobility ¯uctuation in the channel can be attributed to coulombic scattering due to surface roughness and charge in the SiO2 gate insulator. For high eective gate biases, the main noise contribution is probably related to potential barrier ¯uctuation. Then, the barrier is low but may still have in¯uence on second-order characteristics such as activation energy and noise due to an increase of non-homogeneity at grain boundaries as the mean value of potential barrier decreases [19]. The disorder at grain boundaries can induce a non-uniform channel conduction that can generate a decrease of the Hooge parameter [20]. This decrease may also be caused by surface scattering due to surface roughness as the eective channel width is decreased with gate bias increasing. Hooge et al. have shown that boundary scattering do not generate 1/f noise but induces a reduction in the relative noise [21]. At this point, two dierent interpretations can be considered, both including the primordial role played by potential barrier at grain boundaries. The ®rst one interprets the grain boundary 1/f noise source as a mobility ¯uctuation related to the deviation of the electrons forced to pass through the barrier cols. The second one supposes number ¯uctuations associated with capture and release of carriers by oxide traps. The TFT noise model must then be evolved. Its previsions will be carefully compared with experimental results to discriminate between both hypothesis. 4. Conclusions Noise analyses have been performed in poly-Si TFTs for two dierent structures. For the ``two layer structure'', 1/f noise is associated with the mobility ¯uctuation. We have found a Hooge parameter aH value about 2 10ÿ1 . At high gate polarization, we have detected the in¯uence of the access resistance noise attributed to an interface between doped and undoped polysilicon layers in this ``two layer structure''. For the ``single layer structure'', the intrinsic 1/f channel noise is no more hidden by parasitic access resistance noise contribution. The ``single layer'' deposition process permitted to eliminate the noisy interface
1896
A. Mercha et al. / Microelectronics Reliability 40 (2000) 1891±1896
between the undoped and doped polysilicon regions. For large gate biases, the channel noise seems to be caused by the ¯uctuation of the carrier number. We propose an alternative interpretation to the density ¯uctuation model which is supported by the observed evolution of apparent Hooge parameter with gate bias: the measured aapparent parameter decrease with increasing eective gate bias in TFTs may be due to intergrain potential barrier lowering. However, further investigations are needed to con®rm the microscopic mechanisms causing these ¯uctuations. References [1] Aoki M, Hashimoto T, Yamanaka T, Nagano T. Large 1/f noise in polysilicon TFT loads and its eects on the stability of SRAM cells. Jpn J Appl Phys 1996;35:838±41. [2] Vandamme LKJ. Noise as a diagnostic tool for quality and reliability of electronic devices. IEEE Trans Electron Dev 1994;41:2176±87. [3] Ghibaudo G, Roux O, Nguyen-duc Ch, Balestra F, Brini J. Improved analysis of low frequency noise in ®eld eect MOS transistor. Phys Stat Sol (a) 1991;124:571±81. [4] Dimitriadis CA, Brini J, Kamarinos G, Ghibaudo G. Characterization of low-pressure chemical vapor deposited polycrystalline silicon thin ®lm transistors by low frequency noise measurements. Jpn J Appl Phys 1998;37:72±7. [5] Corradetti A, Leoni R, Carlucio R, Fortunato G, Reita C, Plais F, Pribat D. Evidence of carrier number ¯uctuation as origin of 1/f noise in polycrystalline silicon thin ®lm transistors. J Appl Phys Lett 1995;67:1730±2. [6] Mourgues K, Raoult F, Pichon L, Mohammed-Brahim T, Briand D, Bonnaud O. Performance of thin ®lm transistors on unhydrogenated in situ doped polysilicon ®lms obtained by solid phase crystallization. Mat Res Soc Symp Proc 1997;141:155±60.
[7] Rhayem JM, Valenza M, Rigaud D. 1/f noise investigations in small channel length amorphous silicon thin ®lm transistors. J Appl Phys 1998;83:3660±7. [8] Mc Whorter AL. Semiconductor surface physics, University of Pennsylvania Press, PA, 1957. p. 207±28. [9] Hooge FN. 1/f noise is no surface eect. Phys Lett 1969;29:139±40. [10] Peransin JM, Vignaud P, Rigaud D, Vandamme LKJ. 1/f noise in MOSFETs at low drain bias. IEEE Trans Electron Dev 1990;37:2250±3. [11] Seto JYW. The electrical properties of polycrystalline silicon ®lms. J Appl Phys 1975;46:5247±54. [12] Baccarani G, Ricco B, Spadini G. Transport properties of polycrystalline silicon ®lms. J Appl Phys 1978;49:5565±70. [13] Madenach AJ, Werner J. Noise spectroscopy of silicon grain boundaries. Phys Rev B 1988;38:1958±62. [14] De Graa HC, Huybers MTM. 1/f noise in polycrystalline silicon resistors. J Appl Phys 1983;54:2504±7. [15] Jang SL. A model of 1/f noise in polysilicon resistors. Solid-State Electron 1990;33:1155±62. [16] Surya C, Hsiang TY. Surface mobility ¯uctuations in metal-oxide-semiconductor ®eld eect transistors. Phys Rev B 1987;35:6343±7. [17] Chen XY, Salm C. Doping dependence of low frequency noise in polycrystalline SiGe ®lm resistors. J Appl Phys 1999;75:516±8. [18] Luo M-Y, Bosman G. An analytical model for 1/f noise in polycrystalline silicon thin ®lms. IEEE Trans Electron Dev 1990;37:768±73. [19] Dimitriadis CA. Grain boundary potential barrier inhomogeneities in low pressure chemical vapor deposited polycrystalline silicon thin ®lm transistors. IEEE Trans Electron Dev 1997;44:1563±5. [20] Vandamme LKJ. Model for 1/f noise in MOS transistor biased in the linear region. Solid-State Electron 1980; 33:317±23. [21] Hooge FN, Kedzia J, Vandamme LKJ. Boundary scattering and 1/f noise. J Appl Phys 1979;50:8087±9.