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Low power & high gain differential amplifier using 16 nm FinFET
Microprocessors and Microsystems 71 (2019) 102873
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Low power & high gain differential amplifier using 16 nm FinFET J.K. Kasthuri Bha∗, P. Aruna Priya Department of Electronics and Communication, SRM Institute of Science and Technology, Kattankulathur-603203, Chennai, India
a r t i c l e
i n f o
Article history: Received 23 June 2019 Revised 5 August 2019 Accepted 14 August 2019 Available online 17 August 2019 Keywords: FinFET Conventional CMOS The mixed mode signal Operational transconductance amplifier The differential amplifier
a b s t r a c t A low noise, two- stage differential operational amplifiers are designed in 16 nm FinFET technology are presented. The proposed design would be applied in high-speed system on chips (SOCs). The low leakage current, low power dissipation and high current driving abilities of the FinFET are taken into realization with a basic analog building block of OPAMP. In this proposed design dynamic biasing technique is used for enhancing the slew rate of the OPAMP. The input common mode range (ICMR) can be increased and the gain stability is improved by this technique. The performance of a differential amplifier is analyzed using mixed mode device and circuit simulation on FinFET in sub-16-nm node technologies. It observed that by using the FinFET based OPAMP has common mode rejection ratio is 76 dB with improved performance regarding the area, power, and bandwidth. The proposed design has less 1/f noise and better performance that can replace conventional MOSFET in low power Nano circuits. © 2019 Elsevier B.V. All rights reserved.
1. Introduction Operational Amplifier (Op-Amp) is mostly used as a main block in the analog and mixed-signal systems. High speed applications such as analog to digital converter (ADC) and digital to analog converter (DAC) increases the demand for high gain amplifiers. To obtain high voltage gain in the OPAMP, the analog designer often used long channel MOSFET in the OPAMP and avoid the short channel effect [1]. As analog devices are scaled down to the nanometer, innovative design techniques are required to obtain excellent analog metrics. Designing an OPAMP with high gain bandwidth using CMOS is a big challenge for the analog designers. Reducing the channel length of the CMOS achieves larger bandwidth, but there is a trade off in the 1/f noise. The 1/f noise can be minimized by increasing the size of the transistor, but it provides high parasitic capacitances which affect the unity gain frequency by generating poles at the high frequency range. Improvement in the slew rate of OPAMP increases the switching speed and affects the non-linearity in the OPAMP [3,4]. This degradation in performance can be improved by scaling down the transistor dimension. However scaling and operating the transistor on low supply voltage for high-frequency operation will be challenging. Though scaling enhances the power consumption, speed, gain, cost, etc., worsens the short channel effect which leads to higher off ∗
Corresponding author. E-mail addresses: [email protected], [email protected] (J.K. Kasthuri Bha), [email protected], [email protected] (P. Aruna Priya). https://doi.org/10.1016/j.micpro.2019.102873 0141-9331/© 2019 Elsevier B.V. All rights reserved.
current, poor performance in impedance matching, enhancement of noise and a reduction in the high frequency open loop gain. To counteract these effects, a new approach is introduced “Beyond CMOS Devices,” to replace the existing scaled CMOS devices [2]. FinFET offers good tradeoff for power delay. Low power design can achieve by utilizing FinFET. The concept of FinFET improves the performance of the transistor appreciably because their size is minimized compared to planar CMOS transistor. The significance of FinFET is good control of gate to reduce the off current and diminishes the short channel effects with the aid of double gate which is positioned opposite to each other leads to the gate to channel coupling doubled and decreases the total power dissipation [5–6]. FinFET reduces lower drain-to-source leakage current in the off state and increases intrinsic transistor gain. This paper focused on the introduction of FinFET to design RF circuits. In this work, based on the advantages of the FinFET transistor, a FinFET based operational transconductance amplifier (OTA) circuit is designed. To increase the gain in an OPAMP cascode of transistors are used but limits the output swing [7,12–13]. In such cases, cascade OPAMP should be used to boost the gain and large output swing in the output but each gain stage introduces at least one pole in the open loop transfer function affects the stability in the feedback loop. To improve the stability frequency compensation technique is required. RC Miller compensation technique has used for frequency compensation [8–11]. The design is implemented with 16 nm predictive technology model (PTM) FinFET and tested in SPICE simulation environment. The simulation results are given and concluded.
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J.K. Kasthuri Bha and P. Aruna Priya / Microprocessors and Microsystems 71 (2019) 102873
Fig. 1. 3D schematic side view of 16 nm FinFET.
Fig. 2. 2D Cross section view of FinFET.
2. FinFET device structure The device structure and cross sectional view of FinFET structure is shown in Figs. 1 and 2, respectively. The OFF state leakage is mainly due to the higher generation and recombination of an electron when the gate voltage is lesser than the threshold voltage. From the Fig. 3 shows that the threshold voltage for the nanoscale FinFET is 0.5v. The gate terminal of the FinFET is wrapped on the three sides of the channel. This allows the formation of several gate electrodes so as to enhance the drive current and reduce the leakage current. From Fig. 3b log scale of drain current is examined that the FinFET has the low OFF state leakage which highly contributes to the improvement of short channel effect (SCE). The nanoscale FinFET structure has lesser OFF state leakage current which leads to lessr power consumption.
Fig. 3. (a): Comparison of drain current (ID ) versus Gate voltage (VGS ) in linear scale. (b): Comparison of Drain current (ID ) versus Gate voltage (VGS ) in log scale.
3. Two stage differential OPAMP topology Two-stage OPAMP consists of a differential amplifier in the first stage provide high gain followed by a common source amplifier in the second stage increases the gain and also ensure high output voltage swing. The differential amplifier provides the differential voltage that the two inputs are enforced between the inverting and non-inverting terminals. Current mirror topology is a circuit designed to follow the differential signal to the single ended output voltage and afford active loads to the RF circuits. The additional amplification provided by the common source amplifier act as an output buffer. The biasing circuit provides each transistor on operating in the saturation region. At high frequencies, compensation circuitry provides the stability to an operational amplifier when negative feedback is applied to it. The simplified block is shown in Fig. 4.
Fig. 4. Block diagram of a conventional differential amplifier.
4. Circuit specification of the two-stage OPAMP The two-stage differential amplifier has to provide high gain and output swing. Small signal differential gain can be obtained by using small signal analysis.
J.K. Kasthuri Bha and P. Aruna Priya / Microprocessors and Microsystems 71 (2019) 102873
The NMOS transistors (M1 and M2) acts as the input of the first stage of the differential amplifier and the NMOS transistors (M3 and M4) is served as an active load. The first stage of the voltage gain of the differential amplifier is given by Av1are. First stage voltage gain
Av 1 = Gm1 R1 = gm2 (ro2 ||ro4 )
fz =
(2)
(3)
Ao = −gm2 gm6 (r02 ||r04 )(r06 ||r07 )
(4)
Frequency Characteristics: To provide high stability in the high frequency operation of the two stage FinFET OPAMP, the two stages are linked together by a Miller capacitance (Cc ). The total capacitance of first stage C1 is
C1 = CGD2 + CDB2 + CGD4 + CDB4 + CGS6
(5)
The total capacitance of second stage C2 is
C2 = CDB6 + CDB7 + CGD7 + CL
(6)
Since CL is much larger than transistor capacitance C2 > C1. Transfer function:
S1 = −1 (c R + c R + C (G R R + R + R )) c 1 1 2 2 m2 1 2 1 2 (C1 R1 + C2 R2 + Cc (Gm2 R1 R2 + R1 + R2 )) S2 = − [C1C2 + Cc (C1 + C2 )]R1 R2
(7)
At high frequency operation the shunt feedback loop is formed between the drain and the gate of nano FinFET transistor (M6) and also the Miller capacitance (CC ) enhances the feedback path to increase the closed loop stability. The dominant pole can be calculated if the capacitors of Vout1 and Vout2 are known.
1 2π R1 [C1 + Cc (1 + Gm2 R2 )] Gm2Cc = 2π [C1C2 + C1Cc (1 + C2Cc )]
fd = fnd
(8)
The gain-bandwidth product (GBW ) is scrutinised to obtain the frequency performance of the two stage nano FinFET OPAMP.
GBW = Aox fd = GBW =
gm1 Cc
1 W μ pCox 2π Cc L
(9) VGST 1
From (9) and (10) we noticed the contrary, that the increase in Miller capacitance increases the stability and decreases the gain bandwidth. But designing the two-stage OPAMP using nano FinFET increases the effective mobility with the aid of fin type controlled gate than the conventional CMOS and as a result, increases the transconductance (Gm ). From (9) the gain bandwidth increases and the unity gain frequency are larger. Second Pole frequency
1 R2 −1 2π Cc gm6
−1 (10)
⎡
⎤2
W/ L
2 ⎣ 12 − 1⎦ IB = k pn (W/L )12 R2B W/ L 13 RB =
The overall closed loop voltage gain contributed by the twostage FinFET OPAMP is the product of the two- individual voltage gain. Total DC open loop voltage gain
Ao = Av1 Av2
gm6 2π CL
Where resistance of M14 is R2 Bias circuit: Bias current IB is
(1)
In the second stage of the differential amplifier, the NMOS transistor (M6) act as a common source amplifier to enhance the gain of the first stage signal and loaded with an NMOS transistor (M7) to behave as an active load. The second stage of the voltage gain Av2 is Second stage voltage gain
Av 2 = −gm6 (r o6 ||ro7 )
fnd =
3
⎡
⎣
12 − 1⎦
W/ L
2 k pn (W/L )12 IB
W/ L
⎤ (11)
13
Transconductance
gmi
IDSi W/L i = gm12 IB W/L
12
IDS j W/L j g j = gm12 IB W/L
(12)
12
From the above relation, it is assumed that all the transistors are operating in saturation mode. The slew rate value depends on the miller capacitance Cc and the bias current of (M5) transistor. In nano FinFET transistor (M5) the on state current (I5 ) is two times greater than the conventional CMOS, as the gate of the FinFET is wrapped on the channel to obtain the higher slew rate. 5. Design methodology of two stage OPAMP FinFET represents fin-shaped Field effect transistor. The essential choice of applying nano FinFET in this circuit design is operated at lower voltage and the operation speed is higher. The 16 nm FinFET size used to reduce the off state leakage current and reduces the power consumption in the design [6–8]. The topology of this circuit Fig 5 is two-stage FinFET OPAMP consists of three section namely differential gain stage, common source gain stage and biasing stage. 5.1. Differential Gain stage Transistor M1, M2, M3, M4 and M5 form the first stage of OPAMP, the differential to single-ended conversion. The gate of transistor M1 act as a non-inverting terminal and M2 as inverting terminal of the operational amplifier, differential input signals are applied to the two input terminals will be amplified depending on the gain of the differential stage. The gain of this input stage is the transconductance of M1 times the total output resistance at the drain of M2. The transistor M3 and M4 act as the current mirror have three main advantages. First, it used as active load devices to creates a large output resistance in a relatively small amount of chip area. Secondly, performs the conversion of a differential to single- ended by mirroring the current from M1 and subtracted it to M2 of the input signal which applied to the input of the next stage. Finally, the load helps to maintain common mode rejection ratio. The transistor M5 provides constant bias for differential pair.
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J.K. Kasthuri Bha and P. Aruna Priya / Microprocessors and Microsystems 71 (2019) 102873
Fig. 6. Schematic diagram of FinFET two stage OPAMP.
Fig. 5. Two stage differential amplifier using FinFET.
5.2. Common Source gain stage The 16 nm FinFET (M6) and (M7) forms the output bias current pair to provide additional gain. This stage acts current sink active load inverter, receives the output from the nano FinFET (M2) and to increase the gain of the received signal, the signal is amplified through nano FinFET (M6) by common source configuration. The nano FinFET (M7) serves as active load for nano FinFET (M6). The gain of this stage is the transconductance of M6 times the equivalent load resistance seen at the output of M6 and M7. Fig. 7. Transient response of FinFET two stage OPAMP.
5.3. Biasing Circuit In the design, M8, M9, M10, M11, M12, and M13 are the current mirror nano FinFET transistors to form a biasing network and provide a current source between the nano FinFET transistors M5 and M7. Transistor M5 provides constant current bias for the differential pair transistor to provide a very high source resistance and M7 serve as output bias current. And also transistors M5 and M7 act as a current sink for the bias network. 5.4. Frequency Compensation network At high frequencies, the stray capacitances can cause unwanted phase shift and it is difficult to eliminate. The frequency compensated capacitor Cc connected in series provides negative feedback to maintain stable operation. But in a closed loop system, an additional pole is introduced in an amplification stage. The phase falls down, if the new pole location is less than the dominant pole present in system. So for a stable operation we need to maintain good amount of phase margin. The frequency compensation removes the effects of the poles in frequency response. We have used a RC miller compensation technique to improve the stability. 6. Simulation results 6.1. Transient analysis The transient analysis shown in Fig. 6. of FinFET differential amplifier with current mirror circuit shows the amplified version of an input signal. The simulated output is shown in Fig. 7. The input applied is 100μv with a frequency of 100 kHz.
Fig. 8. Schematic diagram of Two stage OPAMP with gain enhancement Technique.
6.2. Ac Analysis The AC analysis Fig. 8. shows a change in the output when the input is applied to the input signal. Fig. 9 shows the open loop frequency response of two-stage OPAMP using FINFET. The gain of the OPAMP measured to be 23 dB. To get high gain bandwidth product need to increase M1 and M2 tube overdrive voltage to reduce its channel length. The gain of the device is proportional to the transconductance which yields higher cutoff frequency (ft ). The gain-bandwidth product was found by estimating the unity gain frequency at 5.07 GHz. The slew rate is how fast the output can swing without distortion. From Fig. 10 it was
J.K. Kasthuri Bha and P. Aruna Priya / Microprocessors and Microsystems 71 (2019) 102873
5
Table 1 Simulation result table.
Fig. 9. The gain of Two stage OPAMP.
Parameters
[1](Implemented in 32 nm CMOS Tech.)
Proposed Method (Implemented in16nm FinFET Tech.)
VDD (V) Gain Gain(dB) Unity gain Frequency Power Consumption Slew rate CMRR
1.8v 1.42 3.04 dB 1100 M
1.8v 15.358 23.7 dB 5.07 GHz
846.2μW
537.1μW
30,500 V/μs 16.93dB
17,500 V/μs 76.67dB
frequency is observed as 5.07 GHz suitable to operate at high frequency applications. From the table it can be observed that low power dissipation in operational amplifier has significantly low in 16 nm FinFET technology. It is noted that the slew rate is 17,500 V/μs well suited for high speed application. 7. Conclusion
Fig. 10. Slew rate of a two stage OPAMP.
Designing a two-stage OPAMP using 16 nm FinFET is a multidimensional problem. Optimization of one parameter of the differential OPAMP like closed loop voltage gain, unity gain bandwidth, slew rate and common mode rejection ratio may easily degrades the characteristics of the other parameters. Also, designer finds constant barrier in designing the 16 nm FinFET predictive technology for high frequency and larger bandwidth applications. Here the overall gain has been improved by using 16 nm FinFET technology. From the design iis observed that the high transconductance FinFET can improves the gain to a larger extent compared to conventional CMOS. Here the unity gain frequency has improved to 5 GHz by raising the bias current and also FinFET reduces the power dissipation to a larger extent and leads a good control over wide range of bandwidth but increases the parasitic resistance and capacitance. Introduction of each stage exhibits an additional pole into the OPAMP which creates problems in stability. Thus a proper RC Miller compensation technique has employed to improve the stability. Declaration of Competing Interest
Fig. 11. Phase Plot of two stage OPAMP.
observed that the proposed OPAMP slew at a rate of 17,500 V/μs for the rising slope and 11,0 0 0 V/μs for the falling slope. This slew rate is very high compared to that of conventional OPAMP and it can be applied for high frequency application. The total power consumption for the OPAMP was 537.1μW.The frequency of operation of two stage OPAMP is 5 GHz. Due to RC compensation circuit, the phase has improved to 180 deg from Fig. 11. The high frequency compensation capacitance makes the power supply rejection ratio (PSRR) to be large at the output. The Compensation circuit improves the unity gain bandwidth by boosting the bias current but diminishes the DC gain. However there is decrease in power dissipation in the design by using FinFET to enhance the operational amplifier to operate at high frequency. From the Table 1 it is concluded that the two stage FinFET OPAMP parameters like overall voltage gain, unity gain frequency and the slew rate has significantly increases with the 16 nm FinFET technology. In this design the overall voltage gain is 23.7db significantly higher than the 32 nm CMOS design. The Unity gain
We wish to confirm that there are no known conflicts of interest associated with this publication and there has been no significant financial support for this work that could have influenced its outcome. Reference [1] Aniket Vikhe, Comparative performance analysis of single stage differential amplifier at 32 nanometer regime, in: Proceedings of the International Conference on Energy Systems and Applications, ICESA 2015, 2015. [2] Zhihao, et al., An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs, Microelectronics J (2011) 515–519. [3] K.N. Abhilash, Shakthi Bose, Anu Gupta, A high gain, high cmrr two-stage fully differential amplifier using gm/Id technique for bio-medical applications, Microelectr. J. (2014) 4pp. [4] Yu-Ming Hsiao, Miin-Shyue Shiau, Kuen-Han Li, et al., “Design a bioamplifier with high CMRR, VLSI Des. 2013 (2013) 5 Article ID 210 265pages, doi:10.1155/ 2013/210265. [5] Rajesh A. Thakker, et al., A novel architecture for improving slew rate in FinFET-based OPAMPS and OTAs, Microelectr. J. (2011), doi:10.1016/j.mejo.2011. 01.010. [6] Ashutosh Nandia, n, Ashok K. Saxenab, Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET, Mincroelectr. J. (2016) 0026-2692/&. [7] Rajesh A. Thakker, et al., A novel table-based approach for design of FinFET circuits, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (7) (2009).
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[8] Abhinav Kranti, G. Alastair Armstrong, Nonclassical channel design in MOSFETs for improving ota gain-bandwidth trade-off, IEEE Trans. Circuits Syst. 7 (12) (December 2010). [9] Ankur Gupta, Satish Kumar, A high gain OTA with slew rate enhancement technique in 45nm FinFET technology, Int. J. Adv. Res. Comput. Commun. Eng 6 (11) (2017) ISO 3297:2007 Certified. [10] G. Pei, E.C.-C. Kan, Independently driven dg MOSFETs for mixed-signal circuits: part I-quasi-static and nonquasi-static channel coupling, IEEE Trans. Electron. Devices 51 (2004) 2086. [11] Haj Al Rai Hi, Microcomputer controlled – magnetic amplifier power supply, Microprocess. Microsyst. 9 (2) (March 1985). [12] J.K. Kasthuri Bha, P. Aruna Priya, Power optimization of transceiver with cascade low noise amplifier using FinFET, in: Proceedings of the International Conference on Signal Processing, 2016. [13] David Ponton, et al., Design of ultra wideband low noise amplifiers in 45nm CMOS technology: comparison between planar bulk and SOI FinFET devices, IEEE Trans. Circuit Syst. 56 (2009). J.K.Kasthuri Bha received B.E degree in Electronics and communication from Madras University, and M.Tech degree in VLSI from SRM University, chennai. Her research interests include Nano-electronics, device modeling and circuit design using nano scale devices. She is currently working as an Assistant Professor in the department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Chennai.
P. Aruna Priya received Ph.D. degree in 2011 from SRM University in the area of Nano-electronics. Her research interests include Nano-electronics, Plasmonic Nanoantenna, Intelligent Automation and Image processing. She is currently working as a Professor in the Department of Electronics and Communication Engineering at SRM Institute of Science and Technology, Chennai.
Contents lists available at ScienceDirect
Microprocessors and Microsystems journal homepage: www.elsevier.com/locate/micpro
Low power & high gain differential amplifier using 16 nm FinFET J.K. Kasthuri Bha∗, P. Aruna Priya Department of Electronics and Communication, SRM Institute of Science and Technology, Kattankulathur-603203, Chennai, India
a r t i c l e
i n f o
Article history: Received 23 June 2019 Revised 5 August 2019 Accepted 14 August 2019 Available online 17 August 2019 Keywords: FinFET Conventional CMOS The mixed mode signal Operational transconductance amplifier The differential amplifier
a b s t r a c t A low noise, two- stage differential operational amplifiers are designed in 16 nm FinFET technology are presented. The proposed design would be applied in high-speed system on chips (SOCs). The low leakage current, low power dissipation and high current driving abilities of the FinFET are taken into realization with a basic analog building block of OPAMP. In this proposed design dynamic biasing technique is used for enhancing the slew rate of the OPAMP. The input common mode range (ICMR) can be increased and the gain stability is improved by this technique. The performance of a differential amplifier is analyzed using mixed mode device and circuit simulation on FinFET in sub-16-nm node technologies. It observed that by using the FinFET based OPAMP has common mode rejection ratio is 76 dB with improved performance regarding the area, power, and bandwidth. The proposed design has less 1/f noise and better performance that can replace conventional MOSFET in low power Nano circuits. © 2019 Elsevier B.V. All rights reserved.
1. Introduction Operational Amplifier (Op-Amp) is mostly used as a main block in the analog and mixed-signal systems. High speed applications such as analog to digital converter (ADC) and digital to analog converter (DAC) increases the demand for high gain amplifiers. To obtain high voltage gain in the OPAMP, the analog designer often used long channel MOSFET in the OPAMP and avoid the short channel effect [1]. As analog devices are scaled down to the nanometer, innovative design techniques are required to obtain excellent analog metrics. Designing an OPAMP with high gain bandwidth using CMOS is a big challenge for the analog designers. Reducing the channel length of the CMOS achieves larger bandwidth, but there is a trade off in the 1/f noise. The 1/f noise can be minimized by increasing the size of the transistor, but it provides high parasitic capacitances which affect the unity gain frequency by generating poles at the high frequency range. Improvement in the slew rate of OPAMP increases the switching speed and affects the non-linearity in the OPAMP [3,4]. This degradation in performance can be improved by scaling down the transistor dimension. However scaling and operating the transistor on low supply voltage for high-frequency operation will be challenging. Though scaling enhances the power consumption, speed, gain, cost, etc., worsens the short channel effect which leads to higher off ∗
Corresponding author. E-mail addresses: [email protected], [email protected] (J.K. Kasthuri Bha), [email protected], [email protected] (P. Aruna Priya). https://doi.org/10.1016/j.micpro.2019.102873 0141-9331/© 2019 Elsevier B.V. All rights reserved.
current, poor performance in impedance matching, enhancement of noise and a reduction in the high frequency open loop gain. To counteract these effects, a new approach is introduced “Beyond CMOS Devices,” to replace the existing scaled CMOS devices [2]. FinFET offers good tradeoff for power delay. Low power design can achieve by utilizing FinFET. The concept of FinFET improves the performance of the transistor appreciably because their size is minimized compared to planar CMOS transistor. The significance of FinFET is good control of gate to reduce the off current and diminishes the short channel effects with the aid of double gate which is positioned opposite to each other leads to the gate to channel coupling doubled and decreases the total power dissipation [5–6]. FinFET reduces lower drain-to-source leakage current in the off state and increases intrinsic transistor gain. This paper focused on the introduction of FinFET to design RF circuits. In this work, based on the advantages of the FinFET transistor, a FinFET based operational transconductance amplifier (OTA) circuit is designed. To increase the gain in an OPAMP cascode of transistors are used but limits the output swing [7,12–13]. In such cases, cascade OPAMP should be used to boost the gain and large output swing in the output but each gain stage introduces at least one pole in the open loop transfer function affects the stability in the feedback loop. To improve the stability frequency compensation technique is required. RC Miller compensation technique has used for frequency compensation [8–11]. The design is implemented with 16 nm predictive technology model (PTM) FinFET and tested in SPICE simulation environment. The simulation results are given and concluded.
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J.K. Kasthuri Bha and P. Aruna Priya / Microprocessors and Microsystems 71 (2019) 102873
Fig. 1. 3D schematic side view of 16 nm FinFET.
Fig. 2. 2D Cross section view of FinFET.
2. FinFET device structure The device structure and cross sectional view of FinFET structure is shown in Figs. 1 and 2, respectively. The OFF state leakage is mainly due to the higher generation and recombination of an electron when the gate voltage is lesser than the threshold voltage. From the Fig. 3 shows that the threshold voltage for the nanoscale FinFET is 0.5v. The gate terminal of the FinFET is wrapped on the three sides of the channel. This allows the formation of several gate electrodes so as to enhance the drive current and reduce the leakage current. From Fig. 3b log scale of drain current is examined that the FinFET has the low OFF state leakage which highly contributes to the improvement of short channel effect (SCE). The nanoscale FinFET structure has lesser OFF state leakage current which leads to lessr power consumption.
Fig. 3. (a): Comparison of drain current (ID ) versus Gate voltage (VGS ) in linear scale. (b): Comparison of Drain current (ID ) versus Gate voltage (VGS ) in log scale.
3. Two stage differential OPAMP topology Two-stage OPAMP consists of a differential amplifier in the first stage provide high gain followed by a common source amplifier in the second stage increases the gain and also ensure high output voltage swing. The differential amplifier provides the differential voltage that the two inputs are enforced between the inverting and non-inverting terminals. Current mirror topology is a circuit designed to follow the differential signal to the single ended output voltage and afford active loads to the RF circuits. The additional amplification provided by the common source amplifier act as an output buffer. The biasing circuit provides each transistor on operating in the saturation region. At high frequencies, compensation circuitry provides the stability to an operational amplifier when negative feedback is applied to it. The simplified block is shown in Fig. 4.
Fig. 4. Block diagram of a conventional differential amplifier.
4. Circuit specification of the two-stage OPAMP The two-stage differential amplifier has to provide high gain and output swing. Small signal differential gain can be obtained by using small signal analysis.
J.K. Kasthuri Bha and P. Aruna Priya / Microprocessors and Microsystems 71 (2019) 102873
The NMOS transistors (M1 and M2) acts as the input of the first stage of the differential amplifier and the NMOS transistors (M3 and M4) is served as an active load. The first stage of the voltage gain of the differential amplifier is given by Av1are. First stage voltage gain
Av 1 = Gm1 R1 = gm2 (ro2 ||ro4 )
fz =
(2)
(3)
Ao = −gm2 gm6 (r02 ||r04 )(r06 ||r07 )
(4)
Frequency Characteristics: To provide high stability in the high frequency operation of the two stage FinFET OPAMP, the two stages are linked together by a Miller capacitance (Cc ). The total capacitance of first stage C1 is
C1 = CGD2 + CDB2 + CGD4 + CDB4 + CGS6
(5)
The total capacitance of second stage C2 is
C2 = CDB6 + CDB7 + CGD7 + CL
(6)
Since CL is much larger than transistor capacitance C2 > C1. Transfer function:
S1 = −1 (c R + c R + C (G R R + R + R )) c 1 1 2 2 m2 1 2 1 2 (C1 R1 + C2 R2 + Cc (Gm2 R1 R2 + R1 + R2 )) S2 = − [C1C2 + Cc (C1 + C2 )]R1 R2
(7)
At high frequency operation the shunt feedback loop is formed between the drain and the gate of nano FinFET transistor (M6) and also the Miller capacitance (CC ) enhances the feedback path to increase the closed loop stability. The dominant pole can be calculated if the capacitors of Vout1 and Vout2 are known.
1 2π R1 [C1 + Cc (1 + Gm2 R2 )] Gm2Cc = 2π [C1C2 + C1Cc (1 + C2Cc )]
fd = fnd
(8)
The gain-bandwidth product (GBW ) is scrutinised to obtain the frequency performance of the two stage nano FinFET OPAMP.
GBW = Aox fd = GBW =
gm1 Cc
1 W μ pCox 2π Cc L
(9) VGST 1
From (9) and (10) we noticed the contrary, that the increase in Miller capacitance increases the stability and decreases the gain bandwidth. But designing the two-stage OPAMP using nano FinFET increases the effective mobility with the aid of fin type controlled gate than the conventional CMOS and as a result, increases the transconductance (Gm ). From (9) the gain bandwidth increases and the unity gain frequency are larger. Second Pole frequency
1 R2 −1 2π Cc gm6
−1 (10)
⎡
⎤2
W/ L
2 ⎣ 12 − 1⎦ IB = k pn (W/L )12 R2B W/ L 13 RB =
The overall closed loop voltage gain contributed by the twostage FinFET OPAMP is the product of the two- individual voltage gain. Total DC open loop voltage gain
Ao = Av1 Av2
gm6 2π CL
Where resistance of M14 is R2 Bias circuit: Bias current IB is
(1)
In the second stage of the differential amplifier, the NMOS transistor (M6) act as a common source amplifier to enhance the gain of the first stage signal and loaded with an NMOS transistor (M7) to behave as an active load. The second stage of the voltage gain Av2 is Second stage voltage gain
Av 2 = −gm6 (r o6 ||ro7 )
fnd =
3
⎡
⎣
12 − 1⎦
W/ L
2 k pn (W/L )12 IB
W/ L
⎤ (11)
13
Transconductance
gmi
IDSi W/L i = gm12 IB W/L
12
IDS j W/L j g j = gm12 IB W/L
(12)
12
From the above relation, it is assumed that all the transistors are operating in saturation mode. The slew rate value depends on the miller capacitance Cc and the bias current of (M5) transistor. In nano FinFET transistor (M5) the on state current (I5 ) is two times greater than the conventional CMOS, as the gate of the FinFET is wrapped on the channel to obtain the higher slew rate. 5. Design methodology of two stage OPAMP FinFET represents fin-shaped Field effect transistor. The essential choice of applying nano FinFET in this circuit design is operated at lower voltage and the operation speed is higher. The 16 nm FinFET size used to reduce the off state leakage current and reduces the power consumption in the design [6–8]. The topology of this circuit Fig 5 is two-stage FinFET OPAMP consists of three section namely differential gain stage, common source gain stage and biasing stage. 5.1. Differential Gain stage Transistor M1, M2, M3, M4 and M5 form the first stage of OPAMP, the differential to single-ended conversion. The gate of transistor M1 act as a non-inverting terminal and M2 as inverting terminal of the operational amplifier, differential input signals are applied to the two input terminals will be amplified depending on the gain of the differential stage. The gain of this input stage is the transconductance of M1 times the total output resistance at the drain of M2. The transistor M3 and M4 act as the current mirror have three main advantages. First, it used as active load devices to creates a large output resistance in a relatively small amount of chip area. Secondly, performs the conversion of a differential to single- ended by mirroring the current from M1 and subtracted it to M2 of the input signal which applied to the input of the next stage. Finally, the load helps to maintain common mode rejection ratio. The transistor M5 provides constant bias for differential pair.
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Fig. 6. Schematic diagram of FinFET two stage OPAMP.
Fig. 5. Two stage differential amplifier using FinFET.
5.2. Common Source gain stage The 16 nm FinFET (M6) and (M7) forms the output bias current pair to provide additional gain. This stage acts current sink active load inverter, receives the output from the nano FinFET (M2) and to increase the gain of the received signal, the signal is amplified through nano FinFET (M6) by common source configuration. The nano FinFET (M7) serves as active load for nano FinFET (M6). The gain of this stage is the transconductance of M6 times the equivalent load resistance seen at the output of M6 and M7. Fig. 7. Transient response of FinFET two stage OPAMP.
5.3. Biasing Circuit In the design, M8, M9, M10, M11, M12, and M13 are the current mirror nano FinFET transistors to form a biasing network and provide a current source between the nano FinFET transistors M5 and M7. Transistor M5 provides constant current bias for the differential pair transistor to provide a very high source resistance and M7 serve as output bias current. And also transistors M5 and M7 act as a current sink for the bias network. 5.4. Frequency Compensation network At high frequencies, the stray capacitances can cause unwanted phase shift and it is difficult to eliminate. The frequency compensated capacitor Cc connected in series provides negative feedback to maintain stable operation. But in a closed loop system, an additional pole is introduced in an amplification stage. The phase falls down, if the new pole location is less than the dominant pole present in system. So for a stable operation we need to maintain good amount of phase margin. The frequency compensation removes the effects of the poles in frequency response. We have used a RC miller compensation technique to improve the stability. 6. Simulation results 6.1. Transient analysis The transient analysis shown in Fig. 6. of FinFET differential amplifier with current mirror circuit shows the amplified version of an input signal. The simulated output is shown in Fig. 7. The input applied is 100μv with a frequency of 100 kHz.
Fig. 8. Schematic diagram of Two stage OPAMP with gain enhancement Technique.
6.2. Ac Analysis The AC analysis Fig. 8. shows a change in the output when the input is applied to the input signal. Fig. 9 shows the open loop frequency response of two-stage OPAMP using FINFET. The gain of the OPAMP measured to be 23 dB. To get high gain bandwidth product need to increase M1 and M2 tube overdrive voltage to reduce its channel length. The gain of the device is proportional to the transconductance which yields higher cutoff frequency (ft ). The gain-bandwidth product was found by estimating the unity gain frequency at 5.07 GHz. The slew rate is how fast the output can swing without distortion. From Fig. 10 it was
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Table 1 Simulation result table.
Fig. 9. The gain of Two stage OPAMP.
Parameters
[1](Implemented in 32 nm CMOS Tech.)
Proposed Method (Implemented in16nm FinFET Tech.)
VDD (V) Gain Gain(dB) Unity gain Frequency Power Consumption Slew rate CMRR
1.8v 1.42 3.04 dB 1100 M
1.8v 15.358 23.7 dB 5.07 GHz
846.2μW
537.1μW
30,500 V/μs 16.93dB
17,500 V/μs 76.67dB
frequency is observed as 5.07 GHz suitable to operate at high frequency applications. From the table it can be observed that low power dissipation in operational amplifier has significantly low in 16 nm FinFET technology. It is noted that the slew rate is 17,500 V/μs well suited for high speed application. 7. Conclusion
Fig. 10. Slew rate of a two stage OPAMP.
Designing a two-stage OPAMP using 16 nm FinFET is a multidimensional problem. Optimization of one parameter of the differential OPAMP like closed loop voltage gain, unity gain bandwidth, slew rate and common mode rejection ratio may easily degrades the characteristics of the other parameters. Also, designer finds constant barrier in designing the 16 nm FinFET predictive technology for high frequency and larger bandwidth applications. Here the overall gain has been improved by using 16 nm FinFET technology. From the design iis observed that the high transconductance FinFET can improves the gain to a larger extent compared to conventional CMOS. Here the unity gain frequency has improved to 5 GHz by raising the bias current and also FinFET reduces the power dissipation to a larger extent and leads a good control over wide range of bandwidth but increases the parasitic resistance and capacitance. Introduction of each stage exhibits an additional pole into the OPAMP which creates problems in stability. Thus a proper RC Miller compensation technique has employed to improve the stability. Declaration of Competing Interest
Fig. 11. Phase Plot of two stage OPAMP.
observed that the proposed OPAMP slew at a rate of 17,500 V/μs for the rising slope and 11,0 0 0 V/μs for the falling slope. This slew rate is very high compared to that of conventional OPAMP and it can be applied for high frequency application. The total power consumption for the OPAMP was 537.1μW.The frequency of operation of two stage OPAMP is 5 GHz. Due to RC compensation circuit, the phase has improved to 180 deg from Fig. 11. The high frequency compensation capacitance makes the power supply rejection ratio (PSRR) to be large at the output. The Compensation circuit improves the unity gain bandwidth by boosting the bias current but diminishes the DC gain. However there is decrease in power dissipation in the design by using FinFET to enhance the operational amplifier to operate at high frequency. From the Table 1 it is concluded that the two stage FinFET OPAMP parameters like overall voltage gain, unity gain frequency and the slew rate has significantly increases with the 16 nm FinFET technology. In this design the overall voltage gain is 23.7db significantly higher than the 32 nm CMOS design. The Unity gain
We wish to confirm that there are no known conflicts of interest associated with this publication and there has been no significant financial support for this work that could have influenced its outcome. Reference [1] Aniket Vikhe, Comparative performance analysis of single stage differential amplifier at 32 nanometer regime, in: Proceedings of the International Conference on Energy Systems and Applications, ICESA 2015, 2015. [2] Zhihao, et al., An analytical model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETs, Microelectronics J (2011) 515–519. [3] K.N. Abhilash, Shakthi Bose, Anu Gupta, A high gain, high cmrr two-stage fully differential amplifier using gm/Id technique for bio-medical applications, Microelectr. J. (2014) 4pp. [4] Yu-Ming Hsiao, Miin-Shyue Shiau, Kuen-Han Li, et al., “Design a bioamplifier with high CMRR, VLSI Des. 2013 (2013) 5 Article ID 210 265pages, doi:10.1155/ 2013/210265. [5] Rajesh A. Thakker, et al., A novel architecture for improving slew rate in FinFET-based OPAMPS and OTAs, Microelectr. J. (2011), doi:10.1016/j.mejo.2011. 01.010. [6] Ashutosh Nandia, n, Ashok K. Saxenab, Oxide thickness and S/D junction depth based variation aware OTA design using underlap FinFET, Mincroelectr. J. (2016) 0026-2692/&. [7] Rajesh A. Thakker, et al., A novel table-based approach for design of FinFET circuits, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (7) (2009).
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[8] Abhinav Kranti, G. Alastair Armstrong, Nonclassical channel design in MOSFETs for improving ota gain-bandwidth trade-off, IEEE Trans. Circuits Syst. 7 (12) (December 2010). [9] Ankur Gupta, Satish Kumar, A high gain OTA with slew rate enhancement technique in 45nm FinFET technology, Int. J. Adv. Res. Comput. Commun. Eng 6 (11) (2017) ISO 3297:2007 Certified. [10] G. Pei, E.C.-C. Kan, Independently driven dg MOSFETs for mixed-signal circuits: part I-quasi-static and nonquasi-static channel coupling, IEEE Trans. Electron. Devices 51 (2004) 2086. [11] Haj Al Rai Hi, Microcomputer controlled – magnetic amplifier power supply, Microprocess. Microsyst. 9 (2) (March 1985). [12] J.K. Kasthuri Bha, P. Aruna Priya, Power optimization of transceiver with cascade low noise amplifier using FinFET, in: Proceedings of the International Conference on Signal Processing, 2016. [13] David Ponton, et al., Design of ultra wideband low noise amplifiers in 45nm CMOS technology: comparison between planar bulk and SOI FinFET devices, IEEE Trans. Circuit Syst. 56 (2009). J.K.Kasthuri Bha received B.E degree in Electronics and communication from Madras University, and M.Tech degree in VLSI from SRM University, chennai. Her research interests include Nano-electronics, device modeling and circuit design using nano scale devices. She is currently working as an Assistant Professor in the department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Chennai.
P. Aruna Priya received Ph.D. degree in 2011 from SRM University in the area of Nano-electronics. Her research interests include Nano-electronics, Plasmonic Nanoantenna, Intelligent Automation and Image processing. She is currently working as a Professor in the Department of Electronics and Communication Engineering at SRM Institute of Science and Technology, Chennai.