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High bandwidth transimpedance amplifier using FGMOS for low voltage operation
INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
Contents lists available at ScienceDirect
INTEGRATION, the VLSI journal journal homepage: www.elsevier.com/locate/vlsi
High bandwidth transimpedance amplifier using FGMOS for low voltage operation Urvashi Bansal, Maneesha Gupta
⁎
Division of ECE, Netaji Subhas Institute of Technology, New Delhi 110078, India
A R T I C L E I N F O
A BS T RAC T
Keywords: Analog circuits CMOS FGMOS Frequency compensation Shunt peaking TIA
In this paper a novel CMOS design of transimpedance amplifier (TIA) suitable for low-voltage low-power application is presented. A floating gate metal oxide semiconductor (FGMOS) transistor is used here in common source configuration to provide active feedback along with a standard MOSFET which acts as input stage of the circuit. Main intend of this work is to minimize supply requirement with increased linearity. The circuit of TIA presented in this paper works only at 1 V supply with small power consumption of 1.1 mW. One of the popular frequency compensation techniques is shunt peaking technique. It is employed here to extend bandwidth. The transimpedance output and − 3 dB bandwidth of proposed circuit are 37.7 dB Ohms and 13.5 GHz, respectively. The input impedance and transfer function is evaluated using mathematical analysis and small signal model of circuit. This is observed that results are improved as compared to well known regulated common gate (RC-G) amplifier.
1. Introduction The first and very important stage of every optical receiver is TIA. It not only transfers input current to an amplified output voltage to be used by subsequent stages but also commands overall system performance in terms of sensitivity, noise figure and bandwidth. Nowadays, the CMOS technology based TIAs are getting very popular due to their low cost, low volume and relaxed sensitivity requirements with comparable performance parameters [1–3]. Most of these amplifiers support current mode operation and exploit common gate configuration or shunt feedback topology [4–6]. The key issue is to handle noise performance, offered bandwidth and sensitivity requirement altogether in optimized way [7,8]. In addition, the low-voltage low-power analog circuits [9,10] demand that the circuit characteristics should not be degraded while minimizing the supply requirements. The conventional RC-G [11–13] offers low input impedance and thereby limits the large input capacitance effect. Such circuits offer extended bandwidth but their supply requirement is quite high. In such case, there is need of a suitable TIA which offers high bandwidth for low-voltage low-power circuits efficiently. The paper presented here suggests a novel design of TIA based on FGMOS called FG-TIA. The input stage of circuit is a common gate MOS transistor and active feedback is provided via common source configuration of FGMOS transistor. In order to improve frequency response of presented circuit, shunt peaking method is employed here among various prevalent bandwidth exten-
⁎
sion techniques [14,15]. The suggested circuit requires only 1 V supply with small power consumption of 1.1 mW. The paper is organized as follows. In Section 2, functioning principle of FGMOS transistor is described in brief. The proposed TIA circuit and working model is explained in Section 3. Then in same section, transfer function and impedance of proposed circuit is derived. Section 4 includes all simulation results and Section 5 concludes the paper. 2. FGMOS transistor A conventional MOSFET is transformed into FGMOS transistor when a polysilicon layer is deposited first to form floating gate and followed by deposition of secondary polysilicon layer to provide multiple input gates (G1,G2…. Gn). FGMOS transistor is analogous to MOSFET in operation with the fact that it dissipates less power and has tunable means to work below the operational limits of supply voltage level without demeaning any other characteristics. Fig. 1(a) and (b) shows a 2-input P-channel FGMOS transistor symbol and its equivalent circuit, respectively. In a FGMOS transistor, the effective gate to source voltage (VGSeff) is estimated by [10].
VGSeff =
CGD VDS + C GBVBS + C1VbS + C2 V2s + Q FG CTFG
Corresponding author. E-mail addresses: [email protected] (U. Bansal), [email protected] (M. Gupta).
http://dx.doi.org/10.1016/j.vlsi.2017.09.001 Received 3 May 2017; Received in revised form 31 July 2017; Accepted 2 September 2017 0167-9260/ © 2017 Published by Elsevier B.V.
Please cite this article as: Bansal, U., INTEGRATION the VLSI journal (2017), http://dx.doi.org/10.1016/j.vlsi.2017.09.001
(1)
INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
U. Bansal, M. Gupta
In Fig. 2(a), input signal is applied at drain terminal of M1 and amplified further. A local feedback is formed via M2 and R2 which actually trim down input impedance by the amount of its own voltage gain. The input impedance of conventional circuit [16] is derived using small signal analysis and given as:
zin (0)≅
1 gm1 (1+gm2 R2 )
(6)
where (1 + gm2R2) represents gain of local feedback stage and bandwidth of the input stage [16] is derived as:
f−3dB =
where QFG stands for the amount of charge trapped at floating gate (FG) and input voltages are Vin1 = Vb and Vin2 = V2. The connected capacitors are indicated as C1 and C2. The parasitic capacitances CGD, CGS and CGB are present between FG and other terminals. The term CTFG signifies to the total capacitance seen by FG and is calculated as CTFG = C1 + C2 + CGD + CGS + CGB. Similarly the voltage at drain (D), bulk (B), bias gate (G1) and signal gate (G2) with respect to source are denoted by VDS, VBS, VbS and V2S, respectively. The expression of drain current (ID) for a FGMOS operating in saturation region, can be given as:
gm (VGSeff − Vth)2 2
(2)
where Vth represents threshold voltage and gm is the transconductance parameter. Moreover, if it is assumed that parasitic capacitances are small and the selected value of input capacitances is such that their total is very high as match up to the parasitic capacitances than CTFG ≈ C1 + C2 and now from Eqs. (1) and (2), ID can be expressed as:
ID =
⎞2 gm ⎛ C1VbS + C2 V2s − Vth⎟ ⎜ ⎠ 2 ⎝ CTFG
z= (3)
g m ⎛ C2 ⎞ ⎜ ⎟ (V2s − V′th)2 2 ⎝ CTFG ⎠
1+RG sCgs gm + sCgs
(4)
Z (s ) = where the new threshold voltage V′th can be given as:
⎤ ⎞⎡ ⎛C C V′th = ⎜ TFG ⎟ ⎢Vth − 1 VbS⎥ ⎝ C2 ⎠ ⎣ CTFG ⎦
(8)
This circuit exploits inductor in shunt peaking style. Furthermore, the transimpedance function of a shunt peaked network [15] can be expressed as:
Eq. (3) can be rewritten as:
ID =
(7)
where αi is low frequency gain (i = 2,4) of following stages, Cf is parasitic capacitance of feedback resistor Rf, Cgd1 is gate to drain terminal capacitance and Cg2 is gate capacitance of M2. The Fig. 2(b) depicts CMOS realization of proposed FG-TIA circuit. This circuit uses standard MOS transistor M1 in common gate configuration as its input and exploits common source active feedback to reduce impedance via FGMOS transistor M2. The presence of FGMOS transistor enables low voltage operation of the circuit. In order to optimize operating bandwidth, shunt peaking technique is exercised. In this technique, an inductor L is connected in series with load resistor. The main function of inductor [15] is to introduce a zero and shunt the output capacitor. The circuit can also make use of an active inductor [17] instead of spiral inductor as latter one occupies large area, gives high parasitic capacitance and is difficult to integrate. Fig. 3(a), (b) and (c) show spiral inductor, its active realization and simplified small signal model. Here L is ideal inductor and R is the resistance of winding, rest of the symbols has their usual meaning [17]. The role of active inductor is same as for the spiral inductor. If value of Cgd, Cds and gds are considered small then overall impedance [17] can be approximated as:
Fig. 1. (a) Symbol of two input P-channel FGMOS. (b) FGMOS equivalent circuit.
ID =
1 ⎡ ⎛ Cgd1 + Cg2 ⎞ ⎤ 2πRf ⎢Cf + ⎜ 1 + α g R α ⎟ ⎥ 2 m1 3 4 ⎠ ⎦ ⎝ ⎣
vout 1 R + sL = ∣∣ (R+sCL ) = iin sCL 1+sRCL + s 2LCL
(9)
where all the symbols are typical [15]. It is clear from Eq. (9) that insertion of inductor will extend bandwidth.
(5)
It is apparent from Eq. (5) that appropriate choice of bias voltage and capacitance ratios can electronically control the threshold voltage of FGMOS transistor. This fact makes it more clear and purposeful to use FGMOS transistor in low voltage and programmable electronic devices.
3.2. Small signal analysis The small signal equivalent circuit of the proposed circuit is given in Fig. 4. Here it is assumed that parasitic capacitances are small and channel output resistance is very high for both transistors. The small signal transimpedance function of proposed TIA can be expressed by following equation.
3. Proposed TIA In view of the fact that the input signal of a TIA is current and output signal is voltage, it can be simply called a current to voltage converter and finds major applications in many areas of electronics and communication engineering.
Z (s ) =
vout 1+a1 s + b1 s 2 = Zi iin 1+a2 s + b2 s 2 + c2 s 3
(10)
In Fig. 4, iph and Cph are photocurrent and associated capacitance, respectively. The transconductance parameter of standard MOSFET is C +C gm1 and FGMOS is gmF2. It is worth noting that gmF = C1 2 gm . The TFG capacitances C1 and C2 are connected at FG and other symbols have their typical meaning. The symbol Zi(0) denotes low frequency transimpedance function and can be expressed as
3.1. Circuit description The conventional RC-G circuit [16] and the proposed FG-TIA circuit is shown in Fig. 2(a) and 2(b), respectively. Both circuits include parasitic capacitance of photodiode. The role of photodiode is to transform optical signal into electrical signal.
Z i (0) =
2
R2 = R2 ∣∣ 1/ gmF 2 1 +gmF 2 R2
(11)
INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
U. Bansal, M. Gupta
Fig. 2. (a) Conventional RC-GTIA circuit [16]. (b) Proposed FG-TIA circuit.
parameter for a TIA. The bit error rate (BER) and sensitivity of the whole optical receiver front-end is directly affected by the input referred noise spectral density. The investigation results of the equivalent input noise current characteristics can be deduced as follows:
Comparison of Eqs. (6) and (11) shows similarity. Next, symbols of Eq. (10) are defined as
a1 =
b1 =
a2 =
b2 =
c2 =
R1 Cgd 2 + L1 gm1 gm1 R1
(12)
L1 Cgd 2 gm1 R1
(13)
(Cgs1 + Cph )(R1 R2 + L1 R2 ) (1+gmF 2 R2 ) R1
+
Cgd 2 gm1
+
Nn2, in ≈NR2 +f 2 Cgs2 N1+f 2 (Cgs2 + Cph )2N22
(18)
4KT 4KT 4KT (γgmF 2 ) + + 2 2 R1 R2 gmF 2 R2
(19)
where NR2 =
L1 R1
(14)
and N22 =
Cgd 2 R2 (Cph R1 + Cgs1 R1 + L1 gmF 2 ) + L1 (Cgd 2 + Ceq ) (1+gmF 2 R2 ) gm1 R1
(15)
L1 R2 (Cgd 2 + Ceq )(Cgs1 + Cph ) (1+gmF 2 R2 ) gm1 R1
(16)
also N12 =
4KT (γgmF 2 ) 2 gmF 2
⎛ 4KT ⎜γgm1 + ⎝
The − 3-dB bandwidth of this circuit can be estimated as gs1 + Cph )(R1R2 + L1R2 )
(1 + gmF 2 R2) R1
⎞ 1 ⎟ R1 + sL1 ⎠
gm21
(21)
It can also be noted from [18] that
1
f−3dB ≈ (C
(20)
+
Cgd 2 gm1
+
L1 R1
gmF =
(17)
If Eq. (7) and Eq. (17) are compared, it is observed that bandwidth of FG-TIA is now extended by using shunt peaking and it consume very low voltage because of floating gate technique.
C1 + C2 g CTFG m
(22)
where Ni is the noise spectral density of transistor (where i = 1,2); gm1 and gmF2 are transconductance of a standard MOSFET (where i = 1,2) and FGMOS, respectively. In addition, here γ is channel noise factor, f is frequency, K is Boltzmann constant and T is the absolute temperature. It is clear from Eq. (18) that noise at high frequencies is dominated by transistors M1 and M2 whereas low frequency noise is usually controlled by R1 and R2. The parasitic capacitance values at the
3.3. Noise analysis The noise analysis gives another very important performance
Fig. 3. (a) Spiral inductor (b) Active realization (c) Small signal model.
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INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
U. Bansal, M. Gupta
Fig. 4. Small signal equivalent circuit of proposed circuit.
around 90 GHz. The transient response of the circuit plots output voltage variations with respect to input current. It is depicted in Fig. 6. The time period of input current pulse is 10 ps and peak to peak value is 10 mA. The output voltage is well in coordination with input and results validate that this TIA works suitably well for large input currents with quick response. Fig. 7 illustrates DC transfer characteristics of proposed circuit. The input current is varied from 0 mA to 10 mA with step size of 1 mA. The output voltage is dynamic and varies linearly in complete range. The input referred noise current density curve is shown in Fig. 8. It is clear that overall noise of this circuit is very less and at low frequency it is 1.3 nA/ Hz and reduces further at high frequencies. To demonstrate performance of the system with variable load condition CL = 0.1 pF, 0.2 pF and 0.5 pF and under temperature variations of T = − 40°, 27° and 70° AC response curves are plotted and shown in Fig. 9. The consistent results are observed with less than ± 10% variation on transimpedance. The third-orderintercept point (IIP3) is also included in simulation results as it is a key parameter for inspecting linearity of an amplifier. The result shown in Fig. 10 is the simulation curve of IIP3 at 13.5 GHz applying two tones with 10 MHz spacing. The estimated IIP3 from this curve is − 4.5 dBm and input power was varied from − 40 to 0 dBm. The labeled layout of the proposed FG-TIA is depicted in Fig. 11 and area of the circuit is calculated as 30.1 × 20.4 µm2. The presence of only one FGMOS transistor in the circuit does not increases area much. All simulation results in this work are based on pre layout simulations. However, post layout simulations results may degrade due to added parasitics but a carefully optimized layout can minimize the difference between pre layout and post layout simulations. The performance summary of proposed FG-TIA is reported in Table 2, where the simulation results of presented circuit are compared with simulation results of other recent work using same technology. An
Table 1 various circuit parameters for proposed circuit. Circuit parameter
Value
Technology Power supply Aspect ratio
0.18 µm 1V M1 = 60/0.18 M2 = 25/0.18 C1 = C2 = 34 fF CL = 0.1 pF, Cph = 0.2 pF R1 = 100 Ω, R2 = 250 Ω L1 = 1.5 nH
Capacitors Resistors Inductor
input can increase noise current hence isolation of parasitic capacitances is desired and can be done using appropriate matching network. As a general rule, the noise should be as low as possible for better performance of an amplifier [19–23]. 4. Simulation results The FG-TIA presented in this paper is a low-voltage low-power TIA, which comprises of a FGMOS, active feedback and shunt peaking network. The suggested circuit shown in Fig. 2(b) is simulated by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 µm process parameters. It employs single supply of 1 V and common gate bias voltage is 0.75 V. All simulations considered a load capacitance of 0.1 μF and photodiode capacitance of 0.2 μF. Table 1 lists the device sizes and other circuit component values. The transimpedance versus frequency curve is plotted in Fig. 5. It can be verified that using the proposed circuit − 3 dB bandwidth is enhanced and calculated as 13.5 GHz with maximum transimpedance of 37.7 dB Ω. The gain bandwidth product of the circuit is estimated
Fig. 5. Transimpedance versus frequency plot of FG-TIA.
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INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
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Fig. 6. Transient response of FG-TIA for CL = 0.1 pF.
Fig. 7. DC transfer characteristics of FG-TIA.
Fig. 8. Input referred noise versus frequency plot.
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INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
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Fig. 9. Transimpedance versus frequency plot for different values of load capacitance CL and Temperature.
Fig. 10. Simulation results of IIP3 at 13.5 GHz.
Fig. 11. Layout of proposed FG-TIA.
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INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
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461–472. [2] Oscal T.-C. Chen, Cheng-Ta Chan, Robin R.-B. Sheen, Transimpedance limit exploration and Inductor-less bandwidth extension for Designing Wideband amplifiers, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24.1 (2016) 348–352. [3] Claudio Talarico, et al., Design optimization of a transimpedance amplifier for a fiber optic receiver, Circuits Syst. Signal Process. 34.9 (2015) 2785–2800. [4] Urvashi Singh, Maneesha Gupta, Richa Srivastava, A new wideband regulated cascode amplifier with improved performance and its application, Microelectron. J. 46.8 (2015) 758–776. [5] Shahab Shahdoost, Ali Medi, Namdar Saniei, Design of low-noise transimpedance amplifiers with capacitive feedback, Analog Integr. Circuits Signal Process. 86.2 (2016) 233–240. [6] Lianxi Liu, et al., A CMOS transimpedance amplifier with high gain and wide dynamic range for optical fiber sensing system, Opt. Int. J. Light Electron Opt. 126.15 (2015) 1389–1393. [7] Mahmood Seifouri, Parviz Amiri, Majid Rakide, Design of broadband transimpedance amplifier for optical communication systems, Microelectron. J. 46.8 (2015) 679–684. [8] Behnam Analui, Ali Hajimiri, Bandwidth enhancement for transimpedance amplifiers, IEEE J. Solid-State Circuits 39.8 (2004) 1263–1270. [9] Ahlad Kumar, A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell, Analog Integr. Circuits Signal Process. 80.2 (2014) 305–314. [10] Urvashi Bansal, Maneesha Gupta, Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation, AEU-Int. J. Electron. Commun. 73 (2017) 59–67. [11] Eduard Sackinger, Walter Guggenbuhl, A high-swing, high-impedance MOS cascode circuit, IEEE J. Solid-State Circuits 25.1 (1990) 289–298. [12] Luis B. Oliveira, M. Leitão Carlos, M. Medeiros Silva, Noise performance of a regulated cascode transimpedance amplifier for radiation detectors, IEEE Trans. Circuits Syst. I: Regul. Pap. 59.9 (2012) 1841–1848. [13] Cheng Li, Samuel Palermo, A low-power 26-GHz transformer-based regulated cascode SiGe BiCMOS transimpedance amplifier, IEEE J. Solid-State Circuits 48.5 (2013) 1264–1275. [14] Zhenghao Lu, et al., Broad-band design techniques for transimpedance amplifiers, IEEE Trans. Circuits Syst. I: Regul. Pap. 54.3 (2007) 590–600. [15] Sudip Shekhar, S. Walling Jeffrey, J. Allstot David, Bandwidth extension techniques for CMOS amplifiers, IEEE J. Solid-State Circuits 41.11 (2006) 2424–2439. [16] Sung Park, Min, Hoi-Jun Yoo, 1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit ethernet applications, IEEE J. Solid-State Circuits 39.1 (2004) 112–121. [17] Liang Han, Mingyan Yu, Lu Zong, Bandwidth ehancement for transimpedance ampilfier in CMOS process, in: Proceedings of the 2010 3rd International Conference on Biomedical Engineering and Informatics, Vol. 7, IEEE, 2010. [18] Esther Rodriguez-Villegas, Low power and low voltage circuit design with the FGMOS transistor, IET 20 (2006). [19] Jaemin Shim, Taejun Yang, Jichai Jeong, Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique, Microelectron. J. 44.9 (2013) 821–826. [20] A.I.A. Galal, et al., High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology, AEU-Int. J. Electron. Commun. 66.1 (2012) 12–17. [21] San-Fu Wang, et al., A new CMOS wideband low noise amplifier with gain control, Integr. VLSI J. 44.2 (2011) 136–143. [22] Silva de Medeiros, Manuel, Luis B. Oliveira, Regulated common-gate transimpedance amplifier designed to operate with a silicon photo-multiplier at the input, IEEE Trans. Circuits Syst. I: Regul. Pap. 3 (61) (2014) 725–735. [23] Reyes Barranca, Mario Alfredo, et al., Using a floating-gate MOS transistor as a transducer in a MEMS gas sensing system, Sensors 10.11 (2010) 10413–10434. [24] G. Royo, et al. CMOS transimpedance amplifier with controllable gain for RF overlay, in: Proceedings of the 12th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), 2016. IEEE, 2016.
Table 2 Performance comparison of various conventional and FG-TIA.
Year Technology (µm) Supply Voltage (V) Power consumption(mW) Transimpedance (dB Ω) Bandwidth (GHz) FOM (GHz Ω/mW)
[3]
[6]
[7]
[24]
This work (FG-TIA)
2015 0.18 1.8 13.5 78.34 2.21 12.82
2015 0.18 1.8 8.1 87.8 1.2 13
2015 0.18 1.8 – 50 9 –
2016 0.18 1.8 27 48–56 1.5 3.11
2017 0.18 1 1.1 37.7 13.5 462
expression of Figure of Merit (FOM) similar to [1,3] is included here to exhibit competence of proposed circuit and given as: Transimpedance . f−3dB(GHz . Ω) FOM = power consumption(mW) It is evident that power supply requirement is minimum in this work. Many of the circuit parameters like bandwidth and noise figure have been improved to a great extent. The transimpedance offered in [3,6,7] is very high but so is the power consumption. It is noticeable that calculated FOM is best among other compared circuit and the power consumption is least in proposed FG-TIA. Thus this TIA is a suitable choice for low-voltage low-power wide band operation. 5. Conclusion This work presents a new CMOS realization of TIA. It not only employs a FGMOS transistor but also active feedback and frequency compensation. This unique permutation enables low-power low-voltage operation of TIA a success along with improved bandwidth and satisfactory performance. Since TIA is very first stage of an optical receiver so its role is very crucial and it is tried best here to deal with sensitivity, noise and bandwidth in most optimized way. Suggested FGTIA works in analog mode and is also suitable for current mirrors/ amplifiers. As a future trend higher bandwidth and transimpedance could be achieved with possible modifications. Acknowledgement The help of Mr. Saif Mohammad in the generation of layout of proposed circuit is gracefully acknowledged. His encouragement to execute this idea helped a lot. Ms. Anjana Das is also thanked for her kind support. References [1] Zhenghao Lu, et al., Design of a CMOS broadband transimpedance amplifier with active feedback, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18.3 (2010)
7
Contents lists available at ScienceDirect
INTEGRATION, the VLSI journal journal homepage: www.elsevier.com/locate/vlsi
High bandwidth transimpedance amplifier using FGMOS for low voltage operation Urvashi Bansal, Maneesha Gupta
⁎
Division of ECE, Netaji Subhas Institute of Technology, New Delhi 110078, India
A R T I C L E I N F O
A BS T RAC T
Keywords: Analog circuits CMOS FGMOS Frequency compensation Shunt peaking TIA
In this paper a novel CMOS design of transimpedance amplifier (TIA) suitable for low-voltage low-power application is presented. A floating gate metal oxide semiconductor (FGMOS) transistor is used here in common source configuration to provide active feedback along with a standard MOSFET which acts as input stage of the circuit. Main intend of this work is to minimize supply requirement with increased linearity. The circuit of TIA presented in this paper works only at 1 V supply with small power consumption of 1.1 mW. One of the popular frequency compensation techniques is shunt peaking technique. It is employed here to extend bandwidth. The transimpedance output and − 3 dB bandwidth of proposed circuit are 37.7 dB Ohms and 13.5 GHz, respectively. The input impedance and transfer function is evaluated using mathematical analysis and small signal model of circuit. This is observed that results are improved as compared to well known regulated common gate (RC-G) amplifier.
1. Introduction The first and very important stage of every optical receiver is TIA. It not only transfers input current to an amplified output voltage to be used by subsequent stages but also commands overall system performance in terms of sensitivity, noise figure and bandwidth. Nowadays, the CMOS technology based TIAs are getting very popular due to their low cost, low volume and relaxed sensitivity requirements with comparable performance parameters [1–3]. Most of these amplifiers support current mode operation and exploit common gate configuration or shunt feedback topology [4–6]. The key issue is to handle noise performance, offered bandwidth and sensitivity requirement altogether in optimized way [7,8]. In addition, the low-voltage low-power analog circuits [9,10] demand that the circuit characteristics should not be degraded while minimizing the supply requirements. The conventional RC-G [11–13] offers low input impedance and thereby limits the large input capacitance effect. Such circuits offer extended bandwidth but their supply requirement is quite high. In such case, there is need of a suitable TIA which offers high bandwidth for low-voltage low-power circuits efficiently. The paper presented here suggests a novel design of TIA based on FGMOS called FG-TIA. The input stage of circuit is a common gate MOS transistor and active feedback is provided via common source configuration of FGMOS transistor. In order to improve frequency response of presented circuit, shunt peaking method is employed here among various prevalent bandwidth exten-
⁎
sion techniques [14,15]. The suggested circuit requires only 1 V supply with small power consumption of 1.1 mW. The paper is organized as follows. In Section 2, functioning principle of FGMOS transistor is described in brief. The proposed TIA circuit and working model is explained in Section 3. Then in same section, transfer function and impedance of proposed circuit is derived. Section 4 includes all simulation results and Section 5 concludes the paper. 2. FGMOS transistor A conventional MOSFET is transformed into FGMOS transistor when a polysilicon layer is deposited first to form floating gate and followed by deposition of secondary polysilicon layer to provide multiple input gates (G1,G2…. Gn). FGMOS transistor is analogous to MOSFET in operation with the fact that it dissipates less power and has tunable means to work below the operational limits of supply voltage level without demeaning any other characteristics. Fig. 1(a) and (b) shows a 2-input P-channel FGMOS transistor symbol and its equivalent circuit, respectively. In a FGMOS transistor, the effective gate to source voltage (VGSeff) is estimated by [10].
VGSeff =
CGD VDS + C GBVBS + C1VbS + C2 V2s + Q FG CTFG
Corresponding author. E-mail addresses: [email protected] (U. Bansal), [email protected] (M. Gupta).
http://dx.doi.org/10.1016/j.vlsi.2017.09.001 Received 3 May 2017; Received in revised form 31 July 2017; Accepted 2 September 2017 0167-9260/ © 2017 Published by Elsevier B.V.
Please cite this article as: Bansal, U., INTEGRATION the VLSI journal (2017), http://dx.doi.org/10.1016/j.vlsi.2017.09.001
(1)
INTEGRATION the VLSI journal xxx (xxxx) xxx–xxx
U. Bansal, M. Gupta
In Fig. 2(a), input signal is applied at drain terminal of M1 and amplified further. A local feedback is formed via M2 and R2 which actually trim down input impedance by the amount of its own voltage gain. The input impedance of conventional circuit [16] is derived using small signal analysis and given as:
zin (0)≅
1 gm1 (1+gm2 R2 )
(6)
where (1 + gm2R2) represents gain of local feedback stage and bandwidth of the input stage [16] is derived as:
f−3dB =
where QFG stands for the amount of charge trapped at floating gate (FG) and input voltages are Vin1 = Vb and Vin2 = V2. The connected capacitors are indicated as C1 and C2. The parasitic capacitances CGD, CGS and CGB are present between FG and other terminals. The term CTFG signifies to the total capacitance seen by FG and is calculated as CTFG = C1 + C2 + CGD + CGS + CGB. Similarly the voltage at drain (D), bulk (B), bias gate (G1) and signal gate (G2) with respect to source are denoted by VDS, VBS, VbS and V2S, respectively. The expression of drain current (ID) for a FGMOS operating in saturation region, can be given as:
gm (VGSeff − Vth)2 2
(2)
where Vth represents threshold voltage and gm is the transconductance parameter. Moreover, if it is assumed that parasitic capacitances are small and the selected value of input capacitances is such that their total is very high as match up to the parasitic capacitances than CTFG ≈ C1 + C2 and now from Eqs. (1) and (2), ID can be expressed as:
ID =
⎞2 gm ⎛ C1VbS + C2 V2s − Vth⎟ ⎜ ⎠ 2 ⎝ CTFG
z= (3)
g m ⎛ C2 ⎞ ⎜ ⎟ (V2s − V′th)2 2 ⎝ CTFG ⎠
1+RG sCgs gm + sCgs
(4)
Z (s ) = where the new threshold voltage V′th can be given as:
⎤ ⎞⎡ ⎛C C V′th = ⎜ TFG ⎟ ⎢Vth − 1 VbS⎥ ⎝ C2 ⎠ ⎣ CTFG ⎦
(8)
This circuit exploits inductor in shunt peaking style. Furthermore, the transimpedance function of a shunt peaked network [15] can be expressed as:
Eq. (3) can be rewritten as:
ID =
(7)
where αi is low frequency gain (i = 2,4) of following stages, Cf is parasitic capacitance of feedback resistor Rf, Cgd1 is gate to drain terminal capacitance and Cg2 is gate capacitance of M2. The Fig. 2(b) depicts CMOS realization of proposed FG-TIA circuit. This circuit uses standard MOS transistor M1 in common gate configuration as its input and exploits common source active feedback to reduce impedance via FGMOS transistor M2. The presence of FGMOS transistor enables low voltage operation of the circuit. In order to optimize operating bandwidth, shunt peaking technique is exercised. In this technique, an inductor L is connected in series with load resistor. The main function of inductor [15] is to introduce a zero and shunt the output capacitor. The circuit can also make use of an active inductor [17] instead of spiral inductor as latter one occupies large area, gives high parasitic capacitance and is difficult to integrate. Fig. 3(a), (b) and (c) show spiral inductor, its active realization and simplified small signal model. Here L is ideal inductor and R is the resistance of winding, rest of the symbols has their usual meaning [17]. The role of active inductor is same as for the spiral inductor. If value of Cgd, Cds and gds are considered small then overall impedance [17] can be approximated as:
Fig. 1. (a) Symbol of two input P-channel FGMOS. (b) FGMOS equivalent circuit.
ID =
1 ⎡ ⎛ Cgd1 + Cg2 ⎞ ⎤ 2πRf ⎢Cf + ⎜ 1 + α g R α ⎟ ⎥ 2 m1 3 4 ⎠ ⎦ ⎝ ⎣
vout 1 R + sL = ∣∣ (R+sCL ) = iin sCL 1+sRCL + s 2LCL
(9)
where all the symbols are typical [15]. It is clear from Eq. (9) that insertion of inductor will extend bandwidth.
(5)
It is apparent from Eq. (5) that appropriate choice of bias voltage and capacitance ratios can electronically control the threshold voltage of FGMOS transistor. This fact makes it more clear and purposeful to use FGMOS transistor in low voltage and programmable electronic devices.
3.2. Small signal analysis The small signal equivalent circuit of the proposed circuit is given in Fig. 4. Here it is assumed that parasitic capacitances are small and channel output resistance is very high for both transistors. The small signal transimpedance function of proposed TIA can be expressed by following equation.
3. Proposed TIA In view of the fact that the input signal of a TIA is current and output signal is voltage, it can be simply called a current to voltage converter and finds major applications in many areas of electronics and communication engineering.
Z (s ) =
vout 1+a1 s + b1 s 2 = Zi iin 1+a2 s + b2 s 2 + c2 s 3
(10)
In Fig. 4, iph and Cph are photocurrent and associated capacitance, respectively. The transconductance parameter of standard MOSFET is C +C gm1 and FGMOS is gmF2. It is worth noting that gmF = C1 2 gm . The TFG capacitances C1 and C2 are connected at FG and other symbols have their typical meaning. The symbol Zi(0) denotes low frequency transimpedance function and can be expressed as
3.1. Circuit description The conventional RC-G circuit [16] and the proposed FG-TIA circuit is shown in Fig. 2(a) and 2(b), respectively. Both circuits include parasitic capacitance of photodiode. The role of photodiode is to transform optical signal into electrical signal.
Z i (0) =
2
R2 = R2 ∣∣ 1/ gmF 2 1 +gmF 2 R2
(11)
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Fig. 2. (a) Conventional RC-GTIA circuit [16]. (b) Proposed FG-TIA circuit.
parameter for a TIA. The bit error rate (BER) and sensitivity of the whole optical receiver front-end is directly affected by the input referred noise spectral density. The investigation results of the equivalent input noise current characteristics can be deduced as follows:
Comparison of Eqs. (6) and (11) shows similarity. Next, symbols of Eq. (10) are defined as
a1 =
b1 =
a2 =
b2 =
c2 =
R1 Cgd 2 + L1 gm1 gm1 R1
(12)
L1 Cgd 2 gm1 R1
(13)
(Cgs1 + Cph )(R1 R2 + L1 R2 ) (1+gmF 2 R2 ) R1
+
Cgd 2 gm1
+
Nn2, in ≈NR2 +f 2 Cgs2 N1+f 2 (Cgs2 + Cph )2N22
(18)
4KT 4KT 4KT (γgmF 2 ) + + 2 2 R1 R2 gmF 2 R2
(19)
where NR2 =
L1 R1
(14)
and N22 =
Cgd 2 R2 (Cph R1 + Cgs1 R1 + L1 gmF 2 ) + L1 (Cgd 2 + Ceq ) (1+gmF 2 R2 ) gm1 R1
(15)
L1 R2 (Cgd 2 + Ceq )(Cgs1 + Cph ) (1+gmF 2 R2 ) gm1 R1
(16)
also N12 =
4KT (γgmF 2 ) 2 gmF 2
⎛ 4KT ⎜γgm1 + ⎝
The − 3-dB bandwidth of this circuit can be estimated as gs1 + Cph )(R1R2 + L1R2 )
(1 + gmF 2 R2) R1
⎞ 1 ⎟ R1 + sL1 ⎠
gm21
(21)
It can also be noted from [18] that
1
f−3dB ≈ (C
(20)
+
Cgd 2 gm1
+
L1 R1
gmF =
(17)
If Eq. (7) and Eq. (17) are compared, it is observed that bandwidth of FG-TIA is now extended by using shunt peaking and it consume very low voltage because of floating gate technique.
C1 + C2 g CTFG m
(22)
where Ni is the noise spectral density of transistor (where i = 1,2); gm1 and gmF2 are transconductance of a standard MOSFET (where i = 1,2) and FGMOS, respectively. In addition, here γ is channel noise factor, f is frequency, K is Boltzmann constant and T is the absolute temperature. It is clear from Eq. (18) that noise at high frequencies is dominated by transistors M1 and M2 whereas low frequency noise is usually controlled by R1 and R2. The parasitic capacitance values at the
3.3. Noise analysis The noise analysis gives another very important performance
Fig. 3. (a) Spiral inductor (b) Active realization (c) Small signal model.
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Fig. 4. Small signal equivalent circuit of proposed circuit.
around 90 GHz. The transient response of the circuit plots output voltage variations with respect to input current. It is depicted in Fig. 6. The time period of input current pulse is 10 ps and peak to peak value is 10 mA. The output voltage is well in coordination with input and results validate that this TIA works suitably well for large input currents with quick response. Fig. 7 illustrates DC transfer characteristics of proposed circuit. The input current is varied from 0 mA to 10 mA with step size of 1 mA. The output voltage is dynamic and varies linearly in complete range. The input referred noise current density curve is shown in Fig. 8. It is clear that overall noise of this circuit is very less and at low frequency it is 1.3 nA/ Hz and reduces further at high frequencies. To demonstrate performance of the system with variable load condition CL = 0.1 pF, 0.2 pF and 0.5 pF and under temperature variations of T = − 40°, 27° and 70° AC response curves are plotted and shown in Fig. 9. The consistent results are observed with less than ± 10% variation on transimpedance. The third-orderintercept point (IIP3) is also included in simulation results as it is a key parameter for inspecting linearity of an amplifier. The result shown in Fig. 10 is the simulation curve of IIP3 at 13.5 GHz applying two tones with 10 MHz spacing. The estimated IIP3 from this curve is − 4.5 dBm and input power was varied from − 40 to 0 dBm. The labeled layout of the proposed FG-TIA is depicted in Fig. 11 and area of the circuit is calculated as 30.1 × 20.4 µm2. The presence of only one FGMOS transistor in the circuit does not increases area much. All simulation results in this work are based on pre layout simulations. However, post layout simulations results may degrade due to added parasitics but a carefully optimized layout can minimize the difference between pre layout and post layout simulations. The performance summary of proposed FG-TIA is reported in Table 2, where the simulation results of presented circuit are compared with simulation results of other recent work using same technology. An
Table 1 various circuit parameters for proposed circuit. Circuit parameter
Value
Technology Power supply Aspect ratio
0.18 µm 1V M1 = 60/0.18 M2 = 25/0.18 C1 = C2 = 34 fF CL = 0.1 pF, Cph = 0.2 pF R1 = 100 Ω, R2 = 250 Ω L1 = 1.5 nH
Capacitors Resistors Inductor
input can increase noise current hence isolation of parasitic capacitances is desired and can be done using appropriate matching network. As a general rule, the noise should be as low as possible for better performance of an amplifier [19–23]. 4. Simulation results The FG-TIA presented in this paper is a low-voltage low-power TIA, which comprises of a FGMOS, active feedback and shunt peaking network. The suggested circuit shown in Fig. 2(b) is simulated by using Mentor Graphics Eldo simulation tool with TSMC CMOS 0.18 µm process parameters. It employs single supply of 1 V and common gate bias voltage is 0.75 V. All simulations considered a load capacitance of 0.1 μF and photodiode capacitance of 0.2 μF. Table 1 lists the device sizes and other circuit component values. The transimpedance versus frequency curve is plotted in Fig. 5. It can be verified that using the proposed circuit − 3 dB bandwidth is enhanced and calculated as 13.5 GHz with maximum transimpedance of 37.7 dB Ω. The gain bandwidth product of the circuit is estimated
Fig. 5. Transimpedance versus frequency plot of FG-TIA.
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Fig. 6. Transient response of FG-TIA for CL = 0.1 pF.
Fig. 7. DC transfer characteristics of FG-TIA.
Fig. 8. Input referred noise versus frequency plot.
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Fig. 9. Transimpedance versus frequency plot for different values of load capacitance CL and Temperature.
Fig. 10. Simulation results of IIP3 at 13.5 GHz.
Fig. 11. Layout of proposed FG-TIA.
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461–472. [2] Oscal T.-C. Chen, Cheng-Ta Chan, Robin R.-B. Sheen, Transimpedance limit exploration and Inductor-less bandwidth extension for Designing Wideband amplifiers, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24.1 (2016) 348–352. [3] Claudio Talarico, et al., Design optimization of a transimpedance amplifier for a fiber optic receiver, Circuits Syst. Signal Process. 34.9 (2015) 2785–2800. [4] Urvashi Singh, Maneesha Gupta, Richa Srivastava, A new wideband regulated cascode amplifier with improved performance and its application, Microelectron. J. 46.8 (2015) 758–776. [5] Shahab Shahdoost, Ali Medi, Namdar Saniei, Design of low-noise transimpedance amplifiers with capacitive feedback, Analog Integr. Circuits Signal Process. 86.2 (2016) 233–240. [6] Lianxi Liu, et al., A CMOS transimpedance amplifier with high gain and wide dynamic range for optical fiber sensing system, Opt. Int. J. Light Electron Opt. 126.15 (2015) 1389–1393. [7] Mahmood Seifouri, Parviz Amiri, Majid Rakide, Design of broadband transimpedance amplifier for optical communication systems, Microelectron. J. 46.8 (2015) 679–684. [8] Behnam Analui, Ali Hajimiri, Bandwidth enhancement for transimpedance amplifiers, IEEE J. Solid-State Circuits 39.8 (2004) 1263–1270. [9] Ahlad Kumar, A 97 dB 400 MHz rail to rail fully differential opamp based on split length FGMOS-MOS cell, Analog Integr. Circuits Signal Process. 80.2 (2014) 305–314. [10] Urvashi Bansal, Maneesha Gupta, Two stage class AB-AB amplifier using FGMOS for low voltage operation and SSF for frequency compensation, AEU-Int. J. Electron. Commun. 73 (2017) 59–67. [11] Eduard Sackinger, Walter Guggenbuhl, A high-swing, high-impedance MOS cascode circuit, IEEE J. Solid-State Circuits 25.1 (1990) 289–298. [12] Luis B. Oliveira, M. Leitão Carlos, M. Medeiros Silva, Noise performance of a regulated cascode transimpedance amplifier for radiation detectors, IEEE Trans. Circuits Syst. I: Regul. Pap. 59.9 (2012) 1841–1848. [13] Cheng Li, Samuel Palermo, A low-power 26-GHz transformer-based regulated cascode SiGe BiCMOS transimpedance amplifier, IEEE J. Solid-State Circuits 48.5 (2013) 1264–1275. [14] Zhenghao Lu, et al., Broad-band design techniques for transimpedance amplifiers, IEEE Trans. Circuits Syst. I: Regul. Pap. 54.3 (2007) 590–600. [15] Sudip Shekhar, S. Walling Jeffrey, J. Allstot David, Bandwidth extension techniques for CMOS amplifiers, IEEE J. Solid-State Circuits 41.11 (2006) 2424–2439. [16] Sung Park, Min, Hoi-Jun Yoo, 1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit ethernet applications, IEEE J. Solid-State Circuits 39.1 (2004) 112–121. [17] Liang Han, Mingyan Yu, Lu Zong, Bandwidth ehancement for transimpedance ampilfier in CMOS process, in: Proceedings of the 2010 3rd International Conference on Biomedical Engineering and Informatics, Vol. 7, IEEE, 2010. [18] Esther Rodriguez-Villegas, Low power and low voltage circuit design with the FGMOS transistor, IET 20 (2006). [19] Jaemin Shim, Taejun Yang, Jichai Jeong, Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique, Microelectron. J. 44.9 (2013) 821–826. [20] A.I.A. Galal, et al., High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology, AEU-Int. J. Electron. Commun. 66.1 (2012) 12–17. [21] San-Fu Wang, et al., A new CMOS wideband low noise amplifier with gain control, Integr. VLSI J. 44.2 (2011) 136–143. [22] Silva de Medeiros, Manuel, Luis B. Oliveira, Regulated common-gate transimpedance amplifier designed to operate with a silicon photo-multiplier at the input, IEEE Trans. Circuits Syst. I: Regul. Pap. 3 (61) (2014) 725–735. [23] Reyes Barranca, Mario Alfredo, et al., Using a floating-gate MOS transistor as a transducer in a MEMS gas sensing system, Sensors 10.11 (2010) 10413–10434. [24] G. Royo, et al. CMOS transimpedance amplifier with controllable gain for RF overlay, in: Proceedings of the 12th Conference on Ph. D. Research in Microelectronics and Electronics (PRIME), 2016. IEEE, 2016.
Table 2 Performance comparison of various conventional and FG-TIA.
Year Technology (µm) Supply Voltage (V) Power consumption(mW) Transimpedance (dB Ω) Bandwidth (GHz) FOM (GHz Ω/mW)
[3]
[6]
[7]
[24]
This work (FG-TIA)
2015 0.18 1.8 13.5 78.34 2.21 12.82
2015 0.18 1.8 8.1 87.8 1.2 13
2015 0.18 1.8 – 50 9 –
2016 0.18 1.8 27 48–56 1.5 3.11
2017 0.18 1 1.1 37.7 13.5 462
expression of Figure of Merit (FOM) similar to [1,3] is included here to exhibit competence of proposed circuit and given as: Transimpedance . f−3dB(GHz . Ω) FOM = power consumption(mW) It is evident that power supply requirement is minimum in this work. Many of the circuit parameters like bandwidth and noise figure have been improved to a great extent. The transimpedance offered in [3,6,7] is very high but so is the power consumption. It is noticeable that calculated FOM is best among other compared circuit and the power consumption is least in proposed FG-TIA. Thus this TIA is a suitable choice for low-voltage low-power wide band operation. 5. Conclusion This work presents a new CMOS realization of TIA. It not only employs a FGMOS transistor but also active feedback and frequency compensation. This unique permutation enables low-power low-voltage operation of TIA a success along with improved bandwidth and satisfactory performance. Since TIA is very first stage of an optical receiver so its role is very crucial and it is tried best here to deal with sensitivity, noise and bandwidth in most optimized way. Suggested FGTIA works in analog mode and is also suitable for current mirrors/ amplifiers. As a future trend higher bandwidth and transimpedance could be achieved with possible modifications. Acknowledgement The help of Mr. Saif Mohammad in the generation of layout of proposed circuit is gracefully acknowledged. His encouragement to execute this idea helped a lot. Ms. Anjana Das is also thanked for her kind support. References [1] Zhenghao Lu, et al., Design of a CMOS broadband transimpedance amplifier with active feedback, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 18.3 (2010)
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